Prosecution Insights
Last updated: April 19, 2026
Application No. 17/826,181

MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) DEVICE and fabrication method thereof

Non-Final OA §102§103
Filed
May 27, 2022
Examiner
BLACKWELL, ASHLEY NICOLE
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Vanguard International Semiconductor Corporation
OA Round
3 (Non-Final)
98%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 98% — above average
98%
Career Allow Rate
52 granted / 53 resolved
+30.1% vs TC avg
Minimal +3% lift
Without
With
+2.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
33 currently pending
Career history
86
Total Applications
across all art units

Statute-Specific Performance

§103
61.1%
+21.1% vs TC avg
§102
23.5%
-16.5% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 53 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 3, 4, 8, and 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/16/2025. Response to Arguments A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/7/2025 has been entered. Applicant’s arguments, see pages 7-9, filed 12/07/2025, with respect to the rejection(s) of claims 1-2, 5-7 and 9-11 under 102 and 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Duqi et al. (US 20190210868 A1). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 6, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tseng et al. (US 20190062153 A1). Claims 1, 2, 5, 6, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 20190062153 A1) in view of Duqi et al. (US 20190210868 A1). Regarding claim 1, Tseng discloses a micro-electro-mechanical system (MEMS) device, comprising: a first substrate (106); ([0017], Fig.1A/2A) an interconnect layer (108) disposed on the first substrate (106), wherein the interconnect layer (104 and 118) comprises a plurality of conductive layers (110) and a plurality of dielectric layers (112), and the plurality of conductive layers (110) and the plurality of dielectric layers are (112) stacked alternately ([0017], Fig. 1A/2A) a MEMS device layer (124) bonded on the interconnect layer (108), wherein the MEMS device layer (124) comprises a proof mass (122); ([0018], Fig. 1A/2A) a stopper (annotated below) disposed directly under the proof mass (122) and spaced apart from the proof mass (122), wherein the stopper(annotated below) is formed as an integrated body and surrounded by a portion of the interconnect layer (annotated below), and the stopper (annotated below) comprises: a bottom portion (128/202) constructed of one of the plurality of conductive layers (per [0020]); and a second substrate (126) including a cavity (120) and bonded on the MEMS device layer (124). (Fig.1A/2A) PNG media_image1.png 684 860 media_image1.png Greyscale Tseng does not disclose: a silicon-based layer disposed on and electrically coupled to the bottom portion; However, Duqi discloses: a silicon-based layer (312) disposed on and electrically coupled to the bottom portion (311); ([0120], Fig. 16D) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Tseng and Duqi to have a silicon-based layer disposed on and electrically coupled to the bottom portion in order to “allow the sensitive portion 212, 512 of the MEMS device 260, 560 to be protected against mechanical shocks, thus increasing the robustness of the device itself.” (Duqi, [0130]) Regarding claim 2, Tseng discloses the MEMS device of claim 1, wherein the interconnect layer (108) comprises a concave portion (118) surrounded by the portion of the interconnect layer (annotated above), and the stopper (annotated above) is disposed in the concave portion (118).(Fig. 2A) Regarding claims 5, Duqi discloses the MEMS device of claim 1, wherein the silicon-based layer comprises polysilicon (per [0120]), amorphous silicon or single crystal silicon. (Fig. 16D) It would have been obvious to one skilled in the art before the effective filing date for the silicon-based layer comprises polysilicon for similar reasons stated above. Regarding claim 6, Tseng discloses the MEMS device of claim 1, wherein the MEMS device layer (124) further comprises a protruding portion (annotated below) towards the interconnect layer (108) and a conductive layer (annotated below) on the protruding portion (annotated below), and the MEMS device layer (124) is bonded with a top conductive layer (topmost 110) of the interconnect layer (108) through the conductive layer (topmost 110) and the protruding portion (annotated below). (Fig.1A/2A) PNG media_image2.png 684 731 media_image2.png Greyscale Regarding claim 9, Tseng discloses the MEMS device of claim 1, wherein the bottom portion of the stopper (128/202) is constructed of a portion of a top conductive layer (topmost 110) of the interconnect layer (108). (Fig. 1A/2A) Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 20190062153 A1) in view of Duqi et al. (US 20190210868 A1) as applied to claim 1 above, and further in view of Wang et al. (US 20210087055 A1) Regarding claim 7, Tseng in view of Duqi disclose the MEMS device of claim 1. Tseng in view of Duqi do not disclose wherein the MEMS device layer further comprises a suspension beam adjacent to the proof mass, and the suspension beam and the proof mass are disposed corresponding to the cavity of the second substrate. However, Wang discloses: the MEMS device layer (124) further comprises a suspension beam (inside 138, annotated below) adjacent to the proof mass (inside 138, annotated below), and the suspension beam (inside 138, annotated below), and the proof mass (inside 138, annotated below), are disposed corresponding to the cavity (140) of the second substrate (128). (Fig.1) PNG media_image3.png 479 821 media_image3.png Greyscale It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Tseng, Duqi and Wang for the MEMS device layer further comprises a suspension beam adjacent to the proof mass, and the suspension beam and the proof mass are disposed corresponding to the cavity of the second substrate in order “to prevent the one or more first and/or second moveable elements 134, 138 from becoming stuck to the passivation structure 118” (Wang, [0018]). Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 20190062153 A1) in view of Duqi et al. (US 20190210868 A1) as applied to claim 9 above, and further in view of Cheng (US 20170203962 A1) and Wang et al. (US 20210087055 A1). Regarding claim 10, Tseng discloses the MEMS device of claim 9. Tseng does not disclose wherein the interconnect layer further comprises a top dielectric layer disposed on the top conductive layer and a passivation layer disposed on the top dielectric layer, and the stopper further comprises a portion of the top dielectric layer and a portion of the passivation layer stacked in sequence on the bottom portion, and a through hole in the portion of the top dielectric layer and the portion of the passivation layer, wherein the silicon-based layer is conformally disposed on the portion of the passivation layer and in the through hole. However, Cheng discloses: the interconnect layer (102) further comprises a top dielectric layer (114) disposed on the top conductive layer (138) and a passivation layer (140) disposed on the top dielectric layer (114), and the stopper (110) further comprises a portion of the top dielectric layer (114) and a portion of the passivation layer (140) stacked in sequence on the bottom portion (138), and a through hole (annotated below) in the portion of the top dielectric layer (114) and the portion of the passivation layer (140), ([0019]-[0020], Fig. 2) PNG media_image4.png 452 792 media_image4.png Greyscale It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Tseng and Cheng for the interconnect layer further comprises a top dielectric layer disposed on the top conductive layer and a passivation layer disposed on the top dielectric layer, and the stopper further comprises a portion of the top dielectric layer and a portion of the passivation layer stacked in sequence on the bottom portion, and a through hole in the portion of the top dielectric layer and the portion of the passivation layer in order to protect underlying layers from damage during formation of the MEMS package. (Cheng, [0019]) Tseng in view of Cheng do not disclose: wherein the silicon-based layer is conformally disposed on the portion of the passivation layer and in the through hole. However, Wang discloses: the silicon-based layer (122) is conformally disposed on the portion of the passivation layer (118) and in the through hole (annotated below). (Fig. 1) PNG media_image5.png 492 782 media_image5.png Greyscale It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Tseng, Cheng and Wang for the silicon-based layer is conformally disposed on the portion of the passivation layer and in the through hole in order “to prevent the one or more first and/or second moveable elements 134, 138 from becoming stuck to the passivation structure 118” (Wang, [0018]). Regarding claim 11, Wang discloses the MEMS device of claim 10, wherein the stopper (132) further comprises a barrier layer (132a) conformally disposed between the silicon-based layer (122) and the portion of the passivation layer (118), and between the silicon-based layer (122) and the bottom portion (116a), and the barrier layer (132a) comprises Ti (Wang, per [0020], “116a may be or comprise a reactive material (e.g., titanium)” and per [0030], “ 132a may, for example, be or comprise titanium,” and hence the examiner has met the limitation), TiN or a combination thereof. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

May 27, 2022
Application Filed
Mar 18, 2025
Non-Final Rejection — §102, §103
Jun 17, 2025
Response Filed
Sep 04, 2025
Final Rejection — §102, §103
Dec 07, 2025
Request for Continued Examination
Dec 17, 2025
Response after Non-Final Action
Jan 06, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Apr 07, 2026
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2y 5m to grant Granted Mar 24, 2026
Patent 12575099
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 10, 2026
Patent 12550324
THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
98%
Grant Probability
99%
With Interview (+2.9%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 53 resolved cases by this examiner. Grant probability derived from career allow rate.

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