Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The information disclosure statement (IDS) submitted on 5/30/2023 was filed after the mailing date of the application on 05/27/2022. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 14 objected to because of the following informalities: it should read "The semiconductor processing method of claim 10, [wherein] a pressure is maintained at less than or about 20 Torr during operations i) and ii).". Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 10, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Cui et al. (US 20190214230) (hereinafter Cui) and Ajaykumar et al. (First Demonstration of Ruthenium and Molybdenum...) (hereinafter Ajauykumar).
Regarding claim 1, Cui discloses in figures 4 and 5 a semiconductor processing method comprising:
providing an oxygen-containing precursor (step 405 of fig. 4) to a semiconductor processing chamber (200) [0032], wherein a substrate (515) [0048 is positioned within the semiconductor processing chamber (200), wherein the substrate (515) comprises:
a trench (505) [0050] formed between columns (510) [0048];
and metal regions (525) [0048] in a plurality of recesses (527) [0048] formed in at least one of the columns (510), wherein at least two of the metal regions (horizontal portions of 525 in recess 527) (see marked up figure 5A below) are connected by a metal-containing first liner (exposed portions of 525) [0048] (see marked up figure 5A below) formed on at least a portion of a sidewall (540) of the trench (505);
forming a plasma of the oxygen-containing precursor in the semiconductor processing chamber (operation 410, figure 4) [0050];
contacting (operation 420, figure 4) [0050] the metal-containing first liner (vertical portion of 525) with plasma effluents of the oxygen-containing precursor [0050], wherein the contacting forms an oxidized portion of metal (555) [0050] on the metal-containing first liner (exposed portions of 525);
providing a halide precursor to the semiconductor processing chamber (operation 425, figure 4) [0059]; and
contacting the oxidized portion of metal (555) with plasma effluents of the halide precursor [0059], wherein the contacting removes the oxidized portion of metal (555) from the sidewall of the trench [0060].
Cui does not disclose wherein the metal regions (525) are molybdenum (Cui discloses wherein the metal regions comprise tungsten (W)).
However, Ajaykumar discloses using molybdenum as the metal regions in 3d NAND structures (figure 3b).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Cui to substitute tungsten [0050] as their metal region (525) for molybdenum in order to decrease the resistivity of these regions in light of the disclosure of Ajaykumar (Abstract).
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Marked Up Figure 5A for Clarification Regarding claim 1
Regarding claim 2, Cui as previously modified teaches the semiconductor processing method of claim 1 wherein the oxygen-containing precursor (operation 405, figure 4) [0050] comprises ozone [0057].
Regarding claim 3, Cui as previously modified teaches the semiconductor processing method of claim 1 wherein the oxygen-containing precursor (operation 405, figure 4) [0050] is formed at a plasma power less than or about 2,000 W [0055].
Regarding claim 4, Cui as previously modified teaches the semiconductor processing method of claim 1 wherein the oxidized portion of [metal] (555) [0050] is characterized by a thickness of less than or about 100 angstroms [0053].
As applied to claim 1, replacing tungsten with molybdenum would have been obvious to a person of ordinary skill in the art prior to the effective filing date.
Regarding claim 5, Cui as previously modified teaches the semiconductor processing method of claim 1 wherein the halide precursor comprises a fluorine-containing precursor [0059].
Regarding claim 6, Cui as previously modified teaches the semiconductor processing method of claim 1 wherein the fluorine-containing precursor comprises tungsten hexafluoride [0059].
Regarding claim 7, Cui as previously modified teaches the semiconductor processing method of claim 1 wherein forming the oxidized portion of [tungsten] produces a layer of [tungsten] oxide (555) [0050] formed along a sidewall (540) [0059] of the trench (505) [0059], and wherein a thickness of the layer of [tungsten] oxide (555) proximate an upper region of the trench (505) differs in thickness from the layer of [tungsten] oxide proximate a lower region of the trench (505) by less than or about 30% [0059].
As applied to claim 1, replacing tungsten with molybdenum would have been obvious to a person of ordinary skill in the art prior to the effective filing date.
Regarding claim 10, Cui discloses a semiconductor processing method comprising:
i) forming plasma effluents of an oxygen-containing precursor (operation 410, figure 4) [0050];
ii) contacting a metal-containing first liner (see marked up figure 5A in regard to claim 1 above) (exposed portions of 525) [0048] connecting at least two [metal]-containing metal regions (525) [0048] arranged within a plurality of recesses (527) [0062] defined by at least one column (510) [0048] of a trench (505) [0048] with plasma effluents of the oxygen-containing precursor [0050], wherein the contacting forms an oxidized portion of [metal] (555) [0050] on the [metal]-containing first liner (exposed portions of 525);
iii) forming plasma effluents of a fluorine-containing precursor (operation 425, figure 4) [0059]; and
iv) contacting the oxidized portion of [metal] (555) with plasma effluents of the fluorine-containing precursor [0059], wherein the contacting removes the oxidized portion (555) of [metal] [0059-0061].
Cui does not disclose wherein the metal regions (525) are molybdenum (Cui discloses wherein the metal regions comprise tungsten (W)).
However, Ajaykumar discloses using molybdenum as the metal regions in 3d NAND structures (figure 3b) as a replacement for tungsten (Abstract).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Cui to substitute tungsten [0050] as their metal region (525) for molybdenum in order to decrease the resistivity of these regions in light of the disclosure of Ajaykumar (Abstract).
Regarding claim 12, Cui as previously modified teaches the semiconductor processing method of claim 10 wherein: the oxygen-containing precursor comprises ozone [0057]; and the fluorine-containing precursor comprises tungsten hexafluoride [0059].
Regarding claim 13, Cui as previously modified teaches the semiconductor processing method of claim 10 wherein a temperature is maintained at between about 200 °C and about 600 °C during operations i) and ii) [0056].
Regarding claim 14, Cui as previously modified teaches the semiconductor processing method of claim 10 wherein a pressure is maintained at less than or about 20 Torr during operations i) and ii) [0056].
Regarding claim 15, Cui as previously modified teaches the semiconductor processing method of claim 10 wherein it is further comprising: adjusting a temperature, a pressure, or both prior to contacting the oxidized portion of .
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cui et al. (US 20190214230) (hereinafter Cui) (embodiment in fig. 6) and Ajaykumar et al. (First Demonstration of Ruthenium and Molybdenum...) (hereinafter Ajauykumar).
Regarding claim 1, Cui discloses (in figures 6 and 7 with reference to figure 5) a semiconductor processing method comprising:
providing an oxygen-containing precursor to a semiconductor processing chamber (ABSTRACT) (operation 605, figure 6) [0071], wherein a substrate (700, figure 7) [0071] is positioned within the semiconductor processing chamber (200, figure 2) [0050] [0071], wherein the substrate (700) comprises:
a trench (705, figure 7) [0071] formed between columns (510, figure 5 – not designated but present in figure 7) [0048];
and [metal] regions (525, figure 5 – not designated but present in figure 7A) [0048] in a plurality of recesses (527, figure 5 – not designated but present in figure 7) [0048] formed in at least one of the columns (510), wherein at least two of the metal regions are connected by a [metal]-containing first liner (exposed portions of 525, figure 5 – not designated but present in figure 7A) [0048] formed on at least a portion of a sidewall (540, figure 5 – not designated but present in figure 7) of the trench (705);
forming a plasma of the oxygen-containing precursor in the semiconductor processing chamber (operation 610, figure 6) [0071];
contacting (operation 620, figure 6) [0071] the [metal]-containing first liner (exposed portions of 525) with plasma effluents of the oxygen-containing precursor [0071], wherein the contacting forms an oxidized portion of [metal] (755) [0071] on the [metal]-containing first liner (exposed portions of 525);
providing a halide precursor to the semiconductor processing chamber (operation 625, figure 6) [0073]; and
contacting the oxidized portion of [metal] (755) with plasma effluents of the halide precursor [0073-0074], wherein the contacting removes the oxidized portion of [metal] (755) [0073] from the sidewall (540) of the trench (705) [0073].
Cui does not disclose wherein the metal regions (525) are molybdenum (Cui discloses wherein the metal regions comprise tungsten (W)).
However, Ajaykumar discloses using molybdenum as the metal regions in 3d NAND structures (figure 3b).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Cui to substitute tungsten [0071] as their metal region (725) for molybdenum in order to decrease the resistivity of these regions in light of the disclosure of Ajaykumar (Abstract).
Regarding claim 10, Cui discloses a semiconductor processing method (in figures 6 and 7 with reference to figure 5) comprising:
i) forming plasma effluents of an oxygen-containing precursor (operation 610, figure 6) [0071];
ii) contacting a [tungsten]-containing first liner (exposed portions of 525, figure 5 – not designated but present in figure 7) [0048] connecting at least two [tungsten]-containing metal regions (725) [0071] arranged within a plurality of recesses (527, figure 5 – not designated but present in figure 7) [0062] defined by at least one column (510, figure 5 – not designated but present in figure 7) [0048] of a trench (705) [0071] with plasma effluents of the oxygen-containing precursor [0071], wherein the contacting forms an oxidized portion of [tungsten] (755) [0073] on the
iii) forming plasma effluents of a fluorine-containing precursor (operation 640, figure 6) [0074]; and
iv) contacting the oxidized portion of
Cui does not disclose wherein the metal regions (525) are molybdenum (Cui discloses wherein the metal regions comprise tungsten (W)).
However, Ajaykumar discloses using molybdenum as the metal regions in 3d NAND structures (figure 3b) as a replacement for tungsten (Abstract).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Cui to substitute tungsten [0071] as their metal region (725) for molybdenum in order to decrease the resistivity of these regions in light of the disclosure of Ajaykumar (Abstract).
Claims 8, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Cui and Ajaykumar as applied to claim 1 for claim 8 and claim 10 for claims 16 and 17 in section 6 above, and further in view of Vanhaelemeersch et al. (US 6900140) (hereinafter Vanhaelemeersch).
Regarding claim 8, Cui as previously modified teaches the semiconductor processing method of claim 1 wherein the substrate further comprises a second liner (745) [0074] disposed adjacent to the [tungsten] regions (725) [0071] and the [tungsten]-containing first liner (exposed portions of 525) [0048] (see marked up figure 5A above, not shown but present in figure 7A), the method further comprising:
providing a fluorine-containing precursor to the semiconductor processing chamber (operation 635, figure 6) [0074];
forming a plasma of the fluorine-containing precursor to produce fluorine- containing plasma effluents (operations 635 and 640, figure 6) [0074];
contacting the second liner (745) with the fluorine-containing plasma effluents to form a fluorinated portion of the second liner (745) [0073-0074];
providing a chlorine-containing precursor [0072] to the semiconductor processing chamber (operation 625, figure 6) [0073];
But Cui does not disclose forming a plasma of the chlorine-containing precursor [0072] to produce chlorine-containing plasma effluents; and
contacting the fluorinated portion of the second liner (745) with the chlorine- containing plasma effluents, wherein the contacting removes the fluorinated portion of the second liner (745).
However, Vanhaelemeersch discloses (in figure 9) a method of etching a semiconductor structure comprising providing a fluorine-containing precursor to the semiconductor processing chamber (Col. 10, lines 14-20);
forming a plasma of the fluorine-containing precursor to produce fluorine- containing plasma effluents (Col. 10, lines 20-24);
contacting the second liner (15) (Col. 10, lines 55-58) with the fluorine-containing plasma effluents to form a fluorinated portion of the second liner (15) (Col. 10, line 66 – Col. 11, line 5);
providing a chlorine-containing precursor to the semiconductor processing chamber Col. 11, lines 8-17) (Colo. 11, lines 61-65);
forming a plasma of the chlorine-containing precursor to produce chlorine-containing plasma effluents (Col. 11, lines 8-17); and
contacting the fluorinated portion of the second liner (15) with the chlorine- containing plasma effluents, wherein the contacting removes the fluorinated portion of the second liner (Col. 11, lines 8-17).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Cui to include forming a plasma with the chlorine-containing precursor in light of the disclosure of Vanhaelemeersch in order to form an anisotropic etch that has increased etch rates due to the chlorine (Col. 11, lines 61-65).
Regarding claim 16, Cui as previously modified teaches the semiconductor processing method of claim 10 wherein the substrate further comprises a second liner (745) [0074] disposed adjacent to the [tungsten] regions (725) [0071] and the [tungsten]-containing first liner (exposed portions of 525) [0048], the method further comprising:
providing a fluorine-containing precursor to the semiconductor processing chamber (operation 635, figure 6) [0074];
forming a plasma of the fluorine-containing precursor to produce fluorine- containing plasma effluents (operation 640, figure 6) [0074];
contacting the second liner (745) with the fluorine-containing plasma effluents to form a fluorinated portion of the second liner (745) [0073-0074];
providing a chlorine-containing precursor to the semiconductor processing chamber (operation 625, figure 6) [0073];
But Cui does not disclose forming a plasma of the chlorine-containing precursor to produce chlorine-containing plasma effluents; and
However, Vanhaelemeersch discloses (in figure 9) a method of etching a semiconductor structure comprising providing a fluorine-containing precursor to the semiconductor processing chamber (Col. 10, lines 14-20);
forming a plasma of the fluorine-containing precursor to produce fluorine- containing plasma effluents (Col. 10, lines 20-24);
contacting the second liner (15) (Col. 10, lines 55-58) with the fluorine-containing plasma effluents to form a fluorinated portion of the second liner (15) (Col. 10, line 66 – Col. 11, line 5);
providing a chlorine-containing precursor to the semiconductor processing chamber Col. 11, lines 8-17) (Colo. 11, lines 61-65);
forming a plasma of the chlorine-containing precursor to produce chlorine-containing plasma effluents (Col. 11, lines 8-17); and
contacting the fluorinated portion of the second liner (15) with the chlorine- containing plasma effluents, wherein the contacting removes the fluorinated portion of the second liner (Col. 11, lines 8-17).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Cui to include forming a plasma with the chlorine-containing precursor in light of the disclosure of Vanhaelemeersch in order to form an anisotropic etch that has increased etch rates due to the chlorine (Col. 11, lines 61-65).
Regarding claim 17, Cui as previously modified teaches the semiconductor processing method of claim 16 wherein the second liner (745) [0074] comprises an oxygen-containing material, a nitrogen-containing material, or an oxygen-and-nitrogen-containing material [0074] (titanium nitride).
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cui and Ajaykumar as applied to claim 1 for claim 9 and claim 10 for claim 11 in section 5 above, and further in view of Korolik et al. (US 9449843) (hereinafter Korolik).
Regarding claim 9, Cui as previously modified teaches the semiconductor processing method of claim 1.
But Cui and Ajaykumar do not disclose wherein the contacting of the molybdenum-containing first liner (exposed portions of 525) with plasma effluents of the oxygen- containing precursor and the contacting the oxidized portion of molybdenum (555 – tungsten oxide) with plasma effluents of the halide precursor is repeated at least two times.
However, Korolik discloses a semiconductor processing method in figure 1 wherein the contacting of the metal with plasma effluents of the oxygen- containing precursor (operation 130) (Col. 4, lines 59-65) and the contacting the oxidized portion of the metal with the halide precursor (operation 150) (col. 4, lines 65-68) is repeated at least two times (Col. 5, lines 3-9) (see figure 1).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Cui to include repeating the contacting of the metal with plasma effluents in order to use a feedback system to ensure precision in the final structure in light of the disclosure of Korolik (Col. 2, lines 54-65).
Regarding claim 11, Cui as previously modified teaches the semiconductor processing method of claim 10.
But Cui and Ajaykumar do not disclose wherein operations i) through iv) are repeated at least two times.
However, Korolik discloses a semiconductor processing method in figure 1 wherein
i) forming plasma effluents of an oxygen-containing precursor (Col. 5, lines 20-24);
ii) contacting an exposed region of [tungsten], wherein the contacting forms an oxidized portion of tungsten on the [tungsten]-containing first liner (operation 130) (Col. 4, lines 4-34);
iv) contacting the oxidized portion of [tungsten] with the fluorine-containing precursor (Operation 150), wherein the contacting removes the oxidized portion of [tungsten] (Col. 4, lines 65-68).
Wherein these steps are repeated at least two times (Col. 5, lines 3-9) (see figure 1).
Therefore, it would have been obvious to a person of ordinary skill in the art (POSITA) before the effective filing date of the invention to modify the method of Cui to include repeating the contacting of the metal with plasma effluents in order to use a feedback system to ensure precision in the final structure in light of the disclosure of Korolik (Col. 2, lines 54-65).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 2, 5, 7, 10, 14, and 15 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 12, 14, 17, 13, 11, and 9, respectively, of U.S. Patent No. 10861676. Although the claims at issue are not identical, they are not patentably distinct from each other because the current claims are broader in scope than or obvious variant the corresponding claims of US Patent No.10861676 in view of Ajaykumar et al. (First Demonstration of Ruthenium and Molybdenum...) (hereinafter Ajauykumar).
Specifically claim 1 and 10 of the instant applicant, claims 1 and 13 of the patent 10861676 recites essential the same limitations and having narrower limitation for oxidizing for a period of time less than one minute than the current independent claims 1 and 10 Additionally, claim 1 of the patent 10861676 refers to having metal slabs while they are limited to molybdenum in the instant application, but using molybdenum as the metal portion in 3D NAND transistors would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention as it is a popular material to substitute previously used materials in 3D NAND devices such as tungsten as disclosed by Ajaykumar (abstract).
Regarding Claim 2, claim 12 of patent 10861676 recites oxygen-containing precursor comprise ozone.
Regarding claim 5, claim 14 of patent 10861676 recites the halide precursor comprising tungsten fluoride
Regarding claim 7, claim 17 of patent 10861676 recites wherein the oxidizing produces a layer of oxide formed along the sidewalls of the trench, and wherein a thickness of the layer of oxide proximate an upper region of the trench differs in thickness from the layer of oxide proximate a lower region of the trench by less than about 30%.
Regarding claim 14, claim 11 of patent 10861676 recites wherein a chamber operating pressure of less than or about 100 Torr is maintained during the etching.
Regarding claim 15, claim 9 discloses wherein temperature is adjusted prior to contacting the oxidized portion of the metal with plasma effluents of the fluorine-containing precursor.
Response to Arguments
Applicant's arguments filed 4/8/2025 have been fully considered but they are not persuasive.
With regards to the double patenting rejection, the applicant has indicated that the filing of a terminal disclaimer will be held until an indication that the claims are allowed. No arguments were presented as to the merits of the double patenting rejection. The double patenting rejection is maintained and the claims are not allowed.
With regard to the obviousness rejections under 35 U.S.C. 103, applicant has argued that Cui does not teach providing an oxygen precursor to a semiconductor processing chamber and forming a plasma of the oxygen precursor in the semiconductor processing chamber. Applicant points to operation 405, 410 and 415 in Cui’s process flow as arguing that Cui teaches remote oxygen plasma formation, not local oxygen plasma formation as claimed.
This argument is not persuasive. Initially, it noted that the claims do not recite “local” or “local oxygen plasma formation.” Instead claims only require the plasma be formed in the semiconductor processing chamber. Cui teaches this in the language quoted by applicant. Cui teaches “flowing an oxygen-containing precursor into a remote plasma region of the semiconductor processing chamber.” Thus Cui teaches flowing the precursor into the semiconductor processing chamber. Cui further teaches “forming a plasma of the oxygen-containing precursor” and “flowing the oxygen-containing plasma effluents into the processing region.” Taken together, Cui teaches flowing the oxygen-containing precursor into the semiconductor processing chamber, forming a plasma and then flowing the plasma effluents into the processing region. Note that the remote plasma region and the processing region are within the semiconductor processing chamber. The remote plasma region of the processing chamber may be a physically separated or capacitively couple plasma region, but they are considered as part of the same chamber as the semiconductor processing chamber.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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