DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/27/2025 has been entered.
Claim Status
Present action: Claims 1, 2, 6 through 16 allowed. Claims 21 through 27 rejected.
Previous action: Claims 1, 2, 8, 9, 11, 13, 14, 21, 22, 23, 24, 25, 26, and 27 are rejected. Claims 6, 7, 10, 12, 15, and 16 are objected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8, and 9 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lin (US 2014/0084445)
Regarding claim 1.
Lin teaches:
A semiconductor structure (fig 1:10[0012]), comprising:
a semiconductor substrate (fig 1:20[0012]);
an interconnect structure (fig 1:42[0015]) disposed over the semiconductor substrate (fig 1:20[0012]),
the interconnect structure (fig 1:42[0015]) comprising interconnect wirings (fig 1:38b[0015]),
a passivation layer (fig 1:24[0015]) covering the interconnect wirings (fig 1:38b[0015]) and a first thermal conductor (fig 1,2:44[0016,0020]) partially covered by the passivation layer (fig 1:24[0015]);
and a bonding structure (fig 1:50,52,48,54,56,58[0017,0019]) disposed over the interconnect structure (fig 1:42[0015]),
the bonding structure (fig 1:50,52,48,54,56,58[0017,0019])comprising a dielectric layer (fig 1:50,52[0017,0018]) covering the interconnect structure (fig 1:42[0015]),
signal transmission features (fig 1:54’,56’[0019]) penetrating through the dielectric layer (fig 1:50,52[0017,0018]),
and a thermal conductive feature (fig 1,2:54,56[0019,0020]) penetrating through the dielectric layer (fig 1:50,52[0017,0018]),
wherein the thermal conductive feature (fig 1,2:54,56[0019,0020]) is in contact with the first thermal conductor (fig 1,2:44,60[0016,0020]).
Regarding claim 8
Lin teaches the semiconductor structure as claimed in claim 1:
the thermal conductive feature (fig 1,2:54,56[0019,0020]) is electrically insulated from the signal transmission features (fig 1:54’,56’[0019]).
Regarding claim 9.
Lin teaches the semiconductor structure as claimed in claim 1:
the thermal conductive feature (fig 1,2:54,56[0019,0020]) is electrically floating ([0020]).
Claim(s) 21 and 26 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Lin (US 2014/0084445)
Regarding claim 21.
Lin teaches:
A semiconductor structure (fig 2), comprising:
a first semiconductor die (fig 1:10[0012]) comprising an interconnect structure (fig 1:42[0015]) and a first bonding structure (fig 1:54’,56’[0015]),
the interconnect structure (fig 1:42[0015]) comprising interconnect wirings (fig 1:38b[0015]),
a passivation layer (fig 1:24[0015])and a thermal conductor (fig 1,2:44[0016,0020]),
the first bonding structure (fig 1:50,52,48,54,56,58[0017,0019]) comprising a first dielectric layer (fig 1:50,52[0017,0018]),
first signal transmission features (fig 1:54’,56’[0019]) penetrating through the first dielectric layer (fig 1:50,52[0017,0018]),
and a first thermal conductive feature (fig 1,2:54,56[0019,0020]) penetrating through the first dielectric layer (fig 1:50,52[0017,0018]),
wherein the first thermal conductive feature (fig 1,2:54,56[0019,0020]) is in contact with the thermal conductor (fig 1,2:44[0016,0020]),
and the passivation layer (fig 1:24[0015]) being disposed between the thermal conductor (fig 1,2:44[0016,0020]) and the first thermal conductive feature (fig 1,2:54,56[0019,0020]);
and a second semiconductor die (fig 1,2:10[0012]) comprising a second bonding structure (fig 1,2:30[0013]) and a through semiconductor via (fig 1,2:26a[0013]),
wherein the first bonding structure is bonded to the second bonding structure (see annotated fig 2).
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Regarding claim 26
Lin teaches the semiconductor structure as claimed in claim 21, wherein:
the through semiconductor via (fig 1,2:26a[0013]) is over the first thermal conductive feature (fig 1,2:44[0016]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2014/0084445) as applied to claim 1 and further in view of Hu (US 2019/0164914).
Regarding claim 2
Lin (445) teaches the semiconductor structure as claimed in claim 1,
Lin (445) does not teach a bonding dielectric layer
Hu teaches:
wherein the dielectric layer comprises a bonding dielectric layer (fig 14:540[0106])
and an inter-dielectric layer (fig 14:538[0106])
disposed between the bonding dielectric layer (fig 14:540[0106])
and the interconnect structure (fig 14:526[0106]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a bonding layer in order to enable hybrid bonding and thereby provide shorter connections and finer pitch.
Claim(s) 11, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2014/0084445) in view of Hu (US 2019/0164914) in view of Lin (US 2010/0187670).
Regarding claim 11.
Lin (445) teaches:
A semiconductor structure (fig 2]), comprising:
a first semiconductor die (fig 1,2:10[0012]) comprising an interconnect structure (fig 1:42[0015]) and a first bonding structure (fig 1:54’,56’[0015]),
the interconnect structure (fig 1:42[0015]) comprising interconnect wirings (fig 1:38b[0015]),
a passivation layer (fig 1:24[0015]) covering the interconnect wirings (fig 1:38b[0015]) and a thermal conductor (fig 1,2:44[0016,0020]) partially covered by the passivation layer (fig 1:24[0015]),
the first bonding structure (fig 1:54’,56’[0015]) comprising a first dielectric layer (fig 1:50,52[0017,0018]),
first signal transmission features (fig 1:54’,56’[0019]) penetrating through the first dielectric layer (fig 1:50,52[0017,0018]),
and a first thermal conductive feature (fig 1,2:54.56[0019,0020])penetrating through the first dielectric layer (fig 1:50,52[0017,0018]);
a second semiconductor die (fig 1,2:10[0012]) comprising a second bonding structure (fig 1,2:30[0013]),
the second bonding structure (fig 1:30[0015]) comprising a second dielectric layer (fig 1:50,52[0017,0018]),
second signal transmission features (fig 1:54’,56’[0019]) penetrating through the second dielectric layer (fig 1:50,52[0017,0018]),
and a second thermal conductive feature (fig 1,2:54,56[0019,0020]) penetrating through the second dielectric layer (fig 1:50,52[0017,0018]);
,
,
,
Lin (445) does not teach the features and the dielectric layers are bonded
Hu teaches:
wherein the first dielectric layer (fig 14:540[0106,0110]) is bonded to the second dielectric layer (fig 14:640[0106,0110]),
the first signal transmission features (fig 14:544,542a[0106,0110]) are bonded and electrically connected to the second signal transmission features (fig 14:644,642a[0106,0110]),
and the first thermal conductive feature (fig 14:536,554,552[0106,0110]) is bonded and thermally coupled to the second thermal conductive feature (fig 14:635,652,654[0106,0110]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond the features and the dielectric in order to connect die using hybrid bonding which allows more connections between die due to the finer pitch between connections and shorter lengths
Lin (445) does not teach encapsulant
Lin (670) teaches:
an insulating encapsulant (fig 5:265[0041]) disposed on the second semiconductor die (fig 5:x[0041]) and encapsulating the first semiconductor die(fig 5:y[0041]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to encapsulate the devices in order to protect the structure from the environment.
Regarding claim 13.
Lin (445) in view of Hu in view of Lin (670) teaches the semiconductor structure as claimed in claim 11, further
Lin (445) teaches:
the first thermal conductive feature (fig 1,2:54,56[0019,0020]) and the second thermal conductive feature (fig 1,2:54,56[0019,0020]) are electrically floating ([0020]),
and the first thermal conductive feature (fig 1,2:54,56[0019,0020]) and the second thermal conductive feature (fig 1,2:54,56[0019,0020]) are electrically insulated from the first signal transmission features and the second signal transmission features (fig 1,2:54’,56’[0019]).
Regarding claim 14.
Lin (445) in view of Hu in view of Lin (670) teaches the semiconductor structure as claimed in claim 11, further
Hu teaches:
the first bonding structure further comprises first dummy pads (fig 14:542b[0106,0110]) embedded in the first dielectric layer (fig 14:540[0106,0110]),
the second bonding structure further comprises second dummy pads (fig 14:642b[0106,0110]) embedded in the second dielectric layer (fig 14:640[0106,0110]),
the first dummy pads (fig 14:542b[0106,0110]) and the second dummy pads (fig 14:642b[0106,0110]) are bonded.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide dummy pads in the bonding structure in order to achieve suitable mating surfaces for hybrid bonding have heightened tolerances to help achieve a stronger or more reliable bonding (paragraph 23).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2014/0084445) as applied to claim 21 and further in view of Lee (US 2011/0031598).
Regarding claim 22
Lin (445) teaches the semiconductor structure as claimed in claim 21,
Lin (445) does not teach encapsulation.
Lee teaches:
an insulating encapsulant (fig 1:170[0041]) disposed on the second semiconductor die (fig 1:140[0041]) and encapsulating the first semiconductor die (fig 1:130[0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to encapsulate the devices in order to protect the structure from the environment.
Claim(s) 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2014/0084445) as applied to claim 21 and further in view of Hu (US 2019/0164914).
Regarding claim 23.
Lin (445) teaches the semiconductor structure as claimed in claim 21,
Lin (445) does not teach bonding the features and bonding the dielectrics
Hu teaches:
wherein the second bonding structure comprising a second dielectric layer (fig 14:640[0106,0110]),
second signal transmission features (fig 14:644,542a[0106,0110]) penetrating through the second dielectric layer (fig 14:640[0106,0110]),
a second thermal conductive feature (fig 14:635,654,652[0106,0110]) penetrating through the second dielectric layer (fig 14:640[0106,0110]),
the first dielectric layer (fig 14:540[0106]) is bonded to the second dielectric layer (fig 14:640[0106,0110]),
the first signal transmission features (fig 14:544,542a[0106]) are bonded and electrically connected to the second signal transmission features (fig 14:644,642a[0106,0110]),
and the first thermal conductive feature (fig 14:535,554,552[0106]) is bonded and thermally coupled to the second thermal conductive feature (fig 14:635,654,652[0106,0110]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bonding the features and the dielectric in order to enable hybrid bonding and thereby permit a finer pitch between connection which will provide more communication routes and shorter distances
Regarding claim 24.
Lin (445) in view of Hu teaches the semiconductor structure as claimed in claim 23, further
Lin (445) teaches
the first thermal conductive feature (fig 1,2:44[0020]) and the second thermal conductive feature (fig 1,2:44[0020]) are electrically floating ([0020]),
and the first thermal conductive feature (fig 1,2:44[0020]) and the second thermal conductive feature (fig 1,2:44[0020]) are electrically insulated from the first signal transmission features (fig 1,2:42[0015]) and the second signal transmission features (fig 1,2:42[0015]).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2014/0084445) as applied to claim 21 and further in view of Yu (US 20170053902)
Regarding claim 25.
Lin (445) teaches the semiconductor structure as claimed in claim 21,
Lin (445) does not teach tapered through via sidewalls.
Yu teaches:
the through semiconductor via (fig 1a,1d:118; [0014]) comprises tapered sidewalls.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the through semiconductor via to comprise tapered sidewalls due to the etching process used to form the opening exposing the upper surface to etchant longer than the lower surfaces
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2014/0084445) as applied to claim 21 and further in view of Lin (US 2010/0187670).
Regarding claim 27
Lin (445) teaches the semiconductor structure as claimed in claim 21,
Lin (445) does not teach the through substrate via protrudes.
Lin (670) teaches:
wherein the through semiconductor via (fig 3c:135[0033])protrudes from a backside (fig 3c:138[0033]) of a substrate (fig 3c:100[0033]) of the second semiconductor die (fig 3c:180[0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the through via to protrude from the backside in order to facilitate bonding to another die (paragraph 33).
Allowable Subject Matter
Claims 6, 7, 10, 12, 15, and 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art does not teach a semiconductor structure, comprising: the thermal conductive feature comprises a thermal routing and thermal pads, the thermal pads are disposed on and share the thermal routing, the thermal routing laterally extends between at least two neighboring signal transmission features among the signal transmission features, and the thermal routing laterally extends along a meandering path in combination with other features of the claim.
Regarding claim 7, the prior art does not teach a semiconductor structure, comprising: the thermal conductive feature comprises a thermal routing and thermal pads, the thermal pads are disposed on and share the thermal routing, the thermal routing laterally extends between at least two neighboring signal transmission features among the signal transmission features, the thermal routing comprises via portions and wall portions laterally connecting via portions, and the via portions are in contact with the thermal pads, and wherein at least one of the wall portions laterally extend between at least two neighboring signal transmission features among the signal transmission features in combination with other features of the claim.
Regarding claim 10, the prior art does not teach a semiconductor structure comprising: wherein the thermal conductive feature comprises a thermal routing and thermal pads, the thermal pads are disposed on and share the thermal routing, the thermal routing laterally extends between at least two neighboring signal transmission features among the signal transmission features, the interconnect structure further comprises a second thermal conductor disposed over the passivation layer, and a portion of the thermal routing is landed on the second thermal conductor.
Regarding claim 12, the prior art does not teach a semiconductor structure comprising: the first thermal conductive feature comprises a first thermal routing and first thermal pads, the first thermal pads are disposed on and share the first thermal routing, and the first thermal routing laterally extends between at least two neighboring first signal transmission features among the first signal transmission features, and the first thermal routing comprises a meshed thermal routing.
Regarding claim 15, the prior art does not teach a semiconductor structure comprising: the first thermal conductive feature comprises a first thermal routing and first thermal pads, the first thermal pads are disposed on and share the first thermal routing, and the first thermal routing laterally extends between at least two neighboring first signal transmission features among the first signal transmission features, the first thermal routing comprises first via portions and first wall portions laterally connecting first via portions, and the first via portions are in contact with the first thermal pads, and wherein at least one of the first wall portions laterally extend between at least two neighboring first signal transmission features among the first signal transmission features.
Regarding claim 16, the prior art does not teach a semiconductor structure comprising: the second thermal conductive feature comprises a second thermal routing and second thermal pads, and the second thermal pads are disposed on and share the second thermal routing, the second thermal routing comprises second via portions and second wall portions laterally connecting second via portions, and the second via portions are in contact with the second thermal pads, and wherein at least one of the second wall portions laterally extend between at least two neighboring second signal transmission features among the second signal transmission features.
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 7, 2026