DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/10/2026 has been entered. An action on the RCE follows.
Response to Arguments
Applicant’s reply filed on 04/10/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 28 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 28, The instant claims recite limitation “wherein a depth of the at least one trench, as measured from the first horizontal plane to the recessed surface segment, is in a range from 40% to 90% of a standoff height between a bottom surface of the first chip module and the third horizontal plane” is not clear because recessed surface segment, is in a range from 40% to 90% of a standoff height between a bottom surface of the first chip module and the third horizontal plane is not defined. In addition, there is lack of antecedent issue in “the third horizontal plan”. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over TSAI et al (US 2020/0006176 A1; hereafter TSAI).
Regarding claim 1. TSAI first embodiment discloses a semiconductor structure comprising:
a packaging substrate (Fig [2], redistribution structure 120, construed as package substrate, Para [ 0025]) comprising a front surface and a backside surface (Fig [2], redistribution structure 120, upper/ lower surface Para [ 0025]), first substrate bonding pads ( Fig. [2], left conductive pads 128,Para [ 0026], also shown in figure 1B) located in a first region ( region 130A) of the front surface (Fig [2], redistribution structure 120, upper surface Para [ 0025]), and second substrate bonding pads ( Fig. [2], right conductive pads 128,Para [ 0026], also shown in figure 1B) located in a second region (region130B) of the front surface (Fig [2], redistribution structure 120, upper surface Para [ 0025]), and at least one trench including a respective recessed surface ( recess R1, shown in Fig [2], also shown in Figure 1L) segment of the front surface and located between the first region (region 130A) and the second region (region 130B);
a first chip module including first module-side bump structures (chip 130A, Para [ 0032]) that are bonded to the first substrate bonding pads (Fig. [2], left conductive pads 128, Para [ 0026], also shown in figure 1B) through first solder material portions (left conductive bumps 140, also shown Fig 1B);
a second chip module (chip 130B, Para [ 0032]) including second module-side bump structures (chip 130A, Para [ 0032]) that are bonded to the second substrate bonding pads (Fig. [2], right conductive pads 128, Para [ 0026], also shown in figure 1B) through second solder material portions (right conductive bumps 140, also shown Fig 1B);
a first underfill material portion (Fig. [2], left molding layer 160, Para [ 0039]) laterally surrounding the first solder material portions (left conductive bumps 140, also shown Fig 1B) and extending into a first portion of the at least one trench (recess R1, shown in Fig [2], also shown in Figure 1L); and
a second underfill material portion (right molding layer 160, Para [ 0039]) laterally surrounding the second solder material (right conductive bumps 140, also shown Fig 1B) portions and extending into a second portion of the at least one trench ( recess R1, shown in Fig [2], also shown in Figure 1L), wherein the first module-side bump structures and the second module-side bump structures do not have an areal overlap with the at least one trench in a plan view (plan view [Fig 1K-1, 2], recess R1); the at least one trench (recess R1, shown in Fig [2], also shown in Figure 1L) comprises a pair of sidewalls that are laterally spaced apart along a first horizontal direction by a first width (recess R1, shown in Fig [2], also shown in Figure 1L) and laterally extend along a second horizontal direction recess R1, shown in Fig [2], also shown in Figure 1L); the second chip module (chip 130B, Para [ 0032]) is laterally spaced from the first chip module (chip 130A, Para [ 0032]) along the first horizontal direction by a second width (chip 130B, Para [ 0032]).
But TSAI first embodiment does not disclose explicitly the first width is not less than 0.8 times the second width; and the first width is not greater than 1.2 times the second width.
However, TSAI another embodiment discloses the first width is not less than 0.8 times the second width; and the first width is not greater than 1.2 times the second width (Fig [3-6] discloses different shape of recess between two chip modules [ 132], in addition, Para [ 0086] discloses “the widths W1, W2, W3, and W4 are equal to each other. In some other embodiments (not shown), two of the widths W1, W2, W3, and W4 are different from each other. The trenches R1 and R2 are formed using one or more than one laser cutting process or another suitable process”. Therefore, it is obvious, particular width can be archived by different shape of recess between plurality of chip module.
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine TSAI teaching “the first width is not less than 0.8 times the second width; and the first width is not greater than 1.2 times the second width (Fig [3-6] discloses different shape of recess between two chip modules [ 132], in addition, Para [ 0086] discloses “the widths W1, W2, W3, and W4 are equal to each other. In some other embodiments (not shown), two of the widths W1, W2, W3, and W4 are different from each other. The trenches R1 and R2 are formed using one or more than one laser cutting process or another suitable process”. Therefore, it is obvious, particular width can be archived by different shape of recess between plurality of chip module” for further advantage such as formation of the trench with desire width and depth improves the yield of the chip package structure with the molding layer.
It would have been obvious to one of ordinary skill to determine the optimum depth (see In re Aller, Lacey, and Hall (10 USPQ 233-237). It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed “first width is not less than 0.8 times the second width; and the first width is not greater than 1.2 times the second width” any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical (see In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed. Cir. 1990)). Here, one would incorporate the trench sidewall with desire depth in the claimed for further advantage such as formation of the trench with desire width and depth improves the yield of the chip package structure with the molding layer.
Regarding claim 2. TSAI discloses the semiconductor structure of Claim 1, TSAI further discloses wherein top surfaces of the first substrate bonding pads (Fig. [2], left conductive pads 128,Para [ 0026], also shown in figure 1B) and top surfaces of the second substrate bonding pads ( Fig. [2], right conductive pads 128,Para [ 0026], also shown in figure 1B) are located above a first horizontal plane (upper surface 127, as shown in Figure 1A, construed as first horizontal plane) including each recessed surface segment of the at least one trench ( Fig 2).
Regarding claim 3. TSAI discloses the semiconductor structure of Claim 2, TSAI further discloses wherein:
the top surfaces of the first substrate bonding pads (Fig. [2], left conductive pads 128, Para [ 0026], also shown in figure 1B) and the top surfaces of the second substrate bonding pads ( Fig. [2], right conductive pads 128,Para [ 0026], also shown in figure 1B) are located within a second horizontal plane ( lower surface of conductive bumps 140, also shown Fig 1B); and the second horizontal plane ( lower surface of conductive bumps 140, also shown Fig 1B) is more distal from the backside surface of the packaging substrate (Fig [2], redistribution structure 120, construed as package substrate, Para [ 0025]) than the first horizontal plane (upper surface 127, as shown in Figure 1A, construed as first horizontal plane) is from the backside surface of the packaging substrate (Fig [2], redistribution structure 120, construed as package substrate, Para [ 0025]).
Allowable Subject Matter
Claims 4-6, 10 and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 4. The semiconductor structure of Claim 3, wherein the front surface comprises:
a first horizontal surface segment in contact with the first underfill material portion and located within a third horizontal plane that is more distal from the backside surface of the packaging substrate than the second horizontal plane is from the backside surface of the packaging substrate; and a second horizontal surface segment in contact with the second underfill material portion and located within the third horizontal plane.
Claim 5-6 are objected based on the dependency of claim 4.
Regarding claim 10. wherein: the at least one trench comprises two trenches having a respective uniform width along a first horizontal direction, laterally extending along a second horizontal direction, and laterally spaced apart from each other along the first horizontal direction by a dam structure that protrudes from bottom surfaces of the two trenches; and
the first underfill material portion and the second underfill material portion are laterally spaced from each other by the dam structure.
Regarding claim 29. wherein the at least one trench laterally surrounds the first chip module and the second chip module along at least three sides in the plan view such that the first underfill material portion and the second underfill material portion form respective fillet regions that taper into peripheral portions of the at least one trench on multiple sides of each chip module.
Claims 11, 21, 23-26 and 30-32 are allowed.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
a first fan-out package including first fan-out bump structures that are bonded to the first substrate bonding pads through first solder material portions; a second fan-out package including second fan-out bump structures that are bonded to the second substrate bonding pads through second solder material portions; a first underfill material portion laterally surrounding the first solder material portions and extending into a first portion of the at least one trench; and a second underfill material portion laterally surrounding the second solder material portions and extending into a second portion of the at least one trench, wherein the first solder material portions and the second solder material portions do not have an areal overlap with the at least one trench in a plan view; and wherein the first underfill material portion and the second underfill material portion are laterally spaced from each other by the dam structure and do not contact each other, as recited in claim 11.
Claims 30-31 are allowed based on the dependency of claim 11.
a first chip module including first module-side bump structures that are bonded to the first substrate bonding pads through first solder material portions; a second chip module including second module-side bump structures that are bonded to the second substrate bonding pads through second solder material portions ;a first underfill material portion laterally surrounding the first solder material portion and extending into a first trench of the two trenches; and a second underfill material portion laterally surrounding the second solder material portion and extending into a second trench of the two trenches, wherein the first underfill material portion and the second underfill material portion are laterally spaced from each other by the dam structure, as recited in claim 21.
Claims 23-26 and 32 are allowed based on the dependency of claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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