DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/6/2025 has been entered.
Status of Claims
Claims 1-17 and 21-23 are pending in this application, with claims 3, 6-10, 16-17 and 23 being withdrawn as directed to non-elected species.
Prior rejection of Claims 13-15 under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, is withdrawn in view of applicant’s amendments to claim 13.
Prior rejection of Claim 1-2, 4-5, 11-12 and 21-22 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, is withdrawn in view of applicant’s amendments to claims 1 and 21.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2014/0061897 A1, newly cited).
Re Claim 13, Lin teaches an interposer (200, Fig. 4, para [0047]) for a semiconductor package, comprising:
a first surface (top surface of 200, Fig. 4);
a second surface (bottom surface of 200, Fig. 4);
a plurality of redistribution structures (vias 202, para [0047], Fig. 4) located between the first surface and the second surface of the interposer (200, para [0047], Fig. 4); and
a plurality of metallic material pillars (208A+302+22A and 208B+304+22D, see annotated Fig. 4 below, also see Figs. 3C-3D, where 22A and 22D are marked, paras [0040] - [0048]) over the second surface of the interposer (bottom surface of 200, Fig. 4) and electrically contacting the plurality of redistribution structures (see Fig. 4), wherein the plurality of metallic material pillars over the second surface of the interposer have non-uniform height dimensions (208B+304+22D and 208A+302+22A have non-uniform heights H1 and H2 respectively, marked in annotated Fig. 4 below) and a first metallic material pillar of the plurality of metallic material pillars has a greater height dimension than a second metallic material pillar of the plurality of metallic material pillars (H2 is greater than H1), and the first metallic material pillar and the second metallic material pillar have equal width dimensions (width W1 of 22A of 1st pillars 208A+302+22A, and width W2 of 22D of 2nd pillars 208B+304+22D can be same, para [0026]).
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Re Claim 14, Lin teaches the interposer of claim 13, wherein the plurality of metallic material pillars comprises a periodic two-dimensional array of metallic material pillars (see Fig. 1), wherein a first set of metallic material pillars in a peripheral region of the array has a first height dimension (pillars 208B+304+22D with heights H1 in region 120, Fig. 1), and a second set of metallic material pillars in a central region of the array has a second height dimension (pillars 208A+302+22A with heights H2 in region 110, Fig. 1) that is different than the first height dimension (H2 is greater than H1).
Re Claim 15, Lin teaches the interposer of claim 14, wherein the peripheral region of the array including metallic material pillars having the first height dimension (pillars 208B+304+22D with heights H1 in region 120, Fig. 1) laterally surrounds the central region of the array on four sides (para [0026], Fig. 1).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 4-5, 12 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2014/0061897 A1, newly cited) and further in view of Elsherbini (US 2019/0385977 A1, newly cited).
Re Claim 1, Lin teaches a semiconductor package, comprising:
an interposer (200, Fig. 4, para [0047]);
at least one semiconductor integrated circuit (IC) die (chip 100, marked in annotated Fig. 4 below, para [0048]) mounted over a first surface of the interposer (top surface of 200, Fig. 4);
a plurality of metallic material pillars (208A+302+22A and 208B+304+22D, see annotated Fig. 4 below, also see Fig. 2, where 22A and 22D are marked, paras [0040] - [0048]) over a second surface of the interposer (bottom surface of 200), wherein the plurality of metallic material pillars comprises a first set of one or more metallic material pillars (pillars 208B+304+22D) in a first region of the interposer (pillars 208B+304+22D are in region 120, Fig. 1) having a first height dimension with respect to the second surface of the interposer (height “h1”, marked in annotated Fig. 4 below), and a second set of one or more metallic material pillars (pillars 208A+302+22A) in a second region of the interposer (pillars 208A+302+22A are in region 110, Fig. 1) having a second height dimension with respect to the second surface of the interposer (height “h2”, marked in annotated Fig. 4 below), wherein the second height dimension is greater than the first height dimension (h2 is greater than h1, see Fig. 4), and wherein a width dimension of the first metallic material pillar of the first set of one or more metallic material pillars in the first region of the interposer is equal to a width dimension of a second metallic pillar of the second set of one or more metallic material pillars in the second region of the interposer (width of 22A of pillars 208A+302+22A, and width of 22D of pillars 208B+304+22D can be same, para [0026]);
a plurality of solder material portions (214, Fig. 4, para [0047])
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Lin is silent about the following:
a package substrate comprising a plurality of bonding pads on a front surface of the package substrate; and
a plurality of solder material portions located between respective metallic material pillars over the second surface of the interposer and respective bonding pads of the package substrate.
In a related field of art, Elsherbini teaches a package substrate (102, Fig. 1A, para [0024]) with pads 146 (Fig. 1A, para [0024]) on its top surface. The package substrate is used for mounting the semiconductor dies and chips and route connection to the motherboard or other devices.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include the package substrate into the device of Lin as taught by Elsherbini. The package substrate is used for mounting the semiconductor dies and chips and route connection to the motherboard or other devices.
Hence, Lin modified by Elsherbini teaches:
a package substrate (102, Fig. 1A, para [0024], Elsherbini) comprising a plurality of bonding pads on a front surface of the package substrate (146 Fig. 1A, para [0024], Elsherbini); and
a plurality of solder material portions (214, Fig. 4, para [0047], Lin) located between respective metallic material pillars (pillars 208A+302+22A and 208B+304+22D, Fig. 4, Lin) over the second surface of the interposer (bottom surface of 200, Fig. 4, Lin) and respective bonding pads of the package substrate (146 Fig. 1A, para [0024], Elsherbini).
Re Claim 4, Lin modified by Elsherbini teaches the semiconductor package of claim 1, but does not explicitly disclose the plurality of metallic material pillars each have a height dimension that is at least 5 µm and equal to or less 70 µm.
Lin discloses that the thicknesses of layers 22A and 22D can be 10 µm (para [0040]) and 5 µm (para [0043]) respectively. The thicknesses of 302 is equivalent to the thickness of layer 26A and can be 5 µm (compare Figs. 3C and 4, para [0042]). The thicknesses of 304 is equivalent to the thickness of layer 26D and can be 5 µm (compare Figs. 3D and 4, para [0045]). Lin does not explicitly disclose that the thicknesses of 208A or 208B, but they are approximately the same thicknesses as that of 22A (see Fig. 4), and hence can be approximately 10 µm. Comparing the above numbers, the height of 1st set of pillars 208B+304+22D can be 20 µm, while the height of 2nd set of pillars 208A+302+22A can be 25 µm, which is within the claimed range. The claimed height of the metallic pillars would have been obvious to optimize and ascertainable through routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Re Claim 5, Lin modified by Elsherbini teaches the semiconductor package of claim 4, wherein a ratio of the first height dimension of the first set of one or more metallic material pillars (height of 1st set of pillars 208B+304+22D can be 20 µm, see claim 4 above) in the first region of the interposer to the second height dimension of the second set of one or more metallic material pillars (height of 2nd set of pillars 208A+302+22A can be 25 µm, see claim 4 above) in the second region of the interposer is between 0.07 and 0.98 (ratio is 0.80, within the claimed range).
Re Claim 12, Lin modified by Elsherbini teaches the semiconductor package of claim 1, wherein the interposer (200, Fig. 4, Lin) comprises a semiconductor material interposer (200 can be silicon, para [0047], Lin) comprising a plurality of conductive through-vias (vias 202, Fig. 4, para [0047], Lin) extending through a semiconductor material member.
Re Claim 21, Lin teaches a semiconductor package, comprising:
an interposer (200, Fig. 4, para [0047]);
at least one semiconductor integrated circuit (IC) die (chip 100, marked in annotated Fig. 4 below, para [0048]) mounted over a first surface of the interposer (top surface of 200, Fig. 4);
an array of metallic material pillars (208A+302+22A and 208B+304+22D, see annotated Fig. 4 above, also see Fig. 2, where 22A and 22D are marked, paras [0040] - [0048]) over the second surface of the interposer (bottom surface of 200) having non-uniform height dimensions (pillars 208A+302+22A and 208B+304+22D have non-uniform heights “h2” and “h1” respectively, marked in annotated Fig. 4 above), and a first metallic material pillar (pillar 208A+302+22A) of the plurality of metallic material pillars has a greater height dimension than, and an equal width as, a second metallic material pillar (pillar 208B+304+22D) of the plurality of metallic material pillars (“h2” is greater than “h1”; additionally, width of 22A of pillars 208A+302+22A, and width of 22D of pillars 208B+304+22D can be same, para [0026]);
a plurality of solder material portions (214, Fig. 4, para [0047]), wherein the first metallic material pillar of the plurality of metallic material pillars (pillar 208A+302+22A) is located in a peripheral region of the interposer (pillars 208A+302+22A are in region 110, which includes both central and peripheral regions, see Fig. 1) and the second metallic material pillar (pillar 208B+304+22D) of the plurality of metallic material pillars is located in a central region of the interposer (pillars 208B+304+22D are in region 120, which includes both central and peripheral regions, see Fig. 1).
Lin is silent about the following:
a package substrate comprising a plurality of bonding pads on a front surface of the package substrate; and
a plurality of solder material portions located between respective metallic material pillars over the second surface of the interposer and respective bonding pads of the package substrate.
In a related field of art, Elsherbini teaches a package substrate (102, Fig. 1A, para [0024]) with pads 146 (Fig. 1A, para [0024]) on its top surface. The package substrate is used for mounting the semiconductor dies and chips and route connection to the motherboard or other devices.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to include the package substrate into the device of Lin as taught by Elsherbini. The package substrate is used for mounting the semiconductor dies and chips and route connection to the motherboard or other devices.
Hence, Lin modified by Elsherbini teaches:
a package substrate (102, Fig. 1A, para [0024], Elsherbini) comprising a plurality of bonding pads on a front surface of the package substrate (146 Fig. 1A, para [0024], Elsherbini); and
a plurality of solder material portions (214, Fig. 4, para [0047], Lin) located between respective metallic material pillars (pillars 208A+302+22A and 208B+304+22D, Fig. 4, Lin) over the second surface of the interposer (bottom surface of 200, Fig. 4, Lin) and respective bonding pads of the package substrate (146 Fig. 1A, para [0024], Elsherbini).
Re Claim 22, Lin modified by Elsherbini teaches the semiconductor package of claim 21, wherein a first set of the metallic material pillars has a first height dimension (1st set of pillars 208A+302+22A having height “h2”, see annotated Fig. 4 above), and a second set of the metallic material pillars has a second height dimension (2nd set of pillars 208B+304+22D having height “h1”, see annotated Fig. 4 above) that is different than the first height dimension (“h2” is greater than “h1”), wherein metallic pillars having the first height dimension are located along at least two peripheral edges of the array (pillars 208A+302+22A are in region 110, which includes two peripheral edges, see Fig. 1).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2014/0061897 A1, newly cited) and Elsherbini (US 2019/0385977 A1, newly cited) and further in view of Cosue et al. (US 2012/0199960 A1, newly cited).
Re Claim 11, Lin modified by Elsherbini teaches the semiconductor package of claim 1, wherein the interposer (200, Fig. 4, Lin) comprises an organic interposer (200 can be organic materials, para [0047], Lin) comprising interconnect structures (vias 202, Fig. 4, para [0047], Lin).
Lin does not explicitly disclose that the organic interposer comprises of dielectric polymer material matrix.
In a related semiconductor art, Cosue teaches that an interposer can be made of an organic dielectric polymer.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the organic interposer of Lin using organic dielectric polymer as disclosed by Cosue. The selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 recites the limitation wherein, “the first region of the interposer overlaps a central point of the interposer and the second region of the interposer surrounds the central region”. Lin (US 2014/0061897 A1, newly cited) shows a first region (region 120, Fig. 1, see claim 1 above) which overlaps a central point of the interposer 200, however, the second region (region 110, Fig. 1) does not surround the central region. This limitation is neither anticipated nor made obvious by the prior art of record in the Examiner’s opinion.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1, 13 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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