The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-10, 12-20 and 29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
There is no support in the specification for a final structure of a semiconductor structure for the claimed limitation of “a top surface of the portion of the dielectric liner is above a top surface of the substrate, and a top surface of another portion of the dielectric liner is coplanar with the top surface of the substrate”, as recited in claim 9.
Applicants state that “Support for the amendments can be found at least in claim 14, paragraphs [0031] and [0034] and FIGS. 10A and 10C of the present application as originally filed”. Applicants further state that figure 10C depicts a top surface of the portion of the dielectric liner is above a top surface of the substrate a top surface of the portion of the dielectric liner is above a top surface of the substrate, and figure 10A depicts that a top surface of another portion of the dielectric liner is coplanar with the top surface of the substrate.
However, the specification recites:
“[0006] FIGS. 1A, 2-7, 8A, 9, 10A and 10C [as filed on 05/06/2025] illustrate cross-sectional views of various stages in a manufacturing process of a semiconductor structure, in accordance with some embodiments of the present disclosure”.
Therefore, the two claimed limitations in the amendment filed on 01/16/2026 are brought together from two separate intermediate product during the manufacturing process of the semiconductor structure, and they are part of one final structure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10, 12-20 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (20140353744) in view of Park (2020/0395362) and Beck (2006/0194430).Regarding claim 9, Jung et al. teach in figure 3 and related text a semiconductor structure, comprising:
a substrate 11 having contact openings;
a dielectric liner 21 disposed on sidewalls of the contact openings; and
a bit line structure 100 disposed over the substrate and spanning the contact openings in a first direction;
wherein the bit line structure 100 comprises:
a contact 19A disposed directly above the contact openings; and
a plug layer 25 disposed above the substrate and separated from the contact by a portion of the dielectric liner 21 in the first direction, wherein a top surface of the bit line structure 10 is substantially coplanar with a top surface of the plug layer 25;
wherein the dielectric liner 21 surrounds the bit line structure within the contact openings, and the portion of the dielectric liner 21 extends into the bit line structure and
a top surface of the portion of the dielectric liner 21 is above a top surface of the substrate 11.
Jung et al. do not teach that the plug layer comprises semiconductor, and do you teach that a top surface of another portion of the dielectric liner is coplanar with the top surface of the substrate
Park teaches in related text that the plug layer comprises semiconductor (see e.g. claim 8).
Beck teaches in figure 9 and related text that a top surface of the portion of the dielectric liner 214 is above a top surface of the substrate 204, and a top surface of another portion of the dielectric liner 208 is coplanar with the top surface of the substrate.
Beck, Jung et al. and Park are analogous art because they are directed to conductive plugs and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jung et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the plug layer comprises semiconductor, as taught by Park, and to form a top surface of the portion of the dielectric liner is above a top surface of the substrate, and a top surface of another portion of the dielectric liner is coplanar with the top surface of the substrate, as taught by Beck, in Jung et al.’s device, in order to be able to simplify the processing steps of making the device by using conventional conductive material and in order to provide better protection to the device by increasing the length of the liner, respectively.
Note that substitution of materials is not patentable even when the substitution is new and useful. Safetran Systems Corp. v. Federal Sign & Signal Corp. (DC NIII, 1981) 215 USPQ 979.
See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”).
Regarding claim 10, Jung et al. teach in figure 3 and related text that the dielectric liner 129 completely covers the sidewalls of the contact openings.
Regarding claim 12, Jung et al. teach in figure 3 and related text that the contact is electrically connected to the substrate at a bottom surface of the contact openings.
Regarding claim 13, Jung et al. teach in figure 3 and related text that a portion of the dielectric liner that intersects the bit line structure is level with the top surface of the contact.
Regarding claim 14, Jung et al. teach in figure 3 and related text that a portion of the dielectric liner that does not intersect the bit line structure is level with the top surface of the substrate.
Regarding claim 15, Jung et al. teach in figure 3 and related text that the bit line structure is in physical contact with the dielectric liner in the first direction.
Regarding claim 16, Jung et al. teach in figure 3 and related text that there is a spacing between the bit line structure and the dielectric liner in the second direction.
Regarding claim 17, Jung et al. teach in figure 3 and related text that the dielectric liner comprises silicon nitride.
Regarding claim 18, Jung et al. teach in figure 3 and related text that the substrate and the semiconductor layer are separated from each other.
Regarding claim 19, Jung et al. teach in figure 3 and related text that the substrate comprises: a conductive portion 11A electrically connected to the bit line structure; and an isolation portion 12 alternately arranged with the conductive portion, wherein the dielectric liner is disposed over (at higher elevation from) the isolation portion.
Regarding claim 20, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the conductive portion comprises silicon, and the isolation portion comprises silicon oxide, in prior art’s device in order to simplify the processing steps of making the device by using conventional materials.
Regarding claim 29, Jung et al. teach in figure 3 and related text that the dielectric liner is sandwich between the contact and the semiconductor layer in the first direction.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
4/30/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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