The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-10, 12-20 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (2014/0353744) in view of Park (2020/0395362) and Beck (2006/0194430).Regarding claim 9, Jung et al. teach in figure 3 and related text a semiconductor structure, comprising:
a substrate 11 having contact openings;
a dielectric liner 21 disposed on sidewalls of the contact openings; and
a bit line structure 100 disposed over the substrate and spanning the contact openings in a first direction;
wherein the bit line structure 100 comprises:
a contact 19A disposed directly above the contact openings; and
a plug layer 25 disposed above the substrate and separated from the contact by a portion of the dielectric liner 21 in the first direction, wherein a top surface of the bit line structure 10 is substantially coplanar with a top surface of the plug layer 25;
wherein the dielectric liner 21 surrounds the bit line structure within the contact openings, and the portion of the dielectric liner 21 extends into the bit line structure and
a top surface of the portion of the dielectric liner 21 is above a top surface of the substrate 11.
Jung et al. do not teach that the plug layer comprises semiconductor, and do you teach that a top surface of another portion of the dielectric liner is coplanar with the top surface of the substrate
Park teaches in related text that the plug layer comprises semiconductor (see e.g. claim 8).
Beck teaches in figure 9 and related text that a top surface of the portion of the dielectric liner 214 is above a top surface of the substrate 204, and a top surface of another portion of the dielectric liner 208 (“208” this is a typo since the dielectric layer, was identified as element 214) is coplanar with the top surface of the substrate.
Beck, Jung et al. and Park are analogous art because they are directed to conductive plugs and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jung et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the plug layer comprises semiconductor, as taught by Park, and to form a top surface of the portion of the dielectric liner is above a top surface of the substrate, and a top surface of another portion of the dielectric liner is coplanar with the top surface of the substrate, as taught by Beck, in Jung et al.’s device, in order to be able to simplify the processing steps of making the device by using conventional conductive material and in order to provide better protection to the device by increasing the length of the liner, respectively.
Note that substitution of materials is not patentable even when the substitution is new and useful. Safetran Systems Corp. v. Federal Sign & Signal Corp. (DC NIII, 1981) 215 USPQ 979.
See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (“The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.”).
Regarding claim 10, Jung et al. teach in figure 3 and related text that the dielectric liner 129 completely covers the sidewalls of the contact openings.
Regarding claim 12, Jung et al. teach in figure 3 and related text that the contact is electrically connected to the substrate at a bottom surface of the contact openings.
Regarding claim 13, Jung et al. teach in figure 3 and related text that a portion of the dielectric liner that intersects the bit line structure is level with the top surface of the contact.
Regarding claim 14, Jung et al. teach in figure 3 and related text that a portion of the dielectric liner that does not intersect the bit line structure is level with the top surface of the substrate.
Regarding claim 15, Jung et al. teach in figure 3 and related text that the bit line structure is in physical contact with the dielectric liner in the first direction.
Regarding claim 16, Jung et al. teach in figure 3 and related text that there is a spacing between the bit line structure and the dielectric liner in the second direction.
Regarding claim 17, Jung et al. teach in figure 3 and related text that the dielectric liner comprises silicon nitride.
Regarding claim 18, Jung et al. teach in figure 3 and related text that the substrate and the semiconductor layer are separated from each other.
Regarding claim 19, Jung et al. teach in figure 3 and related text that the substrate comprises: a conductive portion 11A electrically connected to the bit line structure; and an isolation portion 12 alternately arranged with the conductive portion, wherein the dielectric liner is disposed over (at higher elevation from) the isolation portion.
Regarding claim 20, it would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the conductive portion comprises silicon, and the isolation portion comprises silicon oxide, in prior art’s device in order to simplify the processing steps of making the device by using conventional materials.
Regarding claim 29, Jung et al. teach in figure 3 and related text that the dielectric liner is sandwich between the contact and the semiconductor layer in the first direction.
Response to Arguments
1 Applicants argue that “Beck fails to disclose "a top surface of another portion of the dielectric liner is coplanar with the top surface of the substrate”.", because “Jung's spacer 21 and Beck's dielectric layers 208 and 214 differ in both configuration and function”.
The examiner agrees that “Beck's dielectric layers 208 and 214 differ in both configuration and function”, as argued by applicants. However, the rejection explicitly recites “Beck teaches in figure 9 and related text that a top surface of the portion of the dielectric liner 214 is above a top surface of the substrate 204”. That is, the rejection identifies the dielectric layer as element 214. The recitation, later in the rejection that “a top surface of another portion of the dielectric liner 208” is a typographical error since the dielectric layer was already identified as element 214.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on a1ccess to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
O.N. /ORI NADAV/
9/5/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
Prosecution Insights