DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Claim Rejections - 35 USC § 112 3
A. Claims 1-3, 5-8, and 21-27 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. 3
III. Claim Rejections - 35 USC § 103 5
A. Claims 1-3, 5, 7, 8, and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0159211 (“Rubin”) in view of US 9,515,003 (“Fitzgerald”) and US 2014/0062607 (“Nair”). 5
B. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Rubin in view of Fitzgerald and Nair, as applied to claims 1 and 5, above, and further in view of US 2007/0152321 (“Shi”). 22
IV. Response to Arguments 23
Conclusion 24
[The rest of this page is intentionally left blank.]
I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
A. Claims 1-3, 5-8, and 21-27 are rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement.
The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor at the time the application was filed, had possession of the claimed invention.
Each of independent claims 1 and 27 was amended to include the limitation,
wherein at least one of the embedded active and/or passive circuit components is located wholly under a shadow of a first surface-attachable device from the first plurality of surface-attachable devices;
With regard to this feature, the Instant Specification states the following with regard to the package shown in Fig. 1:
[020] As depicted, the embedded active and/or passive modules 21-24 may include a variety of different circuit components may take any suitable form, shape, size, thickness, or structure. In addition, one or more of the embedded active and/or passive modules 21-24 can be positioned in alignment with an outline or power domain of an IC die/chip module 35, 36. For example, there may be design and performance benefits from aligning the position of one or more surface attachable devices (e.g., die/module 35) so that has a “shadow” within which the underlying embedded circuit components (e.g., capacitors) C1 17 and C2 18) are located.
(Instant Specification: p. 7, ¶ 20; emphasis added)
As shown in Fig. 1, while the capacitor C1 is shown to be “wholly” under the shadow of the cross-section of the die module 35, the capacitor C2 is not “wholly” under the shadow of the cross-section of the die module 35, thereby clarifying that the term “shadow” merely includes overlap between a die module and an “embedded active and/or passive modules 21-24” (supra). Because (1) the term “shadow” includes mere overlap within the meaning expressed in the Instant Application, and (2) only a cross-section is shown, there is no disclosure in the Instant Application that the entirety of an embedded active or passive circuit component is “wholly” within the shadow of a surface attachable device, e.g. one of the die modules 35, 36 in Fig. 1. An overhead view would be required to see this but none is shown in the Instant Application. In addition, the Instant Application nowhere uses the term “wholly” and nowhere else states that the entirety of an “embedded active and/or passive modules 21-24” (supra) is under the shadow of a die module.
Based on the foregoing, there is insufficient disclosure in the Instant Application to show that the Instant Inventors were in possession of the limitation, “at least one of the embedded active and/or passive circuit components is located wholly under a shadow of a first surface-attachable device”. Instead, there is only support for the limitation “at least one of the embedded active and/or passive circuit components is located wholly under a shadow of a first surface-attachable device” in a cross-sectional view, as shown in Fig. 1, as well as the other figures.
As such, claims 1 and 27 introduce new matter not fully supported by the Instant Application.
Claims 2-3, 5-8, and 21-26 are rejected for including the same unsupported feature by depending from claim 1 either directly or indirectly.
III. Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1-3, 5, 7, 8, and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0159211 (“Rubin”) in view of US 9,515,003 (“Fitzgerald”) and US 2014/0062607 (“Nair”).
Claim 1 reads,
1. (Currently Amended) A method for making a package assembly, comprising:
[1a] attaching a first plurality of surface-attachable devices to a temporary carrier,
[1b] where the first plurality of surface-attachable devices have different heights and interconnect surfaces facing the temporary carrier;
[2] encapsulating the first plurality of surface-attachable devices with a molding compound material that completely covers the first plurality of surface-attachable devices;
[3] curing the molding compound material to form a first panel of surface-attachable devices having different heights;
[4] grinding or etching a backside surface of the first panel of surface-attachable devices to thin at least one of the first plurality of surface-attachable devices, thereby forming a thinned panel of surface-attachable devices which have a uniform height;
[5a] removing the temporary carrier from the thinned panel of surface-attachable devices before singulating the thinned panel of surface-attachable devices into a plurality of integrated circuit packages, each comprising an encapsulated plurality of surface-attachable devices which have the uniform height,
[5b] where each integrated circuit package has a planar frontside surface exposing circuit connections on interconnect surfaces of the encapsulated plurality of surface-attachable devices, and
[5c] where each integrated circuit package has a planar heat dissipation surface exposing backsides of the encapsulated plurality of surface-attachable devices;
[6a] providing a multichip package substrate comprising a plurality of embedded active and/or passive circuit components embedded in one or more cavities of a substrate core sandwiched between a first redistribution line stack and a second redistribution line stack, wherein the first redistribution line stack includes conducting elements,
[6b] wherein at least one of the embedded active and/or passive circuit components is located wholly under a shadow of a first surface-attachable device from the first plurality of surface-attachable devices;
[7] attaching the planar frontside surface of each integrated circuit package to the first redistribution line stack to make electric connection between the circuit connections and the conducting elements; and
[8] attaching a heat spreader lid to the planar heat dissipation surface of each integrated circuit package so that the heat spreader lid is thermally connected to dissipate heat from the encapsulated plurality of surface-attachable devices through the planar heat dissipation surface.
With regard to claim 1, Rubin discloses, generally in Figs. 4A-4E,
1. (Currently Amended) A method for making a package assembly, comprising:
[1a] attaching a first plurality of surface-attachable devices 320, 330, 340 to a temporary carrier 305 [¶¶ 69-71; Figs. 4A-4B],
[1b] where the first plurality of surface-attachable devices 320, 330, 340 have different heights [as shown in Fig. 4B] and interconnect surfaces 326, 336, 346 facing the temporary carrier 305 [¶ 71];
[2] encapsulating the first plurality of surface-attachable devices with a molding compound material 420 that completely covers the first plurality of surface-attachable devices 320, 330, 340 [¶ 72; Fig. 4C];
[3] curing the molding compound 420 material to form a first panel of surface-attachable devices 320, 330, 340 having different heights [¶¶ 57, 72; Fig. 4C];
[4] grinding or etching a backside surface of the first panel of surface-attachable devices 320, 330, 340 to thin at least one of the first plurality of surface-attachable devices 320, 330, 340, thereby forming a thinned panel of surface-attachable devices which have a uniform height [¶ 73; Fig. 4D];
[5a] removing the temporary carrier 305 from the thinned panel of surface-attachable devices 320, 330, 340 [¶¶ 73-74; as shown in Fig. 4D] before singulating [along dicing lines D] the thinned panel of surface-attachable devices 320, 330, 340 into a plurality of integrated circuit packages 440, each comprising an encapsulated plurality of surface-attachable devices 320, 330, 340 which have the uniform height [¶ 75; Fig. 4D],
[5b] where each integrated circuit package 440 has a planar frontside surface exposing circuit connections on interconnect surfaces 326, 336, 346 of the encapsulated plurality of surface-attachable devices 320, 330, 340 [as shown in Fig. 4D], and
[5c] where each integrated circuit package 440 has a planar heat dissipation surface exposing backsides of the encapsulated plurality of surface-attachable devices 320, 330, 340 [as shown in Figs. 4D and 4E];
[6a] providing a multichip package substrate 380 [¶ 64] comprising a … first redistribution line stack 386 [¶ 64] … wherein the first redistribution line stack includes conducting elements 386,
[6b] … [not taught] …
[7] attaching the planar frontside surface of each integrated circuit package 440 to the first redistribution line stack 386 [by means of solder bumps 430] to make electric connection between the circuit connections 326, 336, 346 and the conducting elements 386 [¶ 76]; and
[8] … [not taught] …
With regard to feature [6a]-[6b] of claim 1,
[6a] providing a multichip package substrate comprising a plurality of embedded active and/or passive circuit components embedded in one or more cavities of a substrate core sandwiched between the first redistribution line stack and a second redistribution line stack, wherein the first redistribution line stack includes conducting elements,
[6b] wherein at least one of the embedded active and/or passive circuit components is located wholly under a shadow of a first surface-attachable device from the first plurality of surface-attachable devices;
As explained above, Rubin teaches a multichip package substrate, but does not indicate that there are “a plurality of embedded active and/or passive circuit components embedded in one or more cavities of a substrate core sandwiched between a first redistribution line stack and a second redistribution line stack”.
Fitzgerald, like Rubin, teaches a package assembly 102 including a plurality of integrated circuit dies both attached to, and electrically connected to, a package substrate 104 by solder balls 108 (Fitzgerald: Fig. 1; col. 2, line 54-col. 3, line 10; col. 4, line 38). Only one integrated circuit die 106 is shown in Fig. 1, but Fitzgerald states that “additional dies”, e.g. “memory, a specialized processor, passive devices or other components … attached to lands or pads on the substrate [104] and secured and sealed with an underfill or in any other way, depending on the intended use of the package [102]” (Fitzgerald: col. 3, lines 11-24).
Fitzgerald further teaches that the package substrate 104 includes a plurality of embedded active and/or passive circuit components (e.g., air core inductors (ACIs) 121-125 (Fitzgerald: col. 3, lines 44-45) or other passive devices [col. 3, lines 25-43]) sandwiched between the first redistribution line stack (that includes the wiring traces 162 [col. 6, line 7] and wiring traces connected to the solder balls 108 that are not shown and metal plates 144 that “may be conventional traces similar to those used for wiring” [col. 4, lines 28-31]) and a second redistribution line stack (that includes at least lateral trace 154 [col. 6, line 1] as well as the metal plates 144 below the ACIs shown in Fig. 1, as well as the wiring traces connected to the solder balls 114 on the bottom surface of the package substrate 104)—as required by feature [6a] of claim 1. In this regard, Fitzgerald states,
Even if the substrate [104] material is a poor thermal conductor, it will have embedded electrically conducting layers and connecting vias to connect the die 106 above to the solder ball grid array 114 below. These electrically conducting layers, typically copper, will also conduct heat and tend to distribute heat throughout the substrate and to any components that are electrically or thermally connected to the substrate [104], such as the IHS [110], the solder ball arrays, and the ambient environment.
(Fitzgerald: col. 6, lines 53-61; emphasis added)
Thus, although not shown in Fig. 1, Fitzgerald explicitly states that there are electrically-conducting copper wires embedded in the substrate 104 that electrically connect the die 106 to the to the solder ball grid array 114 below (id.). As such, the not-shown electrically-conducting copper wires embedded in the substrate 104 (id.) that are above the ACIs 121-125 and electrically connected to the solder balls 108 to connect to the die 106 read on the claimed “first redistribution line stack”, and the electrically-conducting copper wires, e.g. including “lateral trace 154”, embedded in the substrate 104 (id.) that are below the ACIs 121-125 and electrically connected to the solder balls 114 read on the claimed “second redistribution line stack”.
The package in Fig. 1 of Fitzgerald also shows the limitations of feature [6b] of claim 1, as follows:
wherein at least one [i.e. any of ACIs 121, 122, 123 and 124] of the embedded active and/or passive circuit components 121-125 is located wholly under a shadow of a first surface-attachable device 106 from the first plurality of surface-attachable devices;
Just as in the Instant Application, the ACIs 121, 122, 123, and 124 are “wholly under a shadow of a first surface-attachable device 106” in a cross-section view, which is all for which there is support in the Instant Application, as explained in the rejection under 35 USC 112(a), above.
While Fitzgerald shows that the ACIs 121-125 and other passive components are embedded in the material of the package substrate, Fitzgerald does not show that the ACIs 121-125 or other passive components are “embedded in one or more cavities of a substrate core sandwiched between the first redistribution line stack and a second redistribution line stack”.
Nair, like Fitzgerald, teaches both active 104 and passive 124 circuit components (Nair: ¶ 30) in separate cavities 105 formed on a core layer 102 (Nair: e.g. Figs. 1C, 4C; ¶¶ 20, 47). The passive devices include inductors, as well as, a band pass filter, capacitor, resistor, or crystal oscillator for clock generation (Nair: ¶ 26). Nair further teaches the process of manufacturing the package substrate 101, 401 that includes forming the cavity 405 in the core substrate 402 (Figs. 4A-4B; ¶¶ 45-47), inserting an active circuit component 404 and filling the excess space with build-up material (Fig. 4C: ¶¶ 45-52), and then forming the upper and lower interconnect layers, i.e. the claimed first and second redistribution line stacks, sandwiching the core substrate 102 (Figs. 4D-4F; ¶¶ 52-53).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to manufacture the package substrate of Fitzgerald to include the formation of a plurality of cavities formed in a substrate core to embed each of the ACIs 121-125 and the active circuit component, i.e. the thermoelectric cooler 142, and then form upper and lower redistribution layer stacks sandwiching the core substrate, as taught in Nair, because Fitzgerald lacks the details of manufacturing the package substrate having embedded active and passive components, such that one having ordinary skill in the art would use known methods and materials in order to form the package substrate, such as the method and materials of Nair. (See MPEP 2143.)
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the package substrate having ACIs embedded in cavities between upper and lower redistribution line stacks of Fitzgerald/Nair in the package substrate of Rubin, in order to provide a “fully integrated voltage regulator (FIVR)” (Fitzgerald: col. 2, lines 9-15), which allows “active power management”, as taught by Fitzgerald (at col. 1, lines 23-25; col. 3, lines 25-43). As such, Fitzgerald may be seen as an improvement to Rubin in this aspect. (See MPEP 2143.)
Finally, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to position at least one of the ACIs of the package substrate “wholly under a shadow of a first surface-attachable device [i.e. any one of 320, 330, 340]” in a cross-sectional view in Rubin, because Fitzgerald shows that this relative positioning between the ACIs and the surface mount device is suitable for a package device include a surface-mountable device and an embedded ACI.
With regard to feature [8] of claim 1 and claim 2,
[8] attaching a heat spreader lid to the planar heat dissipation surface of each integrated circuit package so that the heat spreader lid is thermally connected to dissipate heat from the encapsulated plurality of surface-attachable devices through the planar heat dissipation surface.
2. (Previously Presented) The method of claim 1, where attaching the heat spreader lid comprises attaching the heat spreader lid to make a thermal conduction path to the plurality of embedded active and/or passive circuit components in the multichip package substrate over thermal conducting elements in the first redistribution line stack formed on the multichip package substrate.
Rubin does not disclose a heat spreader, as required by feature [8] of claim 1 and claim 2.
Fitzgerald, in addition, teaches a heat spreader 110 coupled to the integrated circuit die 106 by means of a thermal interface material (TIM) 112—as required by feature [8] of claim 1— as well as being coupled to at least one ACI 121 by means of a thermal core 131, vertical via 145, metal plates 144, and TIM 146 (Fitzgerald: col. 2, lines 63-67; col. 4, lines 38-43; col. 5, lines 1-17), as required by claim 2.
In addition, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the heat spreader lid 110, TIMs 146 and 112 of Fitzgerald, over and attached to the package substrate 380 of Rubin, as well as the associated thermal dissipation elements, i.e. the metal cores (e.g. 131), thermal vias 145, and plates 144 of Fitzgerald, within the package substrate 380 of Rubin, in order to dissipate heat generated from the integrated circuit dies, e.g. 106, and the ACIs, e.g. 121, to the heat spreader lid 110. As such, Fitzgerald may be seen as an improvement to Rubin in these aspects. (See MPEP 2143.)
In the alternative, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to form a package assembly including the integrated circuit package, i.e. “multi-chip module 440” of Rubin (¶ 75)”, mounted to the package substrate of Fitzgerald/Lambert, because Fitzgerald indicates that the package substrate 104 including the FIVR and the heat-dissipation components has generally utility for any of a variety of integrated circuit dies (Fitzgerald: col. 3, lines 11-43). The benefit would be to provide the collection of dies that Fitzgerald suggests may be present (id.) in a single attachable package, as taught by Rubin. As such, Rubin may be seen as an improvement to Fitzgerald, in this aspect.
This is all of the features of claims 1 and 2.
With regard to claim 3, Rubin further discloses,
3. (Previously Presented) The method of claim 1,
[1] where attaching the plurality of surface-attachable devices 320, 330, 340 to the temporary carrier 305 comprises attaching a plurality of integrated circuit dice 320, 330, 340 have different heights to the temporary carrier 305,
[2] where a landing pad [i.e. the exposed bottom surfaces of 326, 336, 346] is formed at each of the first interconnect surfaces 326, 336, 346.
Note that the Instant Application makes no distinction between the landing pads 110 shown in Figs. 2a-2e of the Instant Application the interconnect surfaces—which are given no reference character in the drawings. In this regard the Instant Application states only that “each integrated circuit die includes an interconnect surface with landing pad connections” (Instant Specification: ¶ 74). As such, Rubin has been interpreted consistent with the Instant Application with regard to the feature, “where a landing pad connection [i.e. the exposed bottom surfaces of 326, 336, 346] is formed at each of the first interconnect surfaces 326, 336, 346”.
With regard to claims 5 and 7, Rubin modified according to Fitzgerald, as explained under claim 1, further teaches,
5. (Original) The method of claim 1, further comprising forming one or more thermally conductive interface layers [i.e. TIM 112] on the planar heat dissipation surface of each integrated circuit package 440 before attaching the heat spreader lid 110 to the planar heat dissipation surface of each integrated circuit package 440.
7. (Previously Presented) The method of claim 1, further comprising
[1] forming one or more thermally conductive adhesive layers [TIMs 112 and 146 of Fitzgerald] on the multichip package substrate [380 of Rubin modified according to Fitzgerald (supra)] or heat spreader lid 110 [of Fitzgerald].
[2] to attach the heat spreader lid 110 to the multichip package substrate 380 and
[3] to provide a heat dissipation path [i.e. TIM 146] to the plurality of embedded active and/or passive circuit components [e.g. ACI 121 of Fitzgerald] in the multichip package substrate 380 over thermal conducting elements [144, 145 of Fitzgerald] in the first redistribution line stack formed on the multichip package substrate 380.
With regard to claim 8, Rubin further discloses,
8. (Original) The method of claim 1, where the plurality of surface-attachable devices 320, 330, 340 includes devices from a group consisting of integrated circuit devices, active devices, passive devices, and/or photonics components [Rubin: ¶ 54].
With regard to claim 21, Nair further teaches,
21. (Currently Amended) The method of claim 1, where the multichip package substrate 101 comprises one or more intervening insulation layers [i.e. “buildup layer material, for example ABF” (Nair: ¶ 21)] which isolate the one or more cavities 105 of the substrate core 102 from one another to insulate the plurality of embedded active 104 and/or passive 124 circuit components from one another [as shown in Figs. 1C and 4B-4C].
Nair states that, “the remaining space in cavity 105 between active die 104 and in-situ electromagnetic shield 108 is filled with buildup layer material, for example ABF” (Nair: ¶ 21, last sentence) and that “the space remaining between active die 404 and in-situ electromagnetic shield 408 may be filled with buildup layer material” (Nair: ¶ 52).
Inasmuch as the use of the substrate core with cavities is obvious (supra), it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, in addition, to include the associated “buildup layer material, for example ABF” (Nair: ¶ 21) in the cavities 105 surrounding the ACIs 121-125 of Fitzgerald in order to protect the ACIs, as taught by Nair.
Claim 22 reads,
22. (Currently Amended) The method of claim 1, wherein the one or more cavities of the substrate core comprises a plurality of cavities.
See explanation above under claim 1.
With regard to claim 23, Nair further teaches,
23. (Previously Presented) The method of claim 1, where the substrate core 102, 402 is formed with a first insulating material 110A/110B, 410A/410B that is sandwiched between the first redistribution line stack and the second redistribution line stack [Nair: ¶ 22; Fig. 1C, 4C].
As stated in the explanation under claim 1, above, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to manufacture the package substrate of Fitzgerald to include a plurality of cavities in a substrate core to embed each of the ACIs 121-125 and upper and lower redistribution layers sandwiching the core substrate, as taught in Nair. So modified, at least the first insulating material 110A/110B, 410A/410B of Nair is sandwiched between the first (i.e. upper) redistribution line stack and the second (i.e. lower) redistribution line stack.
Claim 24 reads, Nair further teaches,
24. (Previously Presented) The method of claim 23, where the first insulating material 110A/110B, 410A/410B is selected from a group consisting of plastic or fiberglass [e.g. polyimide (Nair: ¶ 22)].
Again, using the process and materials of Nair to make the package substrate 104 of Fitzgerald that is used in Rubin (supra) will include the insulating material of Nair, e.g. a polyimide.
Claims 25 and 26 reads,
25. (Previously Presented) The method of claim 22, where an embedded active circuit component is formed and positioned in at least one of the plurality of cavities of the multichip package substrate.
26. (Previously Presented) The method of claim 22, where an embedded passive circuit component [i.e. the ACIs 121-125 of Fitzgerald] is formed and positioned in at least one of the plurality of cavities [610 of Lambert formed in the ] of the multichip package substrate.
As stated above, Fitzgerald teaches a thermoelectric cooler 142 embedded in the package substrate 104, which Fitzgerald called an active element:
The first heat sink is a thermo-electric element 142. This element actively pumps heat away from the embedded inductor. In some embodiments, the thermo-electric cooler element may be a cooler using the Peltier effect, for example a component constructed of bismuth-telluride elements sandwiched between parallel plates. Thermoelectric coolers may be considered to be active elements. The active device may be powered externally or through the electrical traces in the substrate.
(Fitzgerald: col. 4, lines 12-20; emphasis added)
The reasons for embedding the active circuit component, i.e. the thermoelectric cooler 142 of Fitzgerald as well as the passive components, i.e. the ACIs 121-125 of Fitzgerald, in separate cavities in the core substrate 102 of Nair, is already stated under claim 1.
Claim 27 reads,
27. (Previously Presented) A method for making a package assembly, comprising:
[1a] attaching a first plurality of surface-attachable devices directly to a first temporary carrier,
[1b] where the first plurality of surface-attachable devices have different heights and first interconnect surfaces facing the temporary carrier;
[2] encapsulating the first plurality of surface-attachable devices with a molding compound material that completely covers the first plurality of surface-attachable devices;
[3] curing the molding compound material to form a first panel of surface-attachable devices having different heights;
[4] grinding or etching a backside surface of the first panel of surface-attachable devices to thin at least one of the first plurality of surface-attachable devices, thereby forming a thinned panel of surface-attachable devices which have a uniform height and which are exposed at a backside surface of the thinned panel of surface-attachable devices;
[5] attaching a second temporary carrier directly to the backside surface of the thinned panel of surface-attachable devices;
[6] removing the first temporary carrier from the thinned panel of surface-attachable devices to expose the first interconnect surfaces;
[7] attaching a plurality of interconnect conductor structures to the first interconnect surfaces exposed on the thinned panel of surface-attachable devices;
[8a] singulating the thinned panel of surface-attachable devices into at least a first integrated circuit package comprising an encapsulated plurality of surface-attachable devices which have the uniform height,
[8b] where the first integrated circuit package has a planar frontside surface with interconnect conductor structures connected to corresponding first interconnect surfaces, and
[8c] where the first integrated circuit package has a planar heat dissipation surface exposing backsides of the encapsulated plurality of surface-attachable devices;
[9a] providing a multichip package substrate comprising a substrate core formed with an insulating material in which a plurality of cavities are formed with a plurality of embedded active and/or passive circuit components separately embedded in the plurality of cavities,
[9b] wherein at least one of the embedded active and/or passive circuit components is located wholly under a shadow of a first surface-attachable device from the first plurality of surface-attachable devices;
[10] attaching the planar frontside surface of the first integrated circuit package to a first surface of the multichip package substrate to make electric connection between the plurality of embedded active and/or passive circuit components and the encapsulated plurality of surface-attachable devices; and
[11] attaching a heat spreader lid to the planar heat dissipation surface of the first integrated circuit package so that the heat spreader lid is thermally connected to dissipate heat from the encapsulated plurality of surface-attachable devices through the planar heat dissipation surface.
With regard to claim 27, Rubin discloses, generally Figs. 4A-4E,
27. (New) A method for making a package assembly, comprising:
[1a] attaching a first plurality of surface-attachable devices 320/326, 330/336, 340/346 directly to a first temporary carrier 305 [¶¶ 69-71; Figs. 4A-4B],
[1b] where the first plurality of surface-attachable devices 320/326, 330/336, 340/346 have different heights [as shown in Fig. 4B] and interconnect surfaces 326, 336, 346 facing the temporary carrier 305 [¶ 71];
[2] encapsulating the first plurality of surface-attachable devices with a molding compound material 420 that completely covers the first plurality of surface-attachable devices 320/326, 330/336, 340/346 [¶ 72; Fig. 4C];
[3] curing the molding compound 420 material to form a first panel of surface-attachable devices 320/326, 330/336, 340/346 having different heights [¶¶ 57, 72; Fig. 4C];
[4] grinding or etching a backside surface of the first panel of surface-attachable devices 320/326, 330/336, 340/346 to thin at least one of the first plurality of surface-attachable devices 320/326, 330/336, 340/346, thereby forming a thinned panel of surface-attachable devices [i.e. “multi-chip module 440”] which have a uniform height and which are exposed at a backside surface of the thinned panel of surface-attachable devices 440 [¶ 73: “(i) planarizing the upper surface of the structure to thin down the molding layer 420 and to make the backside surfaces of the IC chips 320, 330, and 340 coplanar” (emphasis added); Figs. 4C-4D];
[5] attaching a second temporary carrier 365 directly to the backside surface of the thinned panel of surface-attachable devices 440 [¶ 73: “(ii) bonding a temporary' wafer handler 365 to the planarized surface of the structure” (emphasis added); Fig. 4D];
[6] removing the first temporary carrier 305 from the thinned panel of surface-attachable devices 440 to expose the first interconnect surfaces 326, 336, 346 [¶ 73: “(iii) removing the semiconductor substrate layer 305 to release the interconnect bridge devices 312 and 314” (emphasis added); Fig. 4D];
[7] attaching a plurality of interconnect conductor structures 430 to the first interconnect surfaces exposed on the thinned panel of surface-attachable devices [¶ 73: “(iv) forming solder bumps 430 on the exposed ends of the metallic pillars 326, 336, and 346” (emphasis added); Fig. 4D];
[8a] singulating the thinned panel of surface-attachable devices into at least a first integrated circuit packages 440, each comprising an encapsulated plurality of surface-attachable devices 320/326, 330/336, 340/346 which have the uniform height [¶ 75: “Following the formation of the solder bumps 430, a dicing process is performed to dice the wafer-level molding layer 420 and thereby separate the individual chip modules (e.g., multi-chip module 200, FIG. 2) of the bridge wafer 300.” Figs. 4D-4E],
[8b] where the first integrated circuit package 440 has a planar frontside surface with interconnect conductor structures 430 connected to corresponding first interconnect surfaces 326, 336, 346, and
[8c] where the first integrated circuit package 440 has a planar heat dissipation surface exposing backsides of the encapsulated plurality of surface-attachable devices 320/326, 330/336, 340/346 [as shown in Fig. 4E];
[9a] providing a multichip package substrate 380 comprising a … a plurality of embedded active [i.e. thermoelectric cooler 142] and/or passive circuit components [i.e. ACIs 121-125] separately embedded in the … [package substrate 380],
[9b] … [not taught] …
[10] attaching the planar frontside surface of the first integrated circuit package 440 to a first surface [upper surface] of the multichip package substrate 380 to make electric connection between the … [package substrate 380] … and the encapsulated plurality of surface-attachable devices 320/326, 330/336, 340/346; and
[11] … [not taught] …
With regard to features [1a]-[1b] of claim 27, Rubin states that “the IC chips 320, 330, and 340 comprise respective area arrays of metallic pillars 326, 336, and 346 (e.g., copper pillars) which are formed on regions of the active surfaces of the IC chips 320, 330, and 340 outside the bridge regions”. Therefore, the IC chips are “directly” attached to the first temporary carrier 305, as claimed.
With regard to feature [9a]-[9b] of claim 27,
[9a] providing a multichip package substrate comprising a substrate core formed with an insulating material in which a plurality of cavities are formed with a plurality of embedded active and/or passive circuit components separately embedded in the plurality of cavities,
[9b] wherein at least one of the embedded active and/or passive circuit components is located wholly under a shadow of a first surface-attachable device from the first plurality of surface-attachable devices;
This feature has been explained under features [6a]-[6b] of claim 1, said explanation incorporated here.
With regard to feature [10] of claim 27,
[10] attaching the planar frontside surface of the first integrated circuit package to a first surface of the multichip package substrate to make electric connection between the plurality of embedded active and/or passive circuit components and the encapsulated plurality of surface-attachable devices; and
Because Rubin does not teach embedded active and/or passive circuit components in the package substrate, Rubin does not teach that the plurality of surface-attachable devices 320/326, 330/336, 340/346 are attached to the package substrate so as to make electrical connection to said embedded active and/or passive circuit components, as required by feature [10].
As explained above, under claim 1, including the embedded active and/or passive circuit components of Fitzgerald in the package substrate of Fitzgerald/Nair is the package substrate of Rubin is obvious. To repeat, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the package substrate having ACIs embedded in cavities between upper and lower redistribution line stacks of Fitzgerald/Nair in the package substrate of Rubin, in order to provide a “fully integrated voltage regulator (FIVR)” (Fitzgerald: col. 2, lines 9-15), which allows “active power management”, as taught by Fitzgerald (at col. 1, lines 23-25; col. 3, lines 25-43). The “active power management” referred to in Fitzgerald is the power management of the attached integrated circuit die 106, wherein the voltage regulator circuit(s) are “on the die” while the associated inductors, i.e. ACIs 121-125, are embedded in the package substrate 380—thereby requiring an electrical connection therebetween—Fitzgerald stating in this regard,
The techniques described herein are particularly well suited for ACIs of a FIVR (Fully Integrated Voltage Regulator) but may be applied to other embedded coils for different applications. The coils may be part of an inductor, transformer, or other passive device. There may also be embedded coils for different functions with the same or different cooling techniques applied. In a FIVR, a multiple core die, typically but not necessarily a processor, has one or more voltage regulators formed on the die. Accordingly, the voltage regulator is in or very near the circuitry for which it supplies regulated voltage. This provides a precise and easily controlled voltage to the circuitry and allows parts of the die to be turned off or turned down to save power and to reduce the generation of waste heat. The voltage regulators each use an inductor that is not integrated on the die but instead is embedded within the package substrate. The greater space available within the package substrate allows for a larger higher quality inductor to be fabricated at lower overall cost than if the inductor were formed on the die.
(Fitzgerald: col. 3, lines 25-43; emphasis added)
The ACI has a first set of contacts 310 or electrodes formed as vertical vias over the horizontal coil layers that connect to the power supply switch within the die as coil inputs. A second set of contacts 312 or electrodes connect to the voltage regulator within the die as outputs. The particular inputs and outputs may be adapted to suit any particular voltage regulator design.
(Fitzgerald: col. 7, lines 21-28; emphasis added)
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include at least one voltage regulator circuit in at least one of the surface-attachable devices 320/326, 330/336, 340/346 of Rubin and to include the associated electrical connections to the core-cavity embedded ACIs 121-125 of Fitzgerald in the package substrate of Fitzgerald/Nair used in Rubin, in order to provide the “fully integrated voltage regulator (FIVR)” (Fitzgerald: col. 2, lines 9-15), which allows “active power management”, as taught by Fitzgerald (at col. 1, lines 23-25; col. 3, lines 25-43), i.e. the same reason as provided above. As such, again, Fitzgerald may be seen as an improvement to Rubin in this aspect. (See MPEP 2143.)
With regard to feature [11] of claim 27,
[11] attaching a heat spreader lid to the planar heat dissipation surface of the first integrated circuit package so that the heat spreader lid is thermally connected to dissipate heat from the encapsulated plurality of surface-attachable devices through the planar heat dissipation surface.
This feature has been explained under feature [8] of claim 1, said explanation incorporated here.
This is all of the features of claim 27.
B. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Rubin in view of Fitzgerald and Nair, as applied to claims 1 and 5, above, and further in view of US 2007/0152321 (“Shi”).
Claim 6 reads,
6. (Original) The method of claim 5, where forming one or more thermally conductive interface layers comprises:
[1] forming a first backside metallization layer on the planar heat dissipation surface of each integrated circuit package; and
[2] forming a thermal interface layer on the backside metallization layer of each integrated circuit package.
The prior art of Rubin in view of Fitzgerald and Lambert, as explained above, teaches each of the features of claims 1 and 5.
Fitzgerald does not teach forming a backside metallization on the backside surface of the integrated circuit dies 106 before forming the TIM 112.
Shi, like Fitzgerald, teaches integrated circuit chips 44, 46 mounted on a package substrate 42 using solder balls 48, 50 and a heat spreader lid 26 attached to the package substrate 42 and coupled to the integrated circuit chips 44, 46 by a TIM, i.e. cold-formed solder 20 (Shi: Figs. 7-9; ¶ 25). Shi further teaches that the backside of the integrated circuit chips 44, 46 are metallized with three metal layers 64/66/68 to promote bonding to the solder 20 (Shi: ¶¶ 26-27).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to metallize the backside surface of the integrated circuit package 440 of Rubin with the three metal layers 64/66/68 of Shi, and to use solder as the TIM of Fitzgerald used in the package assembly of Rubin/Fitzgerald, in order to bond the heat spreader lid 110 to the integrated circuit package 440 and thereby ensure a strong thermal interface therebetween.
This is all of the features of claim 6.
IV. Response to Arguments
Applicant’s arguments filed 02/25/2026 have been fully considered but they are not persuasive.
Applicant argues that the applied prior art does not teach the newly added limitation,
wherein at least one of the embedded active and/or passive circuit components is located wholly under a shadow of a first surface-attachable device from the first plurality of surface-attachable devices;
arguing the following:
In contrast to the recited claim limitations, Applicant would first note the Examiner's concession that "Fitzgerald does not show that the ACIs 121-125 or other passive components are 'embedded in one or more cavities of a substrate core sandwiched between the first redistribution line stack and a second redistribution line stack'." See, Office Action, p. 10. As for any attempt to remedy this deficiency by relying on the Nair reference, Applicant would note that the Nair reference discloses embedded devices 104, 124 that extend outside of the shadow of the devices 118A/B. See, Nair, Figures 1C, 2C, 3, and 41. In each of the Nair figures, the embedded components extend outside of the shadow from an overlying surface-attachable device. …
(Remarks filed 02/25/2026: p. 8)
As explained in the rejection, Examiner finds that the orientation of the ACIs 121-124 in Fig. 1 of Fitzgerald are configured relative to the surface mountable device 106 as required by the newly added claim limitation, quoted above. Simply because Nair does not show the position of the ACIs in the cavities are positioned wholly under the shadow of any one of the surface mounted dies does not negate the teaching in Fitzgerald directed to the relative positions of the ACIs 121-124 and the surface mountable device 106. As such, Applicant’s argument is not found persuasive.
Conclusion
Applicant’s amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814