Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to an Office action mailed on 12/16/2025 ("12-16-25 OA"), the Applicant substantively amended elected claims 16, 18-22 and 29 and non-elected, withdrawn claims 36-39 on 03/17/2026 ("03-17-26 Response").
Currently, claims 16-31 and 36-39 are pending with previously-withdrawn claims 36-39 remaining withdrawn.
Response to Arguments
Applicant's amendments to claim 18 have overcome the 35 U.S.C. 112(b) rejection of claim 18 set forth on page 3 under line item number 1 of the 12-16-25 OA.
Applicant's amendments to the independent claims 16 and 22 have overcome the 35 U.S.C. 102(a)(1) rejection of claims 16-18, 21-28 and 31 as being anticipated by Yu set forth starting on page 4 under line item number 2 of the 12-16-25 OA.
Substantive-amendments to the independent claims 16 and 22 required further consideration and updated search. New grounds of rejection are provided below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 16-18 and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2023/0238376 A1 to Lee et al. ("Lee").
Fig. 6 of Lee has been provided to support the rejection below:
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Regarding independent claim 16, Lee teaches a method of forming a semiconductor structure, comprising:
attaching a semiconductor die 104 (para [0015] - “semiconductor die 104”) to an interposer 243 (para [0039] - “substrate 243”) such that the semiconductor die 104 is electrically coupled to the interposer 243;
forming a molding compound die frame 244 (para [0039] - “encapsulant 244”; para [0024] - “Encapsulant 170 can be a polymer composite material, such as an epoxy resin, epoxy acrylate, or polymer with or without a filler added.”) in contact with the semiconductor die 104 and the interposer 243, wherein the molding compound die frame 244 is located on a side of the semiconductor die 104; and
forming a capping layer 262 (para [0042] - “Shielding layer 262 is formed using any suitable metal deposition technique, e.g., chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtered material can be copper, steel, aluminum, gold, titanium, combinations thereof, or any other suitable conductive material. In some embodiments, shielding layer 262 can be made by sputtering on multiple layers of differing material, e.g., stainless steel-copper-stainless steel or titanium-copper.”) that is disposed on a top surface of the semiconductor die 104 and on a top portion of the molding compound die frame 244 on the side of the semiconductor die 104, and on a side surface of the molding compound die frame 244, wherein the capping layer 262 includes sidewalls disposed on a package side underfill material 160 (para [0023] - “A mold under-fill (MUF) 160”), and wherein the forming the capping layer 262 includes depositing metals (para [0042]).
Regarding claim 17, Lee teaches forming the capping layer 262 that further comprises forming the capping layer as a continuous structure that covers respective surfaces of the semiconductor die 104, the molding compound die frame 244, and the interposer 242.
Regarding claim 18, Lee teaches attaching the interposer 242 to a packaging substrate 238 such that the interposer 242 is electrically coupled to the packaging substrate 238, and
wherein forming the capping layer 262 that further comprises forming the capping layer as a continuous structure covering respective (top) surfaces of the semiconductor die 104, the molding compound die frame 244, and the packaging substrate 238.
Regarding claim 21, Lee teaches forming a package substrate 238, wherein the interposer 243 is electrically coupled to the package substrate 238;
forming a dielectric layer 232 (para [0038] - “adhesive tape 232”) on the top surface of the package substrate 238;
forming a pinning structure 239 (para [0039] - “conductive vias 239”) that is formed as a plated through hole protruding form the dielectric layer 232 and a top surface of the pinning structure is covered by a portion of the capping layer 262.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 19, 20, 29 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Lee and further in view of Patent No. US 9,269,673 B1 to Lin et al. (“Lin”).
Regarding claims 19 and 29, Lee does not specify that forming the capping layer further comprises an electroplating process to deposit one or more of the metals from stainless steel, copper, nickel, tungsten, aluminum, magnalium, titanium, silver or gold to form a bulk layer of the capping layer.
Lin teaches forming the capping layer 130 further comprises an electroplating process (col. 9, ln 6-22 - “…(ii) forming the first shielding layer 130b and the second shielding layer 130c by…electroplating…”) to deposit one or more of the metals from stainless steel, copper, nickel, tungsten, aluminum, magnalium, titanium, silver or gold (col. 5, ln 1-17 - “In one embodiment, the first shielding layer 130b is formed of, for example, Cu, silver…”; col. 5, ln 18-38 - “…the second shielding layer 130c is formed of nickel (Ni)…”) to form a bulk layer 130b, 130c of the capping layer 130.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the method of Lee by employing electroplated capping layer having different layers of Lin so as to improve the shielding effectiveness (Lin, col. 6, ln 1-11).
Regarding claims 20 and 30, Lee does not specify that the capping layer that further comprises forming the capping layer that comprises performing a sputtering process to deposit one or more of the metals from stainless steel, TiCu, TiW, TiN, or TaN to form a seed layer of the capping layer, and
wherein the seed layer is formed before the bulk layer is formed.
Lin teaches forming the capping layer that further comprises forming the capping layer 130 that comprises performing a sputtering process (col. 9, ln 6-22 - “(i) forming the seed layer 130a by…sputtering”) to deposit one or more of the metals from stainless steel, TiCu, TiW, TiN, or TaN (col. 4, ln 61-67 - “The seed layer 130a is formed of, for example…stainless steel…”) to form a seed layer 130a of the capping layer 130, and
wherein the seed layer 130a is formed before the bulk layer is formed 130b and/or 130c.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the method of Lee by employing sputtered capping layer having different layers of Lin so as to improve the shielding effectiveness (Lin, col. 6, ln 1-11).
B. Prior-art rejections based on Chen
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 22-25, 27, 28 and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2019/0074264 A1 to Chen et al. ("Chen").
Fig. 1 of Chen has been annotated to support the rejections below:
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Regarding independent claim 22, Chen teaches a method of forming a semiconductor structure (para [0045] - “FIG. 1 illustrates a cross-sectional view of some embodiments of a semiconductor package structure 1 according to an aspect of the present disclosure. The semiconductor package structure 1 may be a semiconductor package structure with double side molding, and includes, but not limited to, a first substrate 10, at least one first semiconductor element 12, a second substrate 24, a plurality of first electrical connectors 26, a first encapsulant 18, at least one second semiconductor element 20 and a second encapsulant 22.”), comprising:
attaching a semiconductor die 20 to an interposer 10 such that the semiconductor die 20 is electrically coupled to the interposer 10, wherein the interposer 10 is coupled to a packaging substrate 24 with a package side underfill material 18 (para [0053] - “at least a portion of the first encapsulant 18 may surround and protect the first interconnection elements 124 (e.g., a molded underfill (MUF)).”); and
forming a capping layer 30 (para [0095] - “The shielding layer 30 may include at least one metal layer and may be formed by plating or sputtering.”) such that a portion of the capping layer 30 is in (indirect) contact with a top surface of the semiconductor die 20, wherein the capping layer 30 includes sidewalls disposed on the package side underfill material 18 and on the packaging substrate 24, and wherein forming the capping layer 30 includes depositing metals (plating or sputtering).
Regarding claim 23, Chen teaches attaching a second semiconductor die SD2 to the interposer 10 such that the second semiconductor die SD2 is electrically attached to the interposer 10.
Regarding claim 24, Chen teaches a second capping layer 22 (para [0045] - “a second encapsulant 22”) that covers a top surface of the second semiconductor die SD2.
Regarding claim 25, Chen teaches the capping layer 30 has a first thickness and the second capping layer 22 has a second thickness that is different than the first thickness.
Regarding claim 27, Chen teaches forming the capping layer 30 that further comprises forming the capping layer 30 as a continuous structure that covers respective surfaces of the semiconductor die 20, and the interposer 10.
Regarding claim 28, Chen teaches attaching the interposer 10 to the packaging substrate 24 such that the interposer 10 is electrically coupled to the packaging substrate 24, and
wherein forming the capping layer 30 further comprises forming the capping layer 30 as a continuous structure covering respective surfaces of the semiconductor die and the packaging substrate 24.
Regarding claim 31, Chen teaches a method of forming a semiconductor structure (see Fig. 4; para [0063] - “The semiconductor package structure 1c of FIG. 4 is similar to the semiconductor package structure 1a as shown in FIG. 2, except that the semiconductor package structure 1c of FIG. 4 further includes a circuit board 32 (e.g., PCB), and that the semiconductor package structure 1a is mounted onto the circuit board 32 by, for example, surface mount technology (SMT).”; para [0045] - “FIG. 1 illustrates a cross-sectional view of some embodiments of a semiconductor package structure 1 according to an aspect of the present disclosure. The semiconductor package structure 1 may be a semiconductor package structure with double side molding, and includes, but not limited to, a first substrate 10, at least one first semiconductor element 12, a second substrate 24, a plurality of first electrical connectors 26, a first encapsulant 18, at least one second semiconductor element 20 and a second encapsulant 22.”), comprising:
attaching a semiconductor die 20 to an interposer 10 such that the semiconductor die 20 is electrically coupled to the interposer 10, wherein the interposer 10 is (indirectly) coupled to a packaging substrate 32 with a package side underfill material 18 (para [0053] - “at least a portion of the first encapsulant 18 may surround and protect the first interconnection elements 124 (e.g., a molded underfill (MUF)).”); and
forming a capping layer 30 (para [0095] - “The shielding layer 30 may include at least one metal layer and may be formed by plating or sputtering.”) such that a portion of the capping layer 30 is in (indirect) contact with a top surface of the semiconductor die 20, wherein the capping layer 30 includes sidewalls disposed on the package side underfill material 18 and on the packaging substrate 24, and wherein forming the capping layer 30 includes depositing metals (plating or sputtering),
forming a dielectric layer 24 (para [0061] - “second substrate 24”) on a top surface of the package substrate 32; and
forming a pinning structure 28 (para [0062] - “thermal vias 28”) that is formed as a plated through hole protruding form the dielectric layer 24 and a top surface of the pinning structure 28 is covered by a portion of the capping layer 30.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 26 is objected to, but would be allowable if (i) its base claim 22 is amended to include all of the limitations of claim 26 or (ii) claim 26 is rewritten in independent form to include all of the limitations of its base claim 22.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Pub. No. US 2018/0235075 A1 to Gaines et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8 A.M. to 7 P.M.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL JUNG/Primary Examiner, Art Unit 2817 01 June 2026
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