DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/17/2025 has been entered.
Election/Restrictions
Applicant elected without traverse of Group I, Species II and Modification IIA, in the reply filed on 12/03/2024.
Newly added Claim 31 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Modification IIB, as shown in Figs. 22A/22B/22C where within a same vertical plane with respect to cross-sectional view, each via is directly above or below the preceding or following via of the adjacent redistribution via layers 920.
Status of Claims
Claims 1-3, 6-7, 11-14, 21-24 and 26-32 are pending in this application. Claims 30-32 were newly added as set forth in the applicant’s response filed on 10/9/2025. Claim 31 is withdrawn as stated above.
Prior rejection of Claims 1-3, 6-7, 11-15, 21-24 and 26-29 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn in view of applicant’s amendments to claims 1, 14 and 21.
Drawings
Prior objection to drawing is withdrawn in view of cancellation of claim 15.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the first and second semiconductor dies" in line 17 of the claim. There is insufficient antecedent basis for this limitation in the claim. It is not clear what the applicant is referring to by reciting, "the first and second semiconductor dies". Thus, claim 14 is indefinite and hence rejected.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 6-7, 11, 13 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2021/0296220 A1, of record).
Re Claim 1, Hsu teaches a chip package structure (Fig. 14), comprising:
a first semiconductor die (52A, Fig. 14, para [0039]);
a second semiconductor die (52B, Fig. 14, para [0039]);
a redistribution structure comprising:
a first redistribution structure portion (region of 48 underneath 52A, Fig. 14, para [0039]) physically and electrically connected (Fig. 14) to the first semiconductor die (52A);
a second redistribution structure (region of 48 underneath 52B, Fig. 14, para [0039]) portion physically and electrically connected (Fig. 14) to the second semiconductor die (52B); and
a dummy bump region (reinforcing patches, 27+23+37+44+46, Fig. 14, para [0044]) positioned between the first redistribution structure portion (region of 48 underneath 52A) and the second redistribution structure portion (region of 48 underneath 52B), the dummy bump region comprising redistribution wiring interconnect layers (27+23+37+44) comprising parallel wiring interconnects that extend in a horizontal direction (see Fig. 14) and redistribution via layers (though only one via layer 46 is shown between interconnect layers 37 and 44, vias can be formed between all neighboring interconnect layers, 27+23+37+44, which will further improve the reinforcing ability, see para [0044]) comprising vias vertically overlapped with the wiring interconnects (vias are vertically overlapping with the interconnect layers, see Fig. 14), wherein:
each wiring interconnect (27+23+37+44) vertically overlaps with multiple other wiring interconnects (see Fig. 14) and with portions of the first semiconductor die (52A, see Fig. 14) and the second semiconductor die (52B, see Fig. 14);
the vias (46) and wiring interconnects (27+23+37+44) are electrically isolated from the first redistribution structure portion and the second redistribution structure portion (the reinforced patches can be discrete and isolated, electrically floating and fully enclosed in dielectric materials, para [0044])
a first underfill material portion (54, Fig. 14, para [0031]) located between the redistribution structure (regions of 48 underneath 52A and 52B) and the first semiconductor die (52A) and the second semiconductor die (52B).
Hsu does not disclose that the wiring interconnects (27+23+37+44) are each connected to at least five of the vias that are overlapped.
Hsu discloses that the wiring interconnects 37 and 44 have two overlapped vias (within via layer 46, see Fig. 14). Hsu also discloses more via layers (like via layer 46) can be formed between neighboring interconnect layers (27+23+37+44) to further improve the reinforcing ability (see para [0044]). Additionally, one of ordinary skill would also realize that the number of vias within each via layer depends on the design and the reinforcement requirement of the individual device, and as such, though Hsu only discloses two vias per via layer within the reinforcement structure, more vias per via-layer can be formed depending upon the design needs. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the number of vias within each via layer and arrive at the claimed value. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed number of vias within each via layer would have been obvious to one of ordinary skill in the art.
Re Claim 2, Hsu teaches the chip package structure of claim 1, wherein the dummy bump region (reinforcing patches, 27+23+37+44) comprises:
a first redistribution via layer (46, Fig. 14, para [0044]);
a first redistribution wiring interconnect layer (37, Fig. 14, para [0044]) physically and electrically connected to the first redistribution via layer (see Fig. 14);
a second redistribution via layer physically and electrically connected to the first redistribution wiring interconnect layer (37); and
a second redistribution wiring interconnect layer (23, Fig. 14, para [0044]) physically and electrically connected to the second redistribution via layer.
Hsu does not explicitly teach a second redistribution via layer. However, Hsu discloses that some neighboring reinforcing patches may be joined with (through vias) the overlying and/or underlying reinforcing patches to form a joined structure, so that the reinforcing ability is further improved (para [0044]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to have a second redistribution via layer (46-2) connecting the reinforcing patches 37 and 23 (see Fig. 14), to further improve the reinforcing ability, as disclosed by Hsu (para [0044]).
Re Claim 3, Hsu teaches the chip package structure of claim 2, but does not explicitly disclose that the vias formed in the first redistribution via layer (46) and vias formed in the second redistribution via layer (46-2) are staggered such that the vias formed in the second redistribution via layer are offset along a first horizontal direction from vias formed in the first redistribution via layer.
One of ordinary skill in the art would realize that there are only two predictable outcomes - the vias in the first redistribution layer can either directly be on the top of the vias in the second redistribution layer, or they can be staggered by having an offset in a horizontal direction. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397. Additionally, the staggered distribution of vias provide more mechanical integrity to the structure and less vulnerable to structural failures. Moreover, the examiner notes that the interconnection layer 23 (see Fig. 14) is shorter than the layer 37, and one of the 46-2 vias can’t be placed directly under one of the 46 vias (see Fig. 14), and the vias have to be staggered, thus satisfying the claimed limitation.
Re Claim 6, Hsu teaches the chip package structure of claim 2, wherein:
wiring interconnects of the first redistribution wiring interconnect layer (37) extend horizontally (see Fig. 14) to electrically connect vias of the first redistribution via layer (46),
wiring interconnects of the first redistribution wiring interconnect layer (37) are positioned parallel to each other in a striped pattern (see Fig. 16C, para [0037]),
wiring interconnects of the second redistribution wiring interconnect layer (23) extend horizontally to electrically (see Fig. 14) connect vias of the second redistribution via layer (46-2, see Claim 2, above), and
wiring interconnects of the second redistribution wiring interconnect layer (23) are positioned parallel to each other in a striped pattern (see Fig. 16C, para [0037]).
Re Claim 7, Hsu teaches the chip package structure of claim 6, wherein the wiring interconnects of the first redistribution wiring interconnect layer (37) extend parallel (see Fig. 14) to the wiring interconnects of the second redistribution wiring interconnect layer (23), and wherein wiring interconnects of the first redistribution wiring interconnect layer (37) and the second redistribution wiring interconnect layer (23) extend parallel to proximate perimeters (see Figs. 14 and 16C) of the first redistribution structure portion (region of 48 underneath 52A) and the second redistribution structure portion (region of 48 underneath 52B).
Re Claim 11, Hsu teaches the chip package structure of claim 2, wherein a density of vias within the dummy bump region is defined as a total area of vias within a horizontal plane in a plan view divided by the total area of vias and a total area of dielectric material within the horizontal plane in a plan view, and wherein the density of vias is at least 3% (see Figs. 14 and 16C, which is approximately within the claimed range).
Re Claim 13, Hsu teaches the chip package structure of claim 1, wherein portions of the dummy bump region (reinforcing patches, 27+23+37+44) are positioned in a same vertical plane (see Fig. 14) as at least one of the first semiconductor die (52A) and the second semiconductor die (52B) in a vertical cross-sectional view (see Fig. 14).
Re Claim 32, Hsu teaches the chip package of claim 1, but does not disclose that each pair of vertically overlapped wiring interconnects (27+23+37+44, Fig. 14) is vertically connected by at least nine of the vias.
Hsu discloses that there can be via layers between each interconnects (27+23+37+44, Fig. 14), with two overlapped vias in each layer (see claim 1 above). Thus, Hsu teaches that for each pair of vertically overlapped wiring interconnects, there will be four vias vertically connected. However, as stated above in claim 1, one of ordinary skill would also realize that the number of vias within each via layer depends on the design and the reinforcement requirement of the individual device, and as such, though Hsu only discloses four vias vertically connected to each pair of interconnects, more vias per via-layer can be formed depending upon the design needs. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the number of vias within each via layer and arrive at the claimed number of vias vertically connected to each pair of interconnects. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed number of vias vertically connected to each pair of interconnects would have been obvious to one of ordinary skill in the art.
Claims 12, 21-24 and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2021/0296220 A1, of record) and further in view of Hatano et al. (US 2006/0226527 A1, of record).
Re Claim 12, Hsu teaches the chip package structure of claim 2, further comprising a bridge (66, Fig. 14, para [0036]) that electrically connects the first semiconductor die (52A) to the second semiconductor die (52B) through the first redistribution structure portion (region of 48 underneath 52A) and the second redistribution structure portion (region of 48 underneath 52B), wherein the first redistribution via layer (46, Fig. 14) is connected to the bridge (46 is connected to the bridge component 66, via the redistribution structure 48).
Hsu also does not disclose that the bridge (package component 66, Fig. 14) is made of silicon.
Related art Hatano discloses a silicon substrate (3, Fig. 2, para [0051]) with a chip-to-chip interconnection (4, Fig. 2, para [0051]) that connects the semiconductor chips 2a and 2b, which enhances signal transmission between the semiconductor chips (para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the package component of Hsu from silicon substrate as disclosed by Hatano, which will connect the semiconductor chips and enhance signal transmission between them (para [0023], Hatano).
Re Claim 21, Hsu teaches a chip package structure, comprising:
a first semiconductor die (52A, Fig. 14, para [0039]);
a second semiconductor die (52B, Fig. 14, para [0039]);
a redistribution structure comprising:
a first redistribution structure portion (region of 48 underneath 52A, Fig. 14, para [0039]) physically and electrically connected (Fig. 14) to the first semiconductor die (52A);
a second redistribution structure (region of 48 underneath 52B, Fig. 14, para [0039]) portion physically and electrically connected (Fig. 14) to the second semiconductor die (52B);
a dummy bump region (reinforcing patches, 27+23+37+44+46, Fig. 14, para [0044]) positioned between the first redistribution structure portion (region of 48 underneath 52A) and the second redistribution structure portion (region of 48 underneath 52B), the dummy bump region comprising:
redistribution wiring interconnect layers (27+23+37+44) comprising parallel wiring interconnects that extend in a horizontal direction (see Fig. 14); and
redistribution via layers (though only one via layer 46 is shown between interconnect layers 37 and 44, vias can be formed between all neighboring interconnect layers, 27+23+37+44, which will further improve the reinforcing ability, see para [0044]) comprising vias vertically overlapped with the wiring interconnects (vias are vertically overlapping with the interconnect layers, see Fig. 14); and
a bridge (66, Fig. 14, para [0036]) extending between the first semiconductor die (52A) and the second semiconductor die (52B) and electrically connected (see Fig. 14) to the first redistribution structure portion (region of 48 underneath 52A) and the second redistribution structure portion (region of 48 underneath 52B), wherein:
each wiring interconnect (27+23+37+44) vertically overlaps with multiple other wiring interconnects (see Fig. 14) and with portions of the first and second semiconductor dies (52A and 52B, see Fig. 14);
the vias (46) and wiring interconnects (27+23+37+44) are electrically isolated from the first redistribution structure portion and the second redistribution structure portion (the reinforced patches can be discrete and isolated, electrically floating and fully enclosed in dielectric materials, para [0044]).
Hsu does not disclose that the wiring interconnects (27+23+37+44) are each connected to at least five of the vias that are overlapped.
Hsu discloses that the wiring interconnects 37 and 44 have two overlapped vias (within via layer 46, see Fig. 14). Hsu also discloses more via layers (like via layer 46) can be formed between neighboring interconnect layers (27+23+37+44) to further improve the reinforcing ability (see para [0044]). Additionally, one of ordinary skill would also realize that the number of vias within each via layer depends on the design and the reinforcement requirement of the individual device, and as such, though Hsu only discloses two vias per via layer within the reinforcement structure, more vias per via-layer can be formed depending upon the design needs. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the number of vias within each via layer and arrive at the claimed value. With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). The optimization of the claimed number of vias within each via layer would have been obvious to one of ordinary skill in the art.
Hsu also does not disclose that the bridge (package component 66, Fig. 14) is made of silicon.
Related art Hatano discloses a silicon substrate (3, Fig. 2, para [0051]) with a chip-to-chip interconnection (4, Fig. 2, para [0051]) that connects the semiconductor chips 2a and 2b, which enhances signal transmission between the semiconductor chips (para [0023]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to make the package component of Hsu from silicon substrate as disclosed by Hatano, which will connect the semiconductor chips and enhance signal transmission between them (para [0023], Hatano).
Re Claim 22, Hsu modified by Hatano teaches the chip package structure of claim 21, comprising a first underfill material portion (54, Fig. 14, para [0031], Hsu) located between the redistribution structure (regions of 48 underneath 52A and 52B) and the first semiconductor die (52A) and the second semiconductor die (52B), wherein portions of the dummy bump region (reinforcing patches, 27+23+37+44+46, Fig. 14, Hsu) are positioned within a vertical plane shared with at least one of the first semiconductor die (52A) and the second semiconductor die (52B) in a vertical cross-sectional view (see Fig. 14).
Re Claim 23, Hsu modified by Hatano teaches the chip package structure of claim 21, wherein the dummy bump region comprises:
a first redistribution via layer (46, Fig. 14, para [0044], Hsu);
a first redistribution wiring interconnect layer (37, Fig. 14, para [0044], Hsu) physically and electrically connected to the first redistribution via layer (see Fig. 14, Hsu);
a second redistribution via layer physically and electrically connected to the first redistribution wiring interconnect layer (37, Hsu); and
a second redistribution wiring interconnect layer (23, Fig. 14, para [0044], Hsu) physically and electrically connected to the second redistribution via layer.
Hsu does not explicitly teach a second redistribution via layer. However, Hsu discloses that some neighboring reinforcing patches may be joined with (through vias) the overlying and/or underlying reinforcing patches to form a joined structure, so that the reinforcing ability is further improved (para [0044]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to have a second redistribution via layer (46-2) connecting the reinforcing patches 37 and 23 (see Fig. 14), to further improve the reinforcing ability, as disclosed by Hsu (para [0044]).
Re Claim 24, Hsu modified by Hatano teaches the chip package structure of claim 23, but Hsu does not explicitly disclose that the vias formed in the first redistribution via layer (46) and vias formed in the second redistribution via layer (46-2) are staggered such that the vias formed in the second redistribution via layer are offset along a first horizontal direction from vias formed in the first redistribution via layer.
One of ordinary skill in the art would realize that there are only two predictable outcomes - the vias in the first redistribution layer can either directly be on the top of the vias in the second redistribution layer, or they can be staggered by having an offset in a horizontal direction. Therefore, a person of ordinary skill has good reason to pursue the known options and reach the claimed limitation with anticipated success, see KSR, 550 U.S. at 421, 82 USPQ2d at 1397. Additionally, the staggered distribution of vias provide more mechanical integrity to the structure and less vulnerable to structural failures. Moreover, the examiner notes that the interconnection layer 23 (see Fig. 14, Hsu) is shorter than the layer 37, and one of the 46-2 vias can’t be placed directly under one of the 46 vias (see Fig. 14, Hsu), and the vias have to be staggered, thus satisfying the claimed limitation.
Re Claim 26, Hsu modified by Hatano teaches the chip package structure of claim 23, wherein:
wiring interconnects of the first redistribution wiring interconnect layer (37, Fig. 14, Hsu) extend horizontally (see Fig. 14) to electrically connect vias of the first redistribution via layer (46),
wiring interconnects of the first redistribution wiring interconnect layer (37, Hsu) are positioned parallel to each other in a striped pattern (see Fig. 16C, para [0037]),
wiring interconnects of the second redistribution wiring interconnect layer (23, Hsu) extend horizontally to electrically (see Fig. 14, Hsu) connect vias of the second redistribution via layer (46-2, see Claim 2, above), and
wiring interconnects of the second redistribution wiring interconnect layer (23) are positioned parallel to each other in a striped pattern (see Fig. 16C, para [0037], Hsu).
Re Claim 27, Hsu modified by Hatano teaches the chip package structure of claim 26, wherein Hsu teaches the wiring interconnects of the first redistribution wiring interconnect layer (37) extend parallel (see Fig. 14) to the wiring interconnects of the second redistribution wiring interconnect layer (23), and wherein wiring interconnects of the first redistribution wiring interconnect layer (37) and the second redistribution wiring interconnect layer (23) extend parallel to proximate perimeters (see Figs. 14 and 16C) of the first redistribution structure portion (region of 48 underneath 52A) and the second redistribution structure portion (region of 48 underneath 52B).
Re Claim 28, Hsu modified by Hatano teaches the chip package structure of claim 23, wherein Hsu teaches a density of vias within the dummy bump region is defined as a total area of vias within a horizontal plane in a plan view divided by the total area of vias and a total area of dielectric material within the horizontal plane in a plan view, and wherein the density of vias is at least 3% (see Figs. 14 and 16C of Hsu, which is approximately within the claimed range).
Re Claim 29, Hsu modified by Hatano teaches the chip package structure of claim 21, wherein Hsu teaches that portions of the dummy bump region (reinforcing patches, 27+23+37+44) are positioned in a same vertical plane (see Fig. 14) as at least one of the first semiconductor die (52A) and the second semiconductor die (52B) in a vertical cross-sectional view (see Fig. 14).
Allowable Subject Matter
Claim 30 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 30 is allowable for at least the reasons of, “wherein the wiring interconnects and the via are arranged in columns that are electrically isolated from one another.” Prior art, Hsu et al. (US 2021/0296220 A1, of record) teaches that the wiring interconnects and the via are arranged in columns (compare Figs. 14 and 16C of Hsu), but does not teach that the columns are electrically isolated from one another. The prior art of record taken either single or in combination fails to teach or reasonably suggest the above limitation when taken in context of the independent claim 1, as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1, 14 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claim 1, applicant argued that Hsu does not teach that “the vias and wiring interconnects are electrically isolated from the first redistribution structure portion”. The examiner respectfully disagrees. In para [0044] of Hsu, it is clearly disclosed that the reinforced patches (27+23+37+44+46, Fig. 14, para [0044]) can be discrete and isolated, electrically floating and fully enclosed in dielectric materials.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PINAKI DAS whose telephone number is (703)756-5641. The examiner can normally be reached M-F 8-5 EST.
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898