DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/19/2025 has been entered.
Response to Amendment
The amendment with respect to claims 16-17, 20-21, 25, 30, and 34 filed on 12/04/2025 have been fully considered for examination based on their merits. The previously presented claims 18-19, 22-24, 26-29, 31-32, and 35 have been considered. Claims 1-15, and 33 are canceled. New claim 36 has been considered for examination.
Response to Arguments
Applicant’s arguments, see (Remarks, pages 8-13), filed 12/04/2025, with respect to the rejection(s) of claim(s) 16-35 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of CHANG.
Regarding Independent Claim 16. The Applicant argues (see Remarks, page 9) that PARK fails to disclose or suggest the amended limitations now recites, “the metal-insulator-metal capacitor comprising: a bottom plate…wherein a portion of the second insulator layer extends on a portion of the first insulator layer; forming a second dielectric layer…wherein there is an interface between the second dielectric layer…and the bottom plate”. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art CHANG (US10290701B1) teaches a method (Fig. 1, 10, flow chart representing a method for manufacturing a MIM capacitor), comprising: providing a workpiece (Fig. 14, 30, MIM capacitor) comprising: forming a metal-insulator-metal capacitor (Fig. 14, 30) over the etch stop layer (Fig. 14, 308, protection layer), the metal-insulator- metal capacitor (Fig. 14, 30) comprising: a bottom plate (Fig. 14, 312, bottom electrode) over the etch stop layer (Fig. 14, 308, protection layer; (CHANG, [Col. 5, Lines 30-40]; CHANG, [Col. 3, Lines 30-35]), a first insulator layer (Fig. 14, 320, first dielectric layer) over the bottom plate (Fig. 14, 312, bottom electrode), a middle plate (Fig. 14, 332, middle electrode) over the first insulator layer (Fig. 14, 320, first dielectric layer), a second insulator layer (Fig. 14, 340, second dielectric layer) over the middle plate (Fig. 14, 332, middle electrode), and a top plate (Fig. 14, 352, top electrode) over the second insulator layer (Fig. 14, 340, second dielectric layer), wherein a portion (annotated Figure 14) of the second insulator layer (Fig. 14, 340, second dielectric layer) extends on a portion (annotated Figure 14) of the first insulator layer (Fig. 14, 320, first dielectric layer); forming a second dielectric layer (Fig. 14, 370, insulating layer) over the metal-insulator-metal capacitor (Fig. 14, 30), wherein there is an interface between (annotated Figure 14) the second dielectric layer (Fig. 14, 370, insulating layer) and sidewalls of the portion (annotated Figure 14) of the first insulator layer (Fig. 14, 332, bottom electrode), the portion (annotated Figure 14) of the second insulator layer (Fig. 14, 352, second dielectric layer), and the bottom plate (Fig. 14, 312, bottom electrode).
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Regarding Independent Claim 21. The Applicant argues (see Remarks, page 11) that PARK fails to disclose the amended claim limitations now recites, “after the forming of the bottom conductor plate, the middle conductor plate, and the top conductor plate, performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third lower contact feature; and after the performing of the etching process, forming a second dielectric layer over the etch stop layer and the top conductor plate.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of the previously adopted prior art ZHANG. For instance, the prior-art ZHANG (US 20190013269 A1) teaches a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]) comprising: after the forming of the bottom conductor plate (Fig. 1, 22), the middle conductor plate (Fig. 1, 26), and the top conductor plate (Fig. 1, 30), performing an etching process ([0015]) to remove portions of the first insulation layer (Fig. 2, 24) and the second insulation layer Fig. 2, 28) extended over the third lower contact feature (Fig. 2, 14, conductive wiring feature); and after the performing of the etching process ([0015]), forming a second dielectric layer (Fig. 3, 36) over the etch stop layer (Fig. 3, 18, capping layer) and the top conductor plate (Fig. 1, 30).
Regarding Independent Claim 30. The Applicant argues (see Remarks, page 12) that PARK fails to disclose or suggest the amended limitations now recites, “forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator- metal capacitor comprising a bottom conductor plate, a first insulation layer over the bottom conductor plate and laterally adjacent to the bottom conductor plate, a middle conductor plate over the first insulation layer, a second insulation layer over the middle conductor plate, and a top conductor plate over the second insulation layer; after the forming of the metal-insulator-metal capacitor, removing a portion of the first insulation layer, thereby exposing a sidewall surface of the bottom conductor plate.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned above. For instance, the prior-art CHANG (US10290701B1) teaches a method (Fig. 1, 10, flow chart representing a method for manufacturing a MIM capacitor), comprising: forming a metal-insulator-metal capacitor (Fig. 14, 30) over the etch stop layer (Fig. 14, 308, protection layer), the metal-insulator- metal capacitor (Fig. 14, 30) comprising a bottom conductor plate (Fig. 14, 312, bottom electrode), a first insulator layer (Fig. 14, 320, first dielectric layer) over the bottom conductor plate (Fig. 14, 312, bottom electrode) and laterally adjacent (annotated Figure 14) to the bottom conductor plate (Fig. 14, 312, bottom electrode), a middle conductor plate (Fig. 14, 332, middle electrode), over the first insulation layer (Fig. 14, 320, first dielectric layer), a second insulation layer (Fig. 14, 340, second dielectric layer) over the middle conductor plate (Fig. 14, 332, middle electrode), and a top conductor plate (Fig. 14, 352, top electrode) over the second insulation layer (Fig. 14, 340, second dielectric layer). The prior-art ZHANG (US 20190013269 A1) teaches a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]) comprising: after the forming of the metal-insulator-metal capacitor (Fig. 1, 22, 24, 26, 28, 30, MIM capacitor stack, [0011]), removing a portion (Fig. 5, 56, cavities) of the first insulation layer (Figs. 2/5, 24), thereby exposing a sidewall surface (annotated Figure 5) of the bottom conductor plate (Fig. 5, 22).
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Regarding Dependent Claims 17-20, 22-29, 31-32, and 34-46: The dependent claims 2, 17-20, 22-29, 31-32, and 34-46 follow similar arguments as Claim 16, 21, and 30, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yao-Wen Chang, (hereinafter CHANG), US 10290701 B1.
Regarding Claim 16, CHANG teaches a method (Fig. 1, 10, flow chart representing a method for manufacturing a MIM capacitor), comprising:
providing a workpiece (Fig. 14, 30, MIM capacitor) comprising:
a first dielectric layer (Fig. 14, 306, barrier layer; [Col. 10, Lines 5-15]); and
a first lower contact feature (Fig. 14, 304, conductive layer), a second lower contact feature (Fig. 14, 304, conductive layer), and a third lower contact feature (Fig. 14, 304, conductive layer) in the first dielectric layer (Fig. 14, 306, barrier layer; [Col. 10, Lines 5-15]);
depositing an etch stop layer (Fig. 14, 308, protection layer; ([CHANG, Col. 5, Lines 30-40]; CHANG, [Col. 3, Lines 30-35]) on the first dielectric layer (Fig. 14, 306, barrier layer);
forming a metal-insulator-metal capacitor (Fig. 14, 30) over the etch stop layer (Fig. 14, 308, protection layer), the metal-insulator- metal capacitor (Fig. 14, 30) comprising: a bottom plate (Fig. 14, 312, bottom electrode) over the etch stop layer (Fig. 14, 308, protection layer; (CHANG, [Col. 5, Lines 30-40]; CHANG, [Col. 3, Lines 30-35]), a first insulator layer (Fig. 14, 320, first dielectric layer) over the bottom plate (Fig. 14, 312, bottom electrode), a middle plate (Fig. 14, 332, middle electrode) over the first insulator layer (Fig. 14, 320, first dielectric layer), a second insulator layer (Fig. 14, 340, second dielectric layer) over the middle plate (Fig. 14, 332, middle electrode), and a top plate (Fig. 14, 352, top electrode) over the second insulator layer (Fig. 14, 340, second dielectric layer), wherein a portion (annotated Figure 14) of the second insulator layer (Fig. 14, 340, second dielectric layer) extends on a portion (annotated Figure 14) of the first insulator layer (Fig. 14, 320, first dielectric layer);
forming a second dielectric layer (Fig. 14, 370, insulating layer) over the metal-insulator-metal capacitor (Fig. 14, 30), wherein there is an interface between (annotated Figure 14) the second dielectric layer (Fig. 14, 370, insulating layer) and sidewalls of the portion (annotated Figure 14) of the first insulator layer (Fig. 14, 332, bottom electrode), the portion (annotated Figure 14) of the second insulator layer (Fig. 14, 352, second dielectric layer), and the bottom plate (Fig. 14, 312, bottom electrode);
forming a first contact via (Fig. 14, 394, opening) penetrating multiple layers (annotated Figure 14) of the metal-insulator-metal capacitor (Fig. 14, 30) to electrically couple ([Col. 9, Lines 35-45]) to the first lower contact feature (Fig. 14, 304, conductive layer); and
forming a second contact via (Fig. 14, 394, opening) penetrating multiple layers (annotated Figure 14) of the metal-insulator-metal capacitor (Fig. 14, 30) to electrically couple ([Col. 9, Lines 35-45]) to the second lower contact feature (Fig. 14, 304, conductive layer).
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Although the primary reference, CHANG does not expressly refer to the barrier layer, 306 as a first dielectric layer, a barrier layer functions inherently as a dielectric (or insulation) layer because it functions to prevent metal diffusion (See CHANG, [Col. 10, Lines 5-15]); therefore, it meets the claim limitation of a first dielectric layer.
Although the primary reference, CHANG does not expressly refer to the protection layer, 308 as an etch stop layer, a protection layer that includes a polymeric material ([CHANG, Col. 5, Lines 30-40]) may accumulate or be trapped in the rough surface of the dielectric layer, thus supports the patterning or etching the metal electrodes (CHANG, [Col. 3, Lines 30-35]) to intentionally serve as an etch stop layer; therefore, it meets the claim limitation of an etch stop layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 16-20, 30-32, and 34-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jinho Park et al, (hereinafter PARK), US 20200350248 A1, in view of Seokjun Won et al, (hereinafter WON), KR 100569720 B1, further in view of Chih-Fan Huang et al, (hereinafter HUANG), US 20190131385 A1, further in view of Chen-Hsiang Hung et al, (hereinafter HUNG), US 20190148370 A1, further in view of CHANG, and further in view of Xunyuan Zhang et al, (hereinafter ZHANG), US 20190013269 A1.
Regarding Claim 16, PARK teaches in Figure 7G, a method ([0046]), comprising:
providing a workpiece comprising (Fig. 1, 100, substrate):
a first dielectric layer (111, interlayer insulation layer); and
a first lower contact feature (113, lower wiring layer), a second lower contact feature (115, lower wiring layer), and a third lower contact feature (117, lower wiring layer) in the first dielectric layer (111, interlayer insulation layer);
depositing an etch stop layer (121, buffer insulation layer) on the first dielectric layer (111, interlayer insulation layer);
forming a metal-insulator-metal capacitor (annotated Figure 7G) over the etch stop layer (121, buffer insulation layer), the metal-insulator- metal capacitor (annotated Figure 7G) comprising: a bottom plate (201, first electrode, [0024]) over the etch stop layer (121, buffer insulation layer), a first insulator layer (203, first dielectric layer) over the bottom plate (201, first electrode, [0024]);
forming a second dielectric layer (211, interlayer insulation layer) over the metal-insulator-metal capacitor (annotated Figure 7G);
forming a first contact via (Fig. 6. 221, upper wiring layer) penetrating multiple layers (annotated Figure 7G) of the metal-insulator-metal capacitor (annotated Figure 7G) to electrically couple ([0037-0038]) to the first lower contact feature (113, lower wiring layer); and
forming a second contact via (Fig. 6. 223, upper wiring layer) penetrating multiple layers (annotated Figure 7G) of the metal-insulator-metal capacitor (annotated Figure 7G) to electrically couple ([0037-0038]) to the second lower contact feature (115, lower wiring layer).
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Although the primary reference, PARK does not expressly refer to the buffer insulation layer, 121 as an etch stop layer, a buffer layer functions inherently as an etch stop layer because it functions to buffer or protect the underneath contact features, during an etch process; therefore, it meets the claim limitation of an etch stop layer.
WON teaches in paragraph [0050] that the first buffer layer, 120 is provided as an etch stop layer during a subsequent etching process.
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified PARK to incorporate the teachings of WON such that the buffer layer, 120 is provided as an etch stop layer, so that it serves as a reinforcing film for suppressing cracks of a dielectric film (WON, Fig. 9, [0050]).
Though PARK and WON refers the buffer insulation layer in place of etch stop layer, but does not explicitly disclose a method comprising: depositing an etch stop layer on the first dielectric layer; forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator- metal capacitor comprising a bottom plate on the etch stop layer.
HUANG teaches a method comprising: depositing an etch stop layer (Fig. 2H, 216) on the first dielectric layer (Fig. 2H, 210); forming a metal-insulator-metal capacitor (Fig. 2H, 500B) over the etch stop layer (Fig. 2H, 216), the metal-insulator- metal capacitor (Fig. 2H, 500B) comprising a bottom plate (Fig. 1A, 220, bottom electrode layer) on the etch stop layer (Fig. 2H, 216).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON to incorporate the teachings of HUANG such that a method comprising: depositing an etch stop layer on the first dielectric layer so that the etch stop layer, 216 serve as via portions of the RDL structures, 250A, 250B and 250C (HUANG, Fig. 2H, [0035]).
Though PARK as modified by WON, and HUANG teaches a method comprising: forming a metal-insulator-metal capacitor over the etch stop layer (or buffer layer), the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer (or buffer layer) with either interlayer insulation layer or dielectric layer in between the MIM capacitor and the etch stop layer, PARK as modified by WON, and HUANG does not disclose a method comprising: forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer (i.e. MIM capacitor layer directly on the etch stop layer as exhibited by the Figure 10 of the instant application).
HUNG teaches in Figure 2D, a method (Fig. 1, 100, flow chart of an exemplary method for forming a semiconductor device, [0006]) comprising: forming a metal-insulator-metal capacitor (Fig. 2C, 200-1, MIM capacitor, [0022]; Fig. 2D, 236-238-224; bottom metal plate-capacitor dielectric layer-top metal plate [0022-0023]) over the etch stop layer (Fig. 2D, 206), the metal-insulator-metal capacitor comprising a bottom plate (Fig. 2D, 236, bottom metal plate) over etch stop layer (Fig. 2D, 236, bottom metal plate over 206, etch stop layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON, and HUANG to incorporate the teachings of HUNG such that a method, comprising: forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer, so that the first metal layer (208) is disposed over the first etch stop layer (206); the dummy capacitor dielectric layer (210) is disposed over the first metal layer (208); the second metal layer (212) is disposed over the dummy capacitor dielectric layer (210) to form a MIM capacitor (200-1) of a semiconductor device that can be used in various radio frequency (RF) circuits, in dynamic random-access memory cells and high-power microprocessor units (HUNG, Fig. 2C, [0002], [0017]).
PARK as modified by WON, HUANG, and HUNG does not explicitly disclose a method comprising: a middle plate over the first insulator layer, a second insulator layer over the middle plate, and a top plate over the second insulator layer, wherein a portion of the second insulator layer extends on a portion of the first insulator layer; wherein there is an interface between the second dielectric layer and sidewalls of the portion of the first insulator layer, the portion of the second insulator layer, and the bottom plate.
CHANG teaches disclose a method (Fig. 1, 10, flow chart representing a method for manufacturing a MIM capacitor) comprising: a middle plate (Fig. 14, 332, middle electrode) over the first insulator layer (Fig. 14, 320, first dielectric layer), a second insulator layer (Fig. 14, 340, second dielectric layer) over the middle plate (Fig. 14, 332, middle electrode), and a top plate (Fig. 14, 352, top electrode) over the second insulator layer (Fig. 14, 340, second dielectric layer), wherein a portion (annotated Figure 14) of the second insulator layer (Fig. 14, 340, second dielectric layer) extends on a portion (annotated Figure 14) of the first insulator layer (Fig. 14, 320, first dielectric layer);
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON, HUANG, and HUNG to incorporate the teachings of CHANG such that a method, comprising: a middle plate over the first insulator layer, a second insulator layer over the middle plate, and a top plate over the second insulator layer, The above arrangement of the MIM capacitors can be used as decoupling capacitors configured to mitigate power supply or switching noise caused by changes in the current, thus to prevent breakdown and improve the MIM capacitor performance (CHANG, [Col. 2, Lines 55-60]; [Col. 3, Lines 35-40]).
PARK as modified by WON, HUANG, HUNG and CHANG does not explicitly disclose a method comprising: wherein a portion of the second insulator layer extends on a portion of the first insulator layer; wherein there is an interface between the second dielectric layer and sidewalls of the portion of the first insulator layer, the portion of the second insulator layer, and the bottom plate.
ZHANG teaches in Figures 2-4, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), wherein there is an interface (annotated Figure 4) between the second dielectric layer (Fig. 4, 36, [0018]) and sidewalls (Figs. 2-4, 31, sidewall, [0017]) of the portion (annotated Figure 4) of the first insulator layer (Fig. 4, 24, dielectric layer), the portion (annotated Figure 4) of the second insulator layer (Fig. 4, 28, dielectric layer), and the bottom plate (Fig. 4, 22, layer comprised conductive materials).
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Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON, HUANG, HUNG and CHANG to incorporate the teachings of ZHANG such that a method comprising: wherein a portion of the second insulator layer extends on a portion of the first insulator layer; wherein there is an interface between the second dielectric layer and sidewalls of the portion of the first insulator layer, the portion of the second insulator layer, and the bottom plate, so that the same sidewall (31) as an outer perimeter or boundary with the area equal to the product of the common length (L) and the common width (W) and further overlap within the dielectric layer (36) and used to pattern the trenches (38, 40, and 42), and therefore, the electrodes and capacitor dielectrics have the same area and the same footprint projected on to top surface of the dielectric layer (20) (ZHANG, [0017-0018]).
Regarding Claim 17, PARK as modified by WON, HUANG, HUNG, CHANG, and ZHANG teaches a method of claim 16.
PARK further teaches in Figures 7A-7G, a method ([0046]), wherein the forming of the metal-insulator-metal capacitor (annotated Figure 7E) comprises:
depositing a first conductive layer (Fig. 7A, EL1, first electrode layer, [0024]) on the etch stop layer (121, buffer insulation layer);
patterning (Fig. 7B, MP1, first mask pattern, [0049]) the first conductive layer (Fig. 7A, EL1, first electrode layer, [0024]) to form a conductive feature (Fig. 7B, 201, first electrode, [0024], [0049]) over the first lower contact feature (113, lower wiring layer) and the bottom plate (201, first electrode, [0024]) over the second lower contact feature (115, lower wiring layer)
depositing the first insulator layer (Fig. 7C, 203, first dielectric layer) over the workpiece (Fig. 1, 100, substrate);
forming the middle plate (Fig. 7E, EL2/205, second electrode layer, [0026]) over the first insulator layer (203, first dielectric layer), the middle plate (205, second electrode, [0026]) being vertically overlapped (annotated Figure 7E) with the first lower contact feature (113, lower wiring layer);
depositing the second insulator layer (Fig. 7E, 207, second dielectric layer) over the workpiece (Fig. 1, 100, substrate); and
forming the top plate (Fig. 7E, EL3/209, third electrode layer, [0028]) over the second insulator layer (Fig. 7E, 207, second dielectric layer), the top plate (209, third electrode, [0028]) being vertically overlapped (annotated Fig. 7E, [0028]) with the second lower contact feature (115, lower wiring layer).
WON further teaches a buffer insulation layer, 120 is provided as an etch stop layer.
HUANG further teaches depositing a first conductive layer (Fig. 1A, 220, bottom electrode layer, [0018]) on the etch stop layer (Fig. 2H, 216).
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Regarding Claim 18, PARK as modified by WON, HUANG, HUNG, CHANG, and ZHANG teaches a method of claim 17.
HUANG further teaches that the forming of a dielectric layer over the etch stop layer (Fig. 2H, 216), the via openings exposing the etch stop layer (Fig. 2H, 216) and removing the portions of the etch stop layer (Fig. 2H, 216) to expose the contact features (Fig. 2H, 214, metal material).
ZHANG further teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), wherein the forming of the first contact via (Fig. 7, 62/68, conductive wiring features/conductive vias [0026]) and the second contact via (Fig. 7, 62/66, conductive wiring features/conductive vias [0026]) comprises:
performing a first etching process (patterned with lithography and etching processes, [0018-0022]) to form a first via opening (Fig. 6, 54, via opening, [0018-0022]) extending through both the middle plate (Fig. 6, 26, patterned layer, [0016]) and the conductive feature (Fig. 2, 32, patterned layers, [0020]) and stop on the etch stop layer (annotated Figure 6; not shown the trench only up to the top layer of capping layer 18, but it is obvious to etch up to the top surface and the Figure 4 shows penetration of the caping layer further), and a second via opening (Fig. 6, 48, via opening, [0018-0022]) extending through both the top plate (Fig. 6, 30, patterned layer, [0016]) and the bottom plate (Fig. 6, 22, patterned layer, [0016]) and stop on the etch stop layer (annotated Figure 6; not shown the trench only up to the top layer of capping layer 18, but it is obvious to etch up to the top surface and the Figure 4 shows penetration of the caping layer further);
performing a second etching process (patterned with lithography and etching processes, [0018-0022]) to extend the first via opening (Fig. 6, 54, via opening, [0018-0022]) and the second via opening (Fig. 6, 48, via opening, [0018-0022]), thereby exposing the first lower contact feature and the second lower contact feature (Fig. 6, 14, conductive wiring features; annotated Figure 6);
forming the first contact via (Fig. 7, 62/68, conductive wiring features/conductive vias [0026]) in the extended first via opening (Fig. 6, 54, via opening, [0018-0022]); and
forming the second contact via (Fig. 7, 62/66, conductive wiring features/conductive vias [0026]) in the extended second via opening (Fig. 6, 48, via opening, [0018-0022]).
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Regarding Claim 19, PARK as modified by WON, HUANG, HUNG, CHANG, and ZHANG teaches a method of claim 18.
HUANG further teaches in Figure 2D, a method (Fig. 1, 100, flow chart of an exemplary method for forming a semiconductor device, [0006]) of claim 18, wherein the workpiece (Fig. Fig. 2H, 500B, MIM capacitor structure) further comprises a third lower contact feature (Fig. 2H, 214, metal material, [0015]) formed in the first dielectric layer (Fig. 2H, 210, dielectric layer, [0012]).
ZHANG further teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), wherein the workpiece (Fig. 1, BEOL Interconnect structure, [0010]) further comprises a third lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 7) formed in the first dielectric layer (Fig. 1, 20, dielectric layer, [0010]) and spaced apart from the second lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 7) along a first direction (annotated Figure 7), wherein the top plate (Fig. 2, 30, patterned layer, [0011]) is not vertically overlapped (annotated Figure 7) with the third lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 7).
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Regarding Claim 20, HUANG further teaches in Figure 2D, a method (Fig. 1, 100, flow chart of an exemplary method for forming a semiconductor device, [0006]) of claim 18, wherein the workpiece (Fig. Fig. 2H, 500B, MIM capacitor structure) further comprises a third lower contact feature (Fig. 2H, 214, metal material, [0015]) formed in the first dielectric layer (Fig. 2H, 210, dielectric layer, [0012]).
PARK further teaches in Figures 7A-7G, a method ([0046]) of claim 19, further comprising: forming a third contact via (Fig. 6, 225, upper wiring layer) penetrating the second dielectric layer (211, interlayer insulation layer) to contact the third lower contact feature (117, lower wiring layer).
ZHANG further teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), after the forming of the metal-insulator-metal capacitor (Fig. 1, 22, 24, 26, 28, 30, MIM capacitor stack, [0011]) and before the forming of the second dielectric layer (Fig. 2, no formation of 36, dielectric layer), performing an etching process ([0015]) to remove portions of the second insulator layer (Fig. 2, 28) and the first insulator layer Fig. 2, 24) over the third lower contact feature (Fig. 2, 14, conductive wiring feature).
Regarding Claim 30, PARK teaches in Figure 7G, a method ([0046]), comprising:
forming a first lower contact feature (113, lower wiring layer), a second lower contact feature (115, lower wiring layer), and a third lower contact feature (117, lower wiring layer) in a first dielectric layer (111, interlayer insulation layer),
depositing an etch stop (121, buffer insulation layer) over the first dielectric layer (111, interlayer insulation layer);
forming a second dielectric layer (211, interlayer insulation layer) over the metal-insulator-metal capacitor (annotated Figure 7G);
forming a first contact via (Fig. 6. 221, upper wiring layer) in the vertically extended first opening (TH1, through hole) to contact the first lower contact feature (113, lower wiring layer);
forming a second contact via (Fig. 6, 223, upper wiring layer) in the vertically extended second opening (TH2, through hole) to contact the second lower contact feature (115, lower wiring layer).
Although the primary reference, PARK does not expressly refer to the buffer insulation layer, 121 as an etch stop layer, a buffer layer functions inherently as an etch stop layer because it functions to buffer or protect the underneath contact features, during an etch process; therefore, it meets the claim limitation of an etch stop layer.
WON teaches in paragraph [0050] that the first buffer layer, 120 is provided as an etch stop layer during a subsequent etching process.
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified PARK to incorporate the teachings of WON such that the buffer layer, 120 is provided as an etch stop layer, so that it serves as a reinforcing film for suppressing cracks of a dielectric film (WON, Fig. 9, [0050]).
Though PARK and WON refers the buffer insulation layer in place of etch stop layer, but does not explicitly disclose a method comprising: depositing an etch stop layer on the first dielectric layer.
HUANG teaches a method comprising: depositing an etch stop layer (Fig. 2H, 216) on the first dielectric layer (Fig. 2H, 210).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON to incorporate the teachings of HUANG such that a method comprising: depositing an etch stop layer on the first dielectric layer so that the etch stop layer, 216 serve as via portions of the RDL structures, 250A, 250B and 250C (HUANG, Fig. 2H, [0035]).
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Though PARK as modified by WON, and HUANG teaches a method comprising: forming a metal-insulator-metal capacitor over the etch stop layer (or buffer layer), the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer (or buffer layer) with either interlayer insulation layer or dielectric layer in between the MIM capacitor and the etch stop layer, PARK as modified by WON, and HUANG does not disclose a method comprising: forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer (i.e. MIM capacitor layer directly on the etch stop layer as exhibited by the Figure 10 of the instant application).
HUNG teaches in Figure 2D, a method (Fig. 1, 100, flow chart of an exemplary method for forming a semiconductor device, [0006]) comprising: forming a metal-insulator-metal capacitor (Fig. 2C, 200-1, MIM capacitor, [0022]; Fig. 2D, 236-238-224; bottom metal plate-capacitor dielectric layer-top metal plate [0022-0023]) over the etch stop layer (Fig. 2D, 206), the metal-insulator-metal capacitor comprising a bottom plate (Fig. 2D, 236, bottom metal plate) over etch stop layer (Fig. 2D, 236, bottom metal plate over 206, etch stop layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON, and HUANG to incorporate the teachings of HUNG such that a method, comprising: forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer, so that the first metal layer (208) is disposed over the first etch stop layer (206); the dummy capacitor dielectric layer (210) is disposed over the first metal layer (208); the second metal layer (212) is disposed over the dummy capacitor dielectric layer (210) to form a MIM capacitor (200-1) of a semiconductor device that can be used in various radio frequency (RF) circuits, in dynamic random-access memory cells and high-power microprocessor units (HUNG, Fig. 2C, [0002], [0017]).
PARK as modified by WON, HUANG and HUNG does not explicitly disclose a method comprising: forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator- metal capacitor comprising a bottom conductor plate, a first insulator layer over the bottom conductor plate and laterally adjacent to the bottom conductor plate, a middle conductor plate, over the first insulation layer, a second insulation layer over the middle conductor plate, and a top conductor plate over the second insulation layer.
CHANG teaches a method (Fig. 1, 10, flow chart representing a method for manufacturing a MIM capacitor), comprising:
forming a metal-insulator-metal capacitor (Fig. 14, 30) over the etch stop layer (Fig. 14, 308, protection layer), the metal-insulator- metal capacitor (Fig. 14, 30) comprising a bottom conductor plate (Fig. 14, 312, bottom electrode), a first insulator layer (Fig. 14, 320, first dielectric layer) over the bottom conductor plate (Fig. 14, 312, bottom electrode) and laterally adjacent (annotated Figure 14) to the bottom conductor plate (Fig. 14, 312, bottom electrode), a middle conductor plate (Fig. 14, 332, middle electrode), over the first insulation layer (Fig. 14, 320, first dielectric layer), a second insulation layer (Fig. 14, 340, second dielectric layer) over the middle conductor plate (Fig. 14, 332, middle electrode), and a top conductor plate (Fig. 14, 352, top electrode) over the second insulation layer (Fig. 14, 340, second dielectric layer);
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON, HUANG, and HUNG to incorporate the teachings of CHANG such that a method, comprising: forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator- metal capacitor comprising a bottom conductor plate, a first insulator layer over the bottom conductor plate and laterally adjacent to the bottom conductor plate, a middle conductor plate, over the first insulation layer, a second insulation layer over the middle conductor plate, and a top conductor plate over the second insulation layer. The above arrangement of the MIM capacitors can be used as decoupling capacitors configured to mitigate power supply or switching noise caused by changes in the current, thus to prevent breakdown and improve the MIM capacitor performance (CHANG, [Col. 2, Lines 55-60]; [Col. 3, Lines 35-40]).
PARK as modified by WON, HUANG, HUNG, and CHANG does not explicitly disclose, a method comprising: performing a first etching process to form a first opening a and a second opening each extending through the second dielectric layer and the metal-insulator-metal capacitor, wherein the performing of the first etching process further forms a third opening spaced apart from each layer of the metal-insulator-metal capacitor, wherein each of the first opening and the second opening exposes a portion of a top surface of the etch stop layer; performing a second etching process to vertically extend the first opening, the second opening, and the third opening, thereby exposing the first lower contact feature, the second lower contact feature, and the third lower contact feature, respectively; forming a first contact via in the vertically extended first opening to contact the first lower contact feature; forming a second contact via in the vertically extended second opening to contact the second lower contact feature; after the forming of the metal-insulator-metal capacitor, removing a portion of the first insulation layer, thereby exposing a sidewall surface of the bottom conductor plate.
ZHANG teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]) comprising:
performing a first etching process (patterned with lithography and etching processes, [0018-0022]) to form a first opening (Fig. 6, 54, via opening, [0018-0022]) and a second opening (Fig. 6, 48, via opening, [0018-0022]) each extending through the second dielectric layer (Fig. 6, 36, [0018-0022]) and the metal-insulator-metal capacitor (Fig. 2, 32, patterned layers, [0020]) wherein the performing of the first etching process further forms a third opening (Fig. 6, 46, via opening, [0018-0022]) spaced apart from each layer of the metal-insulator-metal capacitor (annotated Figure 6), wherein each of the first opening and the second opening exposes a portion of a top surface of the etch stop layer (annotated Figure 6; not shown the trench only up to the top layer of capping layer 18, but it is obvious to etch up to the top surface and the Figure 4 shows penetration of the caping layer further);
performing a second etching process (patterned with lithography and etching processes, [0018-0022]) to vertically extend the first opening (Fig. 6, 54, via opening, [0018-0022]), the second opening (Fig. 6, 48, via opening, [0018-0022]), and the third opening (Fig. 6, 46, via opening, [0018-0022]), thereby exposing the first lower contact feature, the second lower contact feature, and the third lower contact feature (Fig. 6, 14, conductive wiring features; annotated Figure 6), respectively;
forming a first contact via (Fig. 7, 62/68, conductive wiring features/conductive vias [0026]) in the vertically extended first opening (Fig. 6, 54, via opening, [0018-0022]) to contact the first lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 6);
forming a second contact (Fig. 7, 62/66, conductive wiring features/conductive vias [0026]) via in the vertically extended second opening (Fig. 6, 48, via opening, [0018-0022]) to contact the second lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 6).
after the forming of the metal-insulator-metal capacitor (Fig. 1, 22, 24, 26, 28, 30, MIM capacitor stack, [0011]), removing a portion (Fig. 5, 56, cavities) of the first insulation layer (Figs. 2/5, 24), thereby exposing a sidewall surface (annotated Figure 5) of the bottom conductor plate (Fig. 5, 22).
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Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON, and HUANG to incorporate the teachings of ZHANG such that a method comprising: performing a first etching process to form a first opening a and a second opening each extending through the second dielectric layer and the metal-insulator-metal capacitor, wherein the performing of the first etching process further forms a third opening spaced apart from each layer of the metal-insulator-metal capacitor, wherein each of the first opening and the second opening exposes a portion of a top surface of the etch stop layer; performing a second etching process to vertically extend the first opening, the second opening, and the third opening, thereby exposing the first lower contact feature, the second lower contact feature, and the third lower contact feature, respectively; forming a first contact via in the vertically extended first opening to contact the first lower contact feature; forming a second contact via in the vertically extended second opening to contact the second lower contact feature. The aforementioned arrangement of MIM capacitor structure with a first electrode, a second electrode and a third electrode, further includes a conductive via in a via opening extending vertically through the layer stack, for the formation of a semiconductor structure that includes metal-insulator-metal (MIM) capacitor (ZHANG, [0001-0005]). Additionally, the above arrangement enables each of the patterned/etched layers (22, 24, 26, 28, 30) can be etched using single etch mask, 34 so that the electrodes and capacitor dielectrics have the same area and the same footprint projected onto the top surface of the dielectric layer, 20 (ZHANG, [0017]).
Regarding Claim 31, PARK as modified by WON, HUANG, HUNG, CHANG and ZHANG teaches a method of claim 30.
PARK further teaches in Figure 7G, a method ([0046]), further comprising:
during the forming of the metal-insulator-metal capacitor (annotated Figure 7G (above), forming a dummy conductor plate (Figs. 7A/7B, EL1, first electrode layer, [0024]) physically isolated from the bottom conductor plate (201, first electrode, [0024]), wherein the dummy conductor plate (Fig. 7A, EL1, first electrode layer, [0024]) and the bottom conductor plate (201, first electrode, [0024]) are formed simultaneously (Figs. 7A-7G).
Regarding Claim 32, PARK as modified by WON, HUANG, HUNG, CHANG and , ZHANG teaches a method of claim 31.
PARK further teaches in Figure 7G, a method ([0046]), wherein the first via (Fig. 7B, H1/H5, first hole/fifth hole) extends through the dummy conductor plate (Figs. 7A/7B, EL1, first electrode layer, [0024]).
Regarding Claim 34, PARK as modified by WON, HUANG, HUNG, CHANG and ZHANG teaches a method of claim 30.
PARK further teaches in Figure 7G, a method ([0046]), further comprising:
Removing a portion of the second insulation layer (207, second dielectric layer), that extends from the second lower contact feature (115, lower wiring layer) to the third lower contact feature (117, lower wiring layer).
CHANG further teaches a method (Fig. 1, 10, flow chart representing a method for manufacturing a MIM capacitor), further comprising:
wherein the portion (annotated Figure 14) of the second insulator layer (Fig. 14, 340, second dielectric layer) extends on the portion (annotated Figure 14) of the first insulator layer (Fig. 14, 320, first dielectric layer);
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Regarding Claim 35, PARK as modified by WON, HUANG, HUNG, CHANG and ZHANG teaches a method of claim 34.
ZHANG further teaches in Figure 7, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), further comprising:
forming a third contact via (Fig. 7, 62/64, conductive wiring features/conductive vias [0026]) in the vertically extended third opening (Fig. 6, 46, via opening, [0018-0022]) to contact the third lower contact feature (Figs. 6-7, 14, conductive wiring features; annotated Figure 7), wherein the third contact via (Fig. 7, 64, [0026]) is physically spaced apart (annotated Figure 7) from the first insulation (Fig. 7, 24, [0013]) layer and the second insulation layer (Fig. 7, 28, [0013]) by the second dielectric layer (Fig. 7, 36, [0018]).
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Regarding Claim 36, PARK as modified by WON, HUANG, HUNG, CHANG and ZHANG teaches a method of claim 34.
PARK further teaches in Figure 7G, a method ([0046]), wherein, in a top view (Fig. 1), the second lower contact feature (Figs. 1/7G, CP2/115, second contact plug/lower wiring layer) and the third lower contact feature (Figs. 1/7, CP3/117, third contact plug/lower wiring layer) extend lengthwise along different directions (annotated Figure 1).
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Claim(s) 21-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over PARK, WON, HUANG, ZHANG, HUNG.
Regarding Claim 21, PARK teaches in Figure 7G, a method ([0046]), comprising:
forming a first lower contact feature (113, lower wiring layer), a second lower contact feature (115, lower wiring layer), and a third lower contact feature (117, lower wiring layer) in a dielectric layer (111, interlayer insulation layer);
depositing an etch stop layer (121, buffer insulation layer) on the first lower contact feature (113, lower wiring layer), the second lower contact feature (115, lower wiring layer), and the third lower contact feature (117, lower wiring layer);
forming a bottom conductor plate (201, first electrode, [0024]) over the first lower contact feature (113, lower wiring layer);
after the forming of the bottom conductor plate (113, lower wiring layer), conformally depositing a first insulation layer (203, first dielectric layer) over the first dielectric layer (111, interlayer insulation layer);
forming a middle conductor plate (205, second electrode, [0026]) over the first insulation layer (203, first dielectric layer) and the second lower contact feature (115, lower wiring layer);
after the forming of the middle conductor plate (205, second electrode, [0026]), conformally depositing a second insulation layer (207, second dielectric layer) over the first dielectric layer (111, interlayer insulation layer);
forming a top conductor plate (209, third electrode, [0028]) over the second insulation layer (207, second dielectric layer) and the first lower contact feature (113, lower wiring layer).
Although the primary reference, PARK does not expressly refer to the buffer insulation layer, 121 as an etch stop layer, a buffer layer functions inherently as an etch stop layer because it functions to buffer or protect the underneath contact features, during an etch process; therefore, it meets the claim limitation of an etch stop layer.
WON teaches in paragraph [0050] that the first buffer layer, 120 is provided as an etch stop layer during a subsequent etching process.
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified PARK to incorporate the teachings of WON such that the buffer layer, 120 is provided as an etch stop layer, so that it serves as a reinforcing film for suppressing cracks of a dielectric film (WON, Fig. 9, [0050]).
Though PARK and WON refers the buffer insulation layer in place of etch stop layer, but does not explicitly disclose a method comprising: depositing an etch stop layer on the first lower contact feature, the second lower contact feature, and the third lower contact feature.
HUANG teaches a method comprising: depositing an etch stop layer (Fig. 2H, 216) on the first lower contact feature (Fig. 2H, 214, metal material), the second lower contact feature (Fig. 2H, 214, metal material), and the third lower contact feature (Fig. 2H, 214, metal material).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON to incorporate the teachings of HUANG such that a method comprising: depositing an etch stop layer on the first lower contact feature, the second lower contact feature, and the third lower contact feature so that the etch stop layer, 216 serve as via portions of the RDL structures, 250A, 250B and 250C (HUANG, Fig. 2H, [0035]).
PARK as modified by WON, and HUANG does not explicitly disclose a method comprising:
performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third contact feature.
after the forming of the bottom conductor plate, the middle conductor plate, and the top conductor plate, performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third lower contact feature; and
after the performing of the etching process, forming a second dielectric layer over the etch stop layer and the top conductor plate.
ZHANG teaches in Figures 1-2, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]) comprising:
performing an etching process (Fig. 2, 34, a single etch mask patterning, [0015-0017]) to remove portions (unmasked regions of layers 22/24/26/28/30 are removed with a n etching process, [0015]) of the first insulation layer (Fig. 2, 24, patterned dielectric layer, [0016]) and the second insulation layer (Fig. 2, 28, patterned dielectric layer, [0016]) extended over the third contact feature (Fig. 2, 14, conductive wiring feature; annotated Figure 2).
after the forming of the bottom conductor plate (Fig. 1, 22), the middle conductor plate (Fig. 1, 26), and the top conductor plate (Fig. 1, 30), performing an etching process ([0015]) to remove portions of the first insulation layer (Fig. 2, 24) and the second insulation layer Fig. 2, 28) extended over the third lower contact feature (Fig. 2, 14, conductive wiring feature); and
after the performing of the etching process ([0015]), forming a second dielectric layer (Fig. 3, 36) over the etch stop layer (Fig. 3, 18, capping layer) and the top conductor plate (Fig. 1, 30).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON, and HUANG to incorporate the teachings of ZHANG such that a method comprising: performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third contact feature; after the forming of the bottom conductor plate, the middle conductor plate, and the top conductor plate, performing an etching process to remove portions of the first insulation layer and the second insulation layer extended over the third lower contact feature; and after the performing of the etching process, forming a second dielectric layer over the etch stop layer and the top conductor plate. The above arrangement enables each of the patterned/etched layers (22, 24, 26, 28, 30) can be etched using single etch mask, 34 so that the electrodes and capacitor dielectrics have the same area and the same footprint projected onto the top surface of the dielectric layer, 20 (ZHANG, [0017]).
Though PARK as modified by WON, HUANG and ZHANG teaches a method comprising: forming a metal-insulator-metal capacitor over the etch stop layer (or buffer layer), the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer (or buffer layer) with either interlayer insulation layer or dielectric layer in between the MIM capacitor and the etch stop layer, PARK as modified by WON, HUANG and ZHANG does not disclose a method comprising: forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer (i.e. MIM capacitor layer directly on the etch stop layer as exhibited by the Figure 10 of the instant application).
HUNG teaches in Figure 2D, a method (Fig. 1, 100, flow chart of an exemplary method for forming a semiconductor device, [0006]) comprising: forming a metal-insulator-metal capacitor (Fig. 2C, 200-1, MIM capacitor, [0022]; Fig. 2D, 236-238-224; bottom metal plate-capacitor dielectric layer-top metal plate [0022-0023]) over the etch stop layer (Fig. 2D, 206), the metal-insulator-metal capacitor comprising a bottom plate (Fig. 2D, 236, bottom metal plate) over etch stop layer (Fig. 2D, 236, bottom metal plate over 206, etch stop layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have PARK as modified by WON, HUANG and ZHANG to incorporate the teachings of HUNG such that a method, comprising: forming a metal-insulator-metal capacitor over the etch stop layer, the metal-insulator-metal capacitor comprising a bottom plate over etch stop layer, so that the first metal layer (208) is disposed over the first etch stop layer (206); the dummy capacitor dielectric layer (210) is disposed over the first metal layer (208); the second metal layer (212) is disposed over the dummy capacitor dielectric layer (210) to form a MIM capacitor (200-1) of a semiconductor device that can be used in various radio frequency (RF) circuits, in dynamic random-access memory cells and high-power microprocessor units (HUNG, Fig. 2C, [0002], [0017]).
Regarding Claim 22, PARK as modified by WON, HUANG, ZHANG and HUNG teaches a method of claim 21.
PARK further teaches in Figure 7G, a method ([0046]), , wherein, after the performing the etching process ([0060]), of the first insulation layer (203, first dielectric layer), the second insulation layer (203, first dielectric layer) and the bottom conductor plate (201, first electrode, [0024]) of MIM structure (annotated Figure 7G).
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ZHANG further teaches in Figures 2, and 3, the method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007]), wherein, after the performing of the etching process (Fig. 2, 34, single etch mask, [0017]), sidewall surfaces (Fig. 2, 31, same sidewall, [0017]) of the first insulation layer (Fig. 2, 24) and the second insulation layer (Fig. 2, 28) are vertically aligned (Fig. 2A, arrow pointing up) with a sidewall surface of the bottom conductor plate (Fig. 2, 22, conductive material layer, [0012]).
Regarding Claim 23, PARK as modified by WON, HUANG, ZHANG and HUNG teaches a method of claim 21.
PARK further teaches in Figure 7G, a method ([0046]), wherein an entirety of a top surface (annotated Figure 7G) of the top conductor plate (209, third electrode, [0028]) is above a topmost surface (annotated Figure 7G) of the second insulation layer (211, interlayer insulation layer).
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Regarding Claim 24, PARK as modified by WON, HUANG, ZHANG and HUNG teaches a method of claim 21.
PARK further teaches in Figure 7G, a method ([0046]), wherein a distance between the first lower contact feature (113, lower wiring layer) and the third lower contact feature (117, lower wiring layer) is greater than a distance (annotated Figure 7G) between the bottom conductor plate (201, first electrode, [0024]) and the third lower contact feature (117, lower wiring layer).
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Regarding Claim 25, PARK as modified by WON, HUANG, ZHANG and HUNG teaches a method of claim 23.
ZHANG further teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007], wherein the etching process (patterned with lithography and etching processes, [0018-0022]) is a first etching process, and the method further comprises:
performing a second etching process (patterned with lithography and etching processes, [0018-0022]) to form a first via opening (Fig. 6, 54, via opening, [0018-0022]) and a second via opening (Fig. 6, 48, via opening, [0018-0022]) each extending through the second dielectric layer (Fig. 3, 36, [0018]), the first via opening and the second via opening each exposing the etch stop layer (Fig. 3, 18, caping layer, [0018]; annotated Figure 6; not shown the trench only up to the top layer of capping layer 18, but it is obvious to etch up to the top surface and the Figure 4 shows penetration of the caping layer further);
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performing a third etching process (patterned with lithography and etching processes, [0018-0022]) to remove portions of the etch stop layer (Fig. 3, 18, caping layer, [0018]) exposed by the first via opening (Fig. 6, 54, via opening, [0018-0022]) and the second via opening (Fig. 6, 48, via opening, [0018-0022]), thereby exposing the first lower contact feature and the second lower contact feature, respectively (Fig. 6, 14, conductive wiring features; annotated Figure 6; and
forming a first via (Fig. 8, 68, conductive via) and a second via (Fig. 8, 66, conductive via) in the first via opening (Fig. 6, 54, via opening) and the second via opening (Fig. 6, 48, via opening), respectively.
HUANG further teaches that the forming of a dielectric layer over the etch stop layer (Fig. 2H, 216), the via openings exposing the etch stop layer (Fig. 2H, 216) and removing the portions of the etch stop layer (Fig. 2H, 216) to expose the contact features (Fig. 2H, 214, metal material).
Regarding Claim 26, PARK as modified by WON, HUANG, ZHANG and HUNG teaches a method of claim 25.
ZHANG further teaches in Figures 3-6, a method (Figs. 1-7, processing method for a device structure at successive fabrication stages, [0007], comprising:
forming a third via (Fig. 8, 64, conductive via) extending through the second dielectric layer (Fig. 8, 36, dielectric layer) and the etch stop layer (Fig. 8, 18, capping layer) to physically contact the third lower contact feature (Fig. 6, 14, conductive wiring features; annotated Figure 6).
HUANG further teaches that the forming a third via (Fig. 2H, 264C, openings) extending through the second dielectric layer (Fig. 2H, 246) and the etch stop layer (Fig. 2H, 216) to physically contact the third lower contact feature (Fig. 2H, 214, metal material).
Regarding Claim 27, PARK as modified by WON, HUANG, ZHANG and HUNG teaches a method of claim 26.
PARK further teaches in Figure 7G, a method ([0046]), wherein, in a top view (Fig. 1), the third lower contact feature (Figs. 1/7G, CP3/117, third contact plug/lower wiring layer) extends lengthwise along a first direction (annotated Figure 1), the third lower contact feature (Figs. 1/7, CP3/117, third contact plug/lower wiring layer) is disposed laterally adjacent to the first lower contact feature (Figs. 1/7G, CP1/113, first contact plug/lower wiring layer) along a second direction (annotated Figure 1) that is substantially perpendicular (annotated Figure 1) to the first direction (annotated Figure 1).
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Regarding Claim 28, PARK as modified by WON, HUANG, ZHANG and HUNG teaches a method of claim 26.
PARK further teaches in Figure 7G, a method ([0046]), wherein, in the top view (Fig. 1), a length of the first lower contact feature (Figs. 1/7G, CP1/113, first contact plug/lower wiring layer) is less than (annotated Figure 1) a length of the third lower contact feature (Figs. 1/7G, CP3/117, third contact plug/lower wiring layer).
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Regarding Claim 29, PARK as modified by WON, HUANG, ZHANG and HUNG teaches a method of claim 25.
PARK further teaches in Figure 7G, a method ([0046]), , further comprising:
forming a dummy conductor plate (Figs. 7A/7B, EL1, first electrode layer, [0024]) during the forming of the bottom conductor plate (201, first electrode, [0024]), wherein the second via (Fig. 7B, H1/H5, first hole/fifth hole) further extends through the dummy conductor plate (Figs. 7A/7B, EL1, first electrode layer, [0024]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 6573587 B1 – Figures 5(a)-5(e)
STATEMENT OF RELEVANCE – Cross-sectional drawing showing respective processes of a method of manufacturing the semiconductor device (capacitors).
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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