DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on January 30, 2026 has been entered. No claim(s) has/have been canceled or added. Therefore, claim(s) 1-18 and 31-22 continue to be pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 7 and 21-22 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 7, as currently presented the claim requires that the overlap between the first sidewalls of the metal layers be greater than 0 nm, while the first sidewall have a linear profiles along a second direction that requires for the overlap to be zero. Accordingly, it is not clear how the overlap can be simultaneously zero and non-zero. For purpose of compact prosecution, it will be assumed that in order for the first sidewalls to have a linear profiles the overlap has to be zero.
With respect to claim 21, the claim recites the limitation "through via" three times (in lines 7,13 and 25). It is unclear whether the second and third recited “through via” were intended to relate back to “through via” recited in line 7 or to set forth additional through vias. Moreover, it is unclear as to what the recited through vias, that are facing sidewalls of first metal line and first metal via and second metal line and second metal via are substantially aligned to along the first direction. For purpose of compact prosecution, through vias, will be assumed as referring to the same through via, such as through via 130, shown, for example in Fig. 1. Claim 22 which directly depends from claim 21, and which inherits issues of claim 21 is rejected for similar reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang (US 2022/0344284, hereinafter “Chang”).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Chang teaches in Fig. 2 (shown below) and related text, a semiconductor structure comprising:
a device substrate (202, Fig. 2 and ¶[0027]) having a first side and a second side;
a dielectric layer (204, 206, Fig. 2 and ¶¶[0028]-[0029) disposed over the first side of the device substrate;
a through via (208, Fig. 2 and ¶[0030]) that extends along a first direction (i.e. direction extending from top to bottom of the device, Fig. 2) through the dielectric layer (Fig. 2) and through the device substrate (202, Fig. 2) from the first side to the second side (Fig. 2 and ¶[0030]); and
a guard ring (222, Fig. 2 and ¶[0036]) disposed in the dielectric layer and around the through via (208, Fig. 2),
wherein:
the guard ring includes metal layers (222, Fig. 2 and ¶¶[0002] and [0055]) stacked along the first direction,
the metal layers include first sidewalls and second sidewalls, wherein the first sidewalls have linear profiles along a second direction different than the first direction, the second sidewalls have non-linear profiles along the second direction, and the first sidewalls form an inner sidewall of the guard ring (Fig. 2), and
the metal layers include first portion disposed over a second portion, wherein the first portion has a first width, the second portion has a second width and the first width is greater than the second width, and
an overlap between the first sidewalls of the metal layers is less than about 10 nm (i.e. the overlap between the first sidewalls of the metal layers 222 is zero, which is less than 10nm, Fig. 2), wherein the overlap is along the second direction (i.e. direction from left to right of the device, Fig. 2); and
wherein the inner sidewall of the guard ring encompasses a region in the dielectric layer (Fig. 2) through which the through via (208, Fig. 2) extends, the region in the dielectric layer defined by the inner sidewall of the guard ring has a first dimension (i.e. 1st dimension having a width approximately equal to the width 228, Fig. 2, which is approximately 0.1 micrometer and ¶[0038]) along the second direction, the through via has a second dimension (i.e. width of 208 (10 micrometers), Fig. 2 and ¶[0019], i.e. 1% of width of 208 equals to 0.1 micrometer) along the second direction, and a ratio of the first dimension to the second dimension is greater than zero and less than about two (¶¶[019] and [0038]).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2021/0249365, hereinafter, “Liu”, previously cited) in view of Tsai et al. (US 2015/0348874, hereinafter “Tsai”, previously cited).
Regarding claim 1, Liu teaches in Fig. 5 (annotated Fig. 5 shown below) and related text, a semiconductor structure comprising:
a device substrate (116, annotated Fig. 5 and ¶[0015]) having a first side and a second side;
a dielectric layer (112, 114, 120, 122, 124, annotated Fig. 5 and ¶[0015]) disposed over the first side of the device substrate;
a through via (186, annotated Fig. 5 and ¶[0042]) that extends along a first direction (i.e. direction extending from top to bottom of the device, annotated Fig. 5) through the dielectric layer (Fig. 5) and through the device substrate (116, annotated Fig. 5) from the first side to the second side (annotated Fig. 5); and
a guard ring (118, annotated Fig. 5 and ¶[0015]) disposed in the dielectric layer and around the through via (186, annotated Fig. 5),
wherein:
the guard ring includes metal layers (128/130, annotated Fig. 5 and ¶[0022]) stacked along the first direction,
the metal layers include first sidewalls and second sidewalls, wherein the first sidewalls form an inner sidewall of the guard ring (annotated Fig. 5), and
an overlap between the first sidewalls of the metal layers is less than about 10 nm (i.e. the overlap between the first sidewalls of the metal layers 128 is zero, which is less than 10 nm, annotated Fig. 5), wherein the overlap is along the second direction (i.e. direction from left to right of the device, annotated Fig. 5), different than the first direction; and
wherein the inner sidewall of the guard ring encompasses a region in the dielectric layer (annotated Fig. 5) through which the through via (186, annotated Fig. 5) extends, the region in the dielectric layer defined by the inner sidewall of the guard ring has a first dimension (i.e. 1st dimension having a width smaller than width 132 which is disclosed as 3 to 6 micrometers, annotated Fig. 5 and ¶[0023]) along the second direction, the through via has a second dimension (i.e. width of 182/188 of 0.5 to 4 micrometers, annotated Fig. 5 and ¶[0040]) along the second direction, and a ratio of the first dimension to the second dimension is greater than zero and less than about two (¶¶[0023] and [0040]).
[AltContent: textbox (1st direction)][AltContent: ][AltContent: textbox (1st side of device substrate)][AltContent: textbox (inner sidewall of guard ring)][AltContent: ][AltContent: textbox (pitch)][AltContent: ][AltContent: ][AltContent: ][AltContent: ][AltContent: textbox (1st dimension)][AltContent: textbox (spacing between through via and inner sidewall of guard ring)][AltContent: arrow][AltContent: ][AltContent: textbox (2nd direction)][AltContent: arrow][AltContent: arrow][AltContent: textbox (4th metallization)][AltContent: textbox (3rd metallization)][AltContent: textbox (2nd metallization)][AltContent: textbox (1st metallization)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: ][AltContent: ][AltContent: ][AltContent: textbox (3rd set)][AltContent: textbox (2nd set)][AltContent: ][AltContent: textbox (region in dielectric layer)][AltContent: textbox (1st set)][AltContent: textbox ((Annotated Figure))][AltContent: connector][AltContent: connector][AltContent: connector]
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Liu, however, does not explicitly teach wherein the first sidewalls have linear profiles along a second direction different than the first direction, the second sidewalls have non-linear profiles along the second direction, and the first sidewalls form an inner sidewall of the guard ring, the metal layers include a first portion disposed over a second portion, wherein the first portion has a first width, the second portion has a second width, and the first width is greater than the second width.
Tsai, in a similar field of endeavor, teaches in Figs. 3A and 3C, and related text, that a guard ring (e.g. 508/538, Fig. 3A) with an inner sidewalls having a non-linear profiles (Fig. 3A), similar to that disclosed by Liu, and a guard ring (508/538, Fig. 3C and ¶[0065]) wherein first sidewalls have linear profiles along a second direction different than a first direction, second sidewalls have non-linear profiles along the second direction, and the first sidewalls form an inner sidewall of the guard ring, the metal layers include a first portion disposed over a second portion, wherein the first portion has a first width, the second portion has a second width, and the first width is greater than the second width (Fig. 3C and ¶[0065]) can be used interchangeably in order to meet specific design requirements for the device.
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the guard ring disclosed by Tsai with first sidewalls have linear profiles along a second direction different than a first direction and second sidewalls having non-linear profiles along the second direction, such that the first sidewalls form an inner sidewall of the guard ring, the metal layers include a first portion disposed over a second portion, wherein the first portion has a first width, the second portion has a second width, and the first width is greater than the second width, in place of the guard ring disclosed by Liu, in order to meet specific design requirements for the device.
Regarding claim 2 (1), the combined teaching of Liu and Tsai was discussed above in the rejection of claim 1 and includes a first set of the metal layers (Liu, e.g. a first set of 128 and 130, annotated Fig. 5) has a first overlap, a second set of the metal layers (Liu, e.g. a second set of 128 and 130, annotated Fig. 5) has a second overlap. While Liu and Tsai do not explicitly teach in the embodiment of Fig. 5 of Liu that the second overlap is different than the first overlap, and the first overlap and the second overlap are each less than about 10 nm, Liu teaches that metal layers 128 and vias 130 in different sets of metal layers can have different widths (Liu, ¶[0022]), which would result in different overlaps between the first set of the metal layers and a second set of the metal layers.
Accordingly, based on Liu’s teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change widths of the metal layers within the first and second set of metal layers disclosed in the embodiment of Fig. 5, so that the second overlap is different than the first overlap, and the first overlap and the second overlap are each less than about 10 nm in order to meet specific design requirement for the semiconductor device.
Regarding claim 3 (2), the combined teaching of Liu and Tsai discloses wherein the first set of the metal layers (Liu, annotated Fig. 5) is between the second set of the metal layers (Liu annotated Fig. 5) and the first side of the device substrate (Liu, annotated Fig. 5). While Liu and Tsai do not explicitly teach in the embodiment of Fig. 5 of Liu that the first overlap is less than the second overlap, Liu explicitly teaches that the first set of metal layers and the second set of metal layer could have different widths (Liu, ¶[0022]), which would allow to form metal layers within each set of the metal layers such that the first overlap is less than the second overlap, in order to meet specific design requirements for the device.
Accordingly, based on Liu’s teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change widths of the metal layers within the first and second set of metal layers disclosed in the embodiment of Fig. 5, so that the first overlap is less than the second overlap in order to meet specific design requirement for the semiconductor device.
Regarding claim 4 (3), the combined teaching of Liu and Tsai further discloses wherein a third set of the metal layers (Liu, annotated Fig. 5) has a third overlap, the second set of the metal layers is between the third set of the metal layers and the first set of the metal layers (Liu, annotated Fig. 5). While Liu and Tsai do not explicitly teach in the embodiment of Fig. 5 of Liu that the third overlap is different than the first overlap and the second overlap and that the third overlap is greater than the second overlap, Liu explicitly teaches that different sets of metal layers could have different widths (Liu, ¶[0022]), which would allow to form metal layers within each set of first, second and third metal layers, such that the third overlap is different than the first overlap and the second overlap and that the third overlap is greater than the second overlap in order to meet specific design requirements for the device.
Accordingly, based on Liu’s teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the widths of metal layers in the first set of metal layers, the second set of metal layers and the third set of metal layers so that the third overlap is different than the first overlap and the second overlap and that the third overlap is greater than the second overlap, in order to meet specific design requirement for the semiconductor device.
Regarding claim 5 (2), the combined teaching of Liu and Tsai further discloses a multilayer interconnect structure (Liu, 200, annotated Fig. 5) disposed in the dielectric layer (Liu, 114, 120, 122, 124, annotated Fig. 5), wherein the multilayer interconnect structure includes a first set of metallization layers (Liu, e.g. 200, on the same level as the first set of metal layers, annotated Fig. 5A) having a first pitch (Liu, i.e. where a pitch is considered a sum of a width of metal lines of the patterned metal layer and a spacing between directly adjacent metal lines of the patterned metal layer the patterned metal layer, ¶[0028] of the instant application as published) and a second set of metallization layers (Liu, e.g. 200, on the same level as the third set of metal layers, annotated Fig. 5A) having a second pitch (Liu, annotated Fig. 5) and the first set of the metal layers are a portion of the first set of metallization layers and the second set of the metal layers are a portion of the second set of metallization layers (Liu, annotated Fig. 5 and ¶[0026]). While Liu and Tsai do not explicitly teach that the second pitch is different than the first pitch, Liu teaches in Figs. 5 and 6 that pitches between adjacent metal line (i.e. spacing between adjacent conductive elements 200, annotated Fig. 5 (e.g. pitch in 1st and 2nd metallization layers are different) and Fig. 6) can vary in order to meet specific design requirements.
Accordingly, based on Liu’s teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first and second metallization with different pitches in order to meet specific design requirements.
Regarding claim 6 (5), the combined teaching of Liu and Tsai discloses wherein the first set of metallization layers is between the second set of metallization layers and the first side of the device substrate (Liu, annotated Fig. 5). While Liu and Tsai do not explicitly teach in the embodiment of Fig. 5 of Liu that the first pitch is less than the second pitch, Liu teaches that different pitches might be used in different metallization layers (Liu, e.g. pitch in 1st metallization layer is smaller than in 2nd metallization layer, annotated Fig. 5) in order to meet specific design requirements.
Accordingly, based on Liu’s teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the first and/or second pitch disclosed by Liu and Tsai, so that the first pitch is less than the second pitch, in order to meet specific design requirements.
Regarding claim 8 (1), the combined teaching of Liu and Tsai was discussed above and includes a spacing between the through via and the inner sidewall of the guard ring (Liu, annotated Fig. 5), the spacing is along the second direction (Liu, annotated Fig. 5). While Liu and Tsai, do not explicitly teach that the spacing is about 20 nm to about 50 nm, changing the spacing between the through via and the inner sidewall of the guard ring to the be within the claimed range would have been an obvious matter of design choice, since such a modification would have involved a mere change in the size of the components. A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the spacing between the through via and the inner sidewall of the guard ring to the be within the claimed range as doing so would be an obvious matter of design choice that would allow to meet specific design requirements.
Regarding claim 9 (1), the combined teaching of Liu and Tsai discloses wherein a first set of the metal layers has a first width along the second direction and a second set of the metal layers has a second width along the second direction. While Liu and Tsai do not explicitly teach in the embodiment of Fig. 5A of Liu that the second width is different than the first width, Liu explicitly teaches that the metal layers in different sets can have different widths (Liu, ¶[0022]) depending on specific design requirements for the device.
Accordingly, based on Liu’s teaching, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the width of the metal layers of the guard ring disclosed by Liu and Tsai, so that the width of the first metal layer is different form the width of the second metal layer, in order to meet specific design requirements for the device.
Allowable Subject Matter
Claim(s) 10-18 are allowed.
Regarding claims 10, the prior art of record, alone or in combination, and to the examiner’s knowledge does not teach, disclose, suggest, or render obvious, at least to the skilled artisan, the instant invention regarding a semiconductor arrangement particularly characterized by an overlap between interconnect structures of a stack of interconnect structures forming a ring around a conductive structure that increases along a height of the stack of interconnect structures, as recited in the claim in combination with all other elements of the semiconductor arrangement. The closest prior art of record to KU (US 2022/0254739) or Weng (US 2020/0006128) fails to discloses the above noted elements of the claim. Claim(s) 11-18, which either directly or indirectly depend from claim(s) 10, and which include all of the limitations recited in claim(s) 10, is/are allowed for the similar reasons.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893