Prosecution Insights
Last updated: April 19, 2026
Application No. 17/832,580

Semiconductor Devices With Reduced Leakage Current And Methods Of Forming The Same

Final Rejection §103§112
Filed
Jun 04, 2022
Examiner
ADHIKARI DAWADI, BIPANA
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
3 (Final)
100%
Grant Probability
Favorable
4-5
OA Rounds
3y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
3 granted / 3 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
39 currently pending
Career history
42
Total Applications
across all art units

Statute-Specific Performance

§103
52.4%
+12.4% vs TC avg
§102
12.7%
-27.3% vs TC avg
§112
31.9%
-8.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 3 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Examiner’s Note Applicant's request, during the interview on February 26, 2026, for reconsideration of the finality of the rejection of the last Office action is persuasive and, therefore, the finality of that action is withdrawn. The last office action mailed on 02/12/2026 is withdrawn and the time period for reply to the office action will be restarted with the mailing date of this office action. Response to Arguments 2. Regarding claims 1-4, 6, 21-23 Rejected under 35 U.S.C. 112(b), applicant amendment has been fully considered. The amendment overcomes the 35 U.S.C. 112(b) rejections, hence 35 U.S.C. 112(b) rejection is withdrawn for claims 1-4, 6, 21-23. 3. In view of claim amendments incorporating allowable subject matter and applicant’s arguments, filed on 11/17/2025, with respect to claims 1 and 9 have been fully considered and are persuasive. The rejection of claims 1 and 9 and their corresponding dependent claims have been withdrawn. 4. Applicant's arguments regarding claim 25 have been fully considered but they are not persuasive. Applicant states that “Park's sacrificial gate 112 and sacrificial layers 106a, 106b, 106c as corresponding to the claimed "gate structure". More specifically, the Office Action relies on Park's sacrificial gate 112 as corresponding to the claimed "first portion" of the "gate structure", and relies on Park's sacrificial layers 106a, 106b, 106c as corresponding to the claimed "second portion" of the "gate structure". However, Park discloses "each of the sacrificial layers 106 a, b, c, ...are deposited/formed on substrate 102 using an epitaxial growth process" and "the sacrificial layers 106 a, b, c, etc. are each formed from SiGe" (emphasis added). Park, [0029] and [0031]. That is, Park's sacrificial layers 106a-106c (the alleged "second portion" of the gate structure) are formed of SiGe. However, the Office Action does not provide rationale or evidence showing a gate structure can be formed of SiGe. Thus, Park fails to disclose "forming a gate structure comprising a first portion over the plurality of nanostructures and a second portion wrapping around the plurality of nanostructures...; removing a portion of the gate spacers and a part of the first portion of the gate structure, thereby forming a trench", as recited in claim 25.” However, claim 25 does not recite any limitation requiring the gate structure (or the first/second portion thereof) to be formed from any particular material or the same material. Furthermore, the claim language does not restrict “gate structure” to only a complete metal gate stack, nor does it exclude sacrificial/dummy gate structures or other intermediate fabrication structures that function as a “gate structure” in the process flow. Thus, Applicant’s argument effectively assumes that a “gate structure” must be composed only of materials traditionally associated with a final gate electrode which is not commensurate with the scope of claim 25 as presently written. Claim Rejections - 35 USC § 103 5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 7. Claims 25-28 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20230027413 A1) in view of Wu (US 20200343362 A1). Re: Independent Claim 25 (Previously presented), Park discloses a method, comprising: forming a plurality of nanostructures (Park, Fig 4, #106a, b, c and #108a, b, c) over a substrate (Park, Fig 4, #102); forming a gate structure (Park, fig 4, #112 and #106a, b, c) comprising a first portion (Park, Fig 4, #112) over the plurality of nanostructures and a second portion (Park, fig 4, 106a, 106b, 106c) wrapping around the plurality of nanostructures; forming gate spacers (Park, Fig 4, #302' and #304') extending along sidewalls of the first portion of the gate structure; removing a portion of the gate spacers (Park, Fig 8, 304') and a part of the first portion of the gate structure (Park, Fig 11 and Fig 12, #112 is removed) thereby forming a trench (Park, Fig 12, #1202). Park is silent regarding: wherein the trench has a top portion having a non-uniform width and a bottom portion having a uniform width; forming dielectric spacers in the top portion of the trench; and forming a conductive cap in the bottom portion of the trench. However, Wu teaches the trench has a top portion having a non-uniform width and a bottom portion having a uniform width (Wu, Fig 1G, #118′); forming dielectric spacers in the top portion of the trench (Wu, Fig 1K, #126 is in the top portion of the trench); and forming a conductive cap (Wu, Fig 1J, #130) in the bottom portion of the trench. It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use Wu disclosed trench that has a top portion having a non-uniform width and a bottom portion having a uniform width in the method of Park in order to have a wider upper portion, which facilitates the subsequent formation of a metal gate stack (Wu, ¶ [0082], lines 5-7); forming dielectric spacers in the top portion of the trench in the method of Park in order to control shape creating optimal device profiles for better performance; and forming a conductive cap in the bottom portion of the trench in the method of Park in order to enhance performance by improving isolation, reducing unwanted electrical interactions. Re: Claim 26 (Previously presented), Park and Wu disclose all the limitations of claim 25 on which this claim depends. Wu further discloses: wherein, a width of the conductive cap is substantially equal to a width of the first portion of the gate structure (Wu, Fig 1K, conductive cap 130 fills gate structure, resulting in same width as the gate structure). Re: Claim 27 (Previously presented), Park and Wu disclose all the limitations of claim 25 on which this claim depends. PNG media_image1.png 641 696 media_image1.png Greyscale Wu further discloses: wherein a top surface of one of the dielectric spacers spans a first width (Wu annotated Fig 1K up above showing width "Wd" in a top surface of one of the dielectric spacers), and a bottom surface of one of the gate spacers (Wu annotated Fig 1K up above showing width "Wg" in a bottom surface of one of the gate spacers #110) spans a second width less than the first width. Re: Claim 28 (Previously presented), Park and Wu disclose all the limitations of claim 25 on which this claim depends. Wu further discloses: wherein one of the dielectric spacers comprises a first sidewall (Wu, Fig 1K, sidewall of #126 along #110) and a second sidewall (Wu, Fig 1K, sidewall of #126 along #128) opposite the first sidewall, the first sidewall curves outward (#126 has curve profile). 8. Claims 29-30 are rejected under 35 U.S.C. 103 as being unpatentable over Park (US 20230027413 A1) in view of Wu (US 20200343362 A1) and further in view of Adusumilli (US 20170077256 A1). Re: Claim 29 (Previously presented), Park and Wu disclose all the limitations of claim 28 on which this claim depends. Both Park and Wu are silent regarding: wherein the conductive cap extends along a portion of the second sidewall of the one of the dielectric spacers. However, Adusumilli teaches the conductive cap extends along a portion of the second sidewall of the one of the dielectric spacers (Adusumilli, Fig 4, conductive cap #32 extends along second sidewall of dielectric spacer #23). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use Adusumilli disclosed conductive cap extends along a portion of the second sidewall of the one of the dielectric spacers in the method of Park in view of Wu in order to seal the metal gates, effectively protecting the metal gates from subsequent etch process (Adusumilli, ¶ [0037], lines 15-16). Re: Claim 30 (Previously presented), Park and Wu disclose all the limitations of claim 25 on which this claim depends. Both Park and Wu are silent regarding: forming a dielectric cap on the conductive cap, wherein a top surface of the dielectric cap is substantially coplanar with top surfaces of the dielectric spacers. However, Adusumilli teaches forming a dielectric cap (Adusumilli, Fig 4, dielectric cap #33) on the conductive cap (Adusumilli, Fig 4, conductive cap #32), wherein a top surface of the dielectric cap is substantially coplanar with top surfaces of the dielectric spacers (fig 4, ¶ [0041], lines 15-16, dielectric spacers #23). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to use Adusumilli disclosed forming a dielectric cap on the conductive cap, wherein a top surface of the dielectric cap is substantially coplanar with top surfaces of the dielectric spacers in the method of Park in view of Wu in order to prevent shorting between the metal gate and subsequently formed and possibly self-aligned contacts (Adusumilli, ¶[0038], lines 10-12). Allowable Subject Matter 9. Claims 1-4, 6, 9-13 and 21-24 allowed. The following is a statement of reasons for the indication of allowable subject matter: The closest prior arts to the present inventions are Wu (US 20200343362 A1) and Adusumilli (US 20170077256 A1). Regarding independent claim 1, there is no teaching or suggestion in the prior art of record to provide a method, comprising performing an etching process to recess the gate spacers and remove an upper portion of the gate structure, thereby forming a funnel-shaped trench exposing a lower portion of the gate structure; depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench; etching back the dielectric layer to form dielectric spacers on the recessed gate spacers; forming a metal cap on the lower portion of the gate structure without forming the metal cap on the recessed gate spacers; and forming a dielectric cap on the metal cap. Regarding independent claim 9, there is no teaching or suggestion in the prior art of record to provide a method comprising the selectively removing of the upper portion of the gate stack and the upper portion of the gate spacer layer, forming a dielectric spacer directly over the gate spacer layer, wherein the dielectric spacer is spaced apart from a remaining portion of the gate stack; forming a metal cap directly over the gate stack; and forming a dielectric cap directly over the metal cap. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BIPANA ADHIKARI DAWADI whose telephone number is (571)272-4149. The examiner can normally be reached Monday-Friday 11:30am-7:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BIPANA ADHIKARI DAWADI/Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
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Prosecution Timeline

Jun 04, 2022
Application Filed
Aug 04, 2025
Non-Final Rejection — §103, §112
Nov 17, 2025
Response Filed
Feb 06, 2026
Final Rejection — §103, §112
Feb 19, 2026
Interview Requested
Mar 09, 2026
Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604581
METHOD FOR MANUFACTURING ELECTRONIC DEVICE
2y 5m to grant Granted Apr 14, 2026
Study what changed to get past this examiner. Based on 1 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 9m
Median Time to Grant
High
PTA Risk
Based on 3 resolved cases by this examiner. Grant probability derived from career allow rate.

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