DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/25 has been entered.
Election/Restrictions
Applicant’s election without traverse to the restriction requirement mailed on 12/16/24, of Group I (device claims 1-8 and 16-20), in the reply filed on 12/30/24 was acknowledged in a previous office action. Claims 9-15 are withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-6, 8, and 21 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2020/0091309 A1 (“Lin”).
Lin teaches, for example:
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Lin teaches:
1. A semiconductor device, comprising:
at least two active strip regions (e.g. 106a and 106b);
an isolation structure (see below; see e.g. Fig. 9B) disposed between the at least two active strip regions; and
a gate stack (e.g. 124, which may comprise multiple layers such as a capping layer, barrier layer, or work-function layer, see e.g. para 36; or 124/128) across the at least two active strip regions and the isolation structure,
wherein the isolation structure comprises:
a lower dielectric layer comprising:
a first dielectric layer (e.g. 103) having a U-shaped cross-sectional profile (see e.g. Fig. 9B) in an extending direction of the gate stack (e.g. left-to-right as shown in Fig. 9B);
a second dielectric layer (e.g. 104) disposed on an inner surface of the first dielectric layer; and
a high dielectric constant (high-k) dielectric layer (e.g. 122) disposed on the lower dielectric layer, wherein the gate stack covers the high-k dielectric layer so that a top surface of the high-k dielectric layer is lower than a top surface of the gate stack (see e.g. Fig. 9B),
wherein the high-k dielectric layer has a dielectric constant greater than a dielectric constant of the first and second dielectric layers (122 is a high-k material, such as having dielectric constant higher than about 7, see e.g. para 35; whereas liner 103 and 104 may be e.g. SiO2, SiN, or SiON, see e.g. para 19-20; SiO2, SiN, and SiON are well-known to be low-k dielectric materials having dielectric constant around 2.8), and
the high-k dielectric layer interfaces with a top surface of the first dielectric layer and a top surface of the second dielectric layer in the extending direction of the gate stack (see e.g. Fig. 9B).
3. The semiconductor device of claim 1, wherein a sidewall of the high-k dielectric layer is aligned with a sidewall of the gate stack (see e.g. Fig. 9B).
5. The semiconductor device of claim 1, further comprising:
source/drain features (e.g. 112, see e.g. Fig. 12) disposed on the at least two active strip regions at opposite sides of the gate stack; and
source/drain contact plugs (e.g. 142, see e.g. Fig. 12) disposed on the source/drain features, wherein a portion of the source/drain contact plugs extends between adjacent two gate stacks (see e.g. Fig. 1, middle 112 on each 106a and 106b), and the high-k dielectric layer is not included under the source/drain contact plugs (see e.g. Fig. 12).
6. The semiconductor device of claim 5, further comprising:
an etch stop layer (e.g. 132) extending between the source/drain contact plugs and the gate stack (see e.g. Fig. 12), and conformally covering a sidewall of the high-k dielectric layer covered by the gate stack (see e.g. Fig. 12); and
an inter-layer dielectric (ILD) layer (e.g. 134) disposed on the etch stop layer,
wherein a portion of the ILD layer extends between the source/drain contact plugs and the gate stack (see e.g. Fig. 12).
8. The semiconductor device of claim 1, wherein the at least two active strip regions and the isolation structure extend along a first direction, the gate stack extends along a second direction, and the first direction is different from the second direction (see e.g. Fig. 1, wherein 106a and 106b extend along a direction, and the gates 109 extend along a direction perpendicular to the direction).
21. The semiconductor device of claim 1, wherein the high-x dielectric layer comprises HfO2, ZrO2, HfAlOx, HfSiOx, Y2O3, Al2O3, or a combination thereof (see e.g. para 35, wherein it may be e.g. an oxide of either hafnium or aluminum).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin.
Re claim 4, Lin teaches claim 1, as discussed above, and further teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention:
a pair of gate spacers (comprising one or more of e.g. 113, 119, 131, see e.g. Fig. 11C) overlying opposite sidewalls of the gate stack,
wherein a width of the high-k dielectric layer in an extending direction of the isolation structure is less than a width of outer sidewalls of the pair of gate spacers in the extending direction of the isolation structure (see e.g. Fig. 11C; see e.g. para 53, wherein W2 is 1-4 nm, see e.g. para 35 wherein the width of 122 is smaller, such as 15-25 Angstroms).
Applicant has not disclosed that the claimed size is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical. It has been found that mere changes in the size of an object, lacking any convincing proof of criticality or unobviousness thereof, is not sufficient for patentability. See e.g. MPEP 2144.04; in re Rose, F.3d 459, 105 USPQ 237 (CCPA 1955); in re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984);
To overcome a prima facie case of obviousness, Applicant must show factual evidence that the particular range is critical or achieves unexpected results relative to the prior art range. See e.g. MPEP 716.02(b); In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of US 2020/0365467 A1 (“Cheng”).
Re claim 7, Lin teaches claim 1, but does not explicitly teach wherein each active fin structure comprises a plurality of semiconductor nanosheets vertically stacked with each other, and the gate stack wraps the plurality of semiconductor nanosheets.
Cheng teaches and/or would have suggested as obvious to one of ordinary skill in the art at the time of invention, in combination with Lin wherein each active fin structure comprises a plurality of semiconductor nanosheets vertically stacked with each other, and the gate stack wraps the plurality of semiconductor nanosheets (see e.g. para 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the invention of Cheng to the invention of Lin. The motivation to do so is that the combination produces the predictable results of using a nanosheet geometry instead of a FinFET geometry, which is known in the art to provide better performance, due to e.g. better control of channel current flow (see e.g. para 2).
Allowable Subject Matter
Claim(s) 22 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 22, including: wherein the source/drain contact plugs interface with a top surface of the lower dielectric layer.
The other claims each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim(s) 16, 18-20, and 23 is/are allowed. The following is an examiner’s statement of reasons for allowance: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claim 16, including:
an isolation structure comprising a main body portion and a protrusion portion disposed on the main body portion, wherein the protrusion portion has a dielectric constant greater than a dielectric constant of the main body portion;
wherein a top surface of the protrusion portion is lower than a top surface of the gate stack; and
a contact plug disposed aside the gate stack and contacting the main body portion of the isolation structure, wherein the contact plug interfaces with a top surface of the main body portion.
The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments with respect to the pending claims have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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