DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/23/26 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on 1/23/26. Claims 1 and 27 have been amended. No claims have been added or canceled. Currently, claims 1-2, 5-10, and 21-32 pending.
Response to Arguments
Applicant’s arguments filed 1/23/26 have been fully considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In the Final Rejection mailed on November 12, 2025, claims 21-26 were indicated as allowable subject matter. However, in view of the new art of record, claims 21-26 are no longer indicated as allowable subject matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 108735710 A, citations made herein refer to the attached English Machine Translation, hereinafter “Feng I”) in view of Feng (CN 109786359 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on November 11, 2025, hereinafter “Feng II”).
Regarding claim 1, Feng I teaches a method, comprising:
receiving a workpiece (Fig. 5, [0034]) comprising:
a gate structure (210, Fig. 5, [0057]),
a source/drain feature (231, see Fig. 4, [0091]) adjacent the gate structure (210) (see Fig. 4),
a first contact feature (241, [0090], Fig. 5) disposed over the gate structure (210) (see Fig. 5),
a second contact feature (242, Fig. 5) disposed over the source/drain feature (231) ([0091]), and
a dielectric layer (220, [0101], Fig. 5) disposed between the first contact feature (241) and the second contact feature (242) ([0101]),
after receiving the workpiece, applying a programming voltage across the first contact feature (241) and the second contact feature (242) to break down the dielectric layer (220) between the first contact feature and the second contact feature ([0030], [0101]),
wherein the programming voltage is equal to or greater than the breakdown voltage of the dielectric layer (220) but is smaller than the breakdown voltage of the gate dielectric layer ([0057]) ([0101], the interlayer dielectric layer 220 is stated to break down, but not the gate dielectric layer, which means the programming voltage is enough to break down the dielectric layer 220, but not the gate dielectric layer).
Feng I does not teach after receiving the workpiece, reducing a breakdown voltage of the dielectric layer such that the breakdown voltage of the dielectric layer is smaller than a breakdown voltage of a gate dielectric layer in the gate structure.
In a similar field of endeavor, Feng II teaches after receiving the workpiece ([0016] and [0020]), reducing a breakdown voltage of the dielectric layer (labelled as 740 in Fig. 7, labelled as 1040 in Fig. 10, [0016], [0020], [0068], [0090]) without reducing the breakdown voltage of a gate dielectric layer in the gate structure (labelled as 855 in Fig. 8, [0075], [0101]) ([0024], [0068]-[0069], [0076], [0097]; the breakdown voltage of the interlayer dielectric layer is reduced by adding conductive plug 732/832 to the workpiece because it reduces the effective thickness from S2 to L3 of the interlayer dielectric layer 740 in Fig. 7), for the purpose of “increasing the breakdown efficiency at the same breakdown voltage, thereby improving the programming efficiency of the antifuse structure” ([0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I with the reducing the breakdown voltage of the dielectric layer of Feng II, for the purpose of increasing the breakdown efficiency at the same breakdown voltage, thereby improving the programming efficiency of the antifuse structure ([0024]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 108735710 A, citations made herein refer to the attached English Machine Translation, hereinafter “Feng I”) in view of Feng (CN 109786359 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on November 11, 2025, hereinafter “Feng II”), and further in view of Feng et al. (CN 104347589 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on 5/27/2025, hereinafter “Feng III”).
Regarding claim 2, Feng I in view of Feng II teaches the limitations of claim 1. Feng I in view of Feng II does not explicitly teach that the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass.
In a similar field of endeavor, Feng III teaches that the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG) ([0074]; USG, BPSG, PSG), for the purpose of “making the programming voltage controllable and more convenient” ([0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II with the dielectric material of Feng III, for the purpose of “making the programming voltage controllable and more convenient” ([0031]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 108735710 A, citations made herein refer to the attached English Machine Translation, hereinafter “Feng I”) in view of Feng (CN 109786359 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on November 11, 2025, hereinafter “Feng II”), and further in view of Chao et al. (US 20190304989) and Feng (US 20200020630, hereinafter “Feng IV”).
Regarding claim 5, Feng I in view of Feng II teaches the limitations of claim 1. Feng I further teaches that the gate dielectric layer comprises a high-k dielectric material ([0060]).
Feng I in view of Feng II does not explicitly teach that the gate dielectric layer comprises hafnium oxide, and that the breakdown voltage of the gate dielectric layer is between about 4.5 volts and about 5.5 volts.
In a similar field of endeavor, Chao teaches that the gate dielectric layer comprises hafnium oxide ([0028]), in order to make an antifuse element that “may be safer compared to a fuse element including a copper interconnect” ([0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the gate dielectric layer of Feng I in view of Feng II with the the gate dielectric layer of Chao, in order to make an antifuse element that may be safer compared to a fuse element including a copper interconnect ([0013]).
Feng I in view of Feng II and Chao does not explicitly teach that the breakdown voltage of the gate dielectric layer is between about 4.5 volts and about 5.5 volts.
In a similar field of endeavor, Feng IV teaches that the breakdown voltage of the gate dielectric layer (211, Fig. 9, [0046], [0062]) is between 0.5 and 10 volts ([0062], [0067]-[0068]), in order to avoid breakdown of the gate dielectric layer before breakdown of the anti-fuse ([0046]).
However, Feng I in view of Feng II, Chao, and Feng IV does not explicitly teach that the breakdown voltage of the gate dielectric layer is between about 4.5 volts and about 5.5 volts. Nonetheless, the skilled artisan would know too that the breakdown voltage of the gate dielectric layer would impact programming voltage and a programming time of the anti-fuse (Feng IV, [0019]).
The specific claimed breakdown voltages, absent any criticality, is only considered to be the “optimum” voltages disclosed by Feng I in view of Feng II, Chao, and Feng IV that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired circuit reliability, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long the breakdown voltage of the gate dielectric layer being between about 4.5 volts and about 5.5 volts is used, as already suggested by Feng I in view of Feng II, Chao, and Feng IV.
Since the applicant has not established the criticality (see next paragraph) of the breakdown voltages stated and since these breakdown voltages are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Feng I in view of Feng II, Chao, and Feng IV.
Please note that the specification contains no disclosure of either the critical nature of the claimed voltages or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 6-7, 21, 27, 30, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 108735710 A, citations made herein refer to the attached English Machine Translation, hereinafter “Feng I”) in view of Feng (CN 109786359 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on November 11, 2025, hereinafter “Feng II”), and further in view of Xu et al. (CN 105006449 A, citations made herein refer to the attached English Machine Translation).
Regarding claim 6, Feng I in view of Feng II teaches the limitations of claim 1. Feng I in view of Feng II does not teach that the reducing of the breakdown voltage comprises performing an implantation process on the dielectric layer to introduce defects and impurities in the dielectric layer.
In a similar field of endeavor, Xu teaches that the reducing of the breakdown voltage comprises performing an implantation process on the dielectric layer (5, [0052]) to introduce defects and impurities in the dielectric layer ([0009], [0052]), for the purpose of “improving the consistency of the breakdown voltage of the antifuse dielectric layer” ([0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II with the ion implantation of the dielectric layer of Xu, for the purpose of “improving the consistency of the breakdown voltage of the antifuse dielectric layer” ([0009]).
Regarding claim 7, Feng I in view of Feng II and Xu teaches the limitations of claim 6. Xu further teaches that the implantation process implants a group 4A element ([0052], silicon).
Regarding claim 21, Feng I teaches a method, comprising:
providing a device structure (Fig. 5, [0034]) comprising:
a channel region ([0040], underneath gate structure 210),
a gate dielectric layer ([0057], 210 in Fig. 4 includes a gate dielectric layer) over the channel region,
a gate electrode over the gate dielectric layer ([0057]),
a gate contact (241, [0090], Fig. 5) over the gate electrode (in 210) (see Fig. 5),
a source/drain feature (231, see Fig. 4, [0091]) adjacent the channel region,
a source/drain contact (242, Fig. 5) over the source/drain feature (231) ([0091]), and
a dielectric layer (220, [0101], Fig. 5) between the gate contact (241) and the source/drain contact (242) ([0101]); and
after the providing of the device structure, applying a programming voltage to break down the dielectric layer (220) between the gate contact (241) and the source/drain contact (242) ([0030], [0101]) but not the gate dielectric layer ([0057]) ([0101], the interlayer dielectric layer 220 is stated to break down, but not the gate dielectric layer, which means the programming voltage is sufficient to break down the dielectric layer 220, but not the gate dielectric layer).
Feng I does not teach after the providing of the device structure, implanting a dopant into the dielectric layer such that a programming voltage is sufficient to break down the dielectric layer between the gate contact and the source/drain contact but is insufficient to break down the gate dielectric layer.
In a similar field of endeavor, Feng II teaches after the providing of the device structure ([0016] and [0020]), reducing a breakdown voltage of the dielectric layer (labelled as 740 in Fig. 7, labelled as 1040 in Fig. 10, [0016], [0020], [0068], [0090]), without reducing the breakdown voltage of a gate dielectric layer in the gate structure (labelled as 855 in Fig. 8, [0075], [0101]) ([0024], [0068]-[0069], [0076], [0097]; the breakdown voltage of the interlayer dielectric layer is reduced by adding conductive plug 732/832 to the workpiece because it reduces the effective thickness from S2 to L3 of the interlayer dielectric layer 740 in Fig. 7), such that a programming voltage is sufficient to break down the dielectric layer between the gate contact and the source/drain contact but is insufficient to break down the gate dielectric layer ([0024], the interlayer dielectric layer is stated to break down, but not a gate dielectric layer), for the purpose of “increasing the breakdown efficiency at the same breakdown voltage, thereby improving the programming efficiency of the antifuse structure” ([0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I with the reducing the breakdown voltage of the dielectric layer of Feng II, for the purpose of increasing the breakdown efficiency at the same breakdown voltage, thereby improving the programming efficiency of the antifuse structure ([0024]).
Feng I in view of Feng II does not teach that the breakdown voltage of the dielectric layer is lowered by performing an ion implantation process to the dielectric layer.
In a similar field of endeavor, Xu teaches that the breakdown voltage of the dielectric layer (5, [0052]) is lowered by performing an ion implantation process to the dielectric layer ([0009], [0052]), for the purpose of “improving the consistency of the breakdown voltage of the antifuse dielectric layer” ([0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II with the ion implantation of the dielectric layer of Xu, for the purpose of “improving the consistency of the breakdown voltage of the antifuse dielectric layer” ([0009]).
Regarding claim 27, Feng I teaches a method, comprising:
providing a device structure (Fig. 5, [0034]) comprising:
an active region comprising a channel region ([0040], underneath gate structure 210) and a source/drain region (area filled by 231, see Fig. 4, [0091]) adjacent the channel region (see Fig. 4),
a gate dielectric layer over the channel region, a gate electrode over the gate dielectric layer ([0057], 210 in Fig. 4 includes both),
a gate contact (241, [0090], Fig. 5) over the gate electrode (in 210) (see Fig. 5),
a source/drain feature (231, see Fig. 4, [0091]) over the source/drain region (area filled by 231) (Fig. 4),
a source/drain contact (242, Fig. 5) over the source/drain feature (231) ([0091]), and
a dielectric layer (220, [0101], Fig. 5) between the gate contact (241) and the source/drain contact (242) ([0101]),
after the providing of the device structure, applying a programming voltage to break down the dielectric layer (220) between the gate contact (241) and the source/drain contact (242) ([0030], [0101]),
wherein the programming voltage is smaller than the breakdown voltage of the gate dielectric layer ([0101], the interlayer dielectric layer 220 is stated to break down, but not the gate dielectric layer, which means the programming voltage is smaller than the breakdown voltage of the gate dielectric layer).
Feng I does not teach after the providing of the device structure, performing an ion implantation process to the dielectric layer to lower a breakdown voltage of the dielectric layer such that the breakdown voltage of the dielectric layer is smaller than a breakdown voltage of the gate dielectric layer; and
that applying the programming voltage to break down the dielectric layer between the gate contact and the source/drain contact is after the performing of the ion implantation process,
wherein the ion implantation process implants germanium, tin, xenon, or argon.
In a similar field of endeavor, Feng II teaches after the providing of the device structure, reducing a breakdown voltage of the dielectric layer (labelled as 740 in Fig. 7, labelled as 1040 in Fig. 10, [0016], [0020], [0068], [0090]) without reducing the breakdown voltage of a gate dielectric layer in the gate structure (labelled as 855 in Fig. 8, [0075], [0101]) ([0024], [0068]-[0069], [0076], [0097]; the breakdown voltage of the interlayer dielectric layer is reduced by adding conductive plug 732/832 to the workpiece because it reduces the effective thickness from S2 to L3 of the interlayer dielectric layer 740 in Fig. 7), for the purpose of “increasing the breakdown efficiency at the same breakdown voltage, thereby improving the programming efficiency of the antifuse structure” ([0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I with the reducing the breakdown voltage of the dielectric layer of Feng II, for the purpose of increasing the breakdown efficiency at the same breakdown voltage, thereby improving the programming efficiency of the antifuse structure ([0024]).
Feng I in view of Feng II does not teach that the breakdown voltage of the dielectric layer is lowered by performing an ion implantation process to the dielectric layer, and
that applying the programming voltage to break down the dielectric layer between the gate contact and the source/drain contact is after the performing of the ion implantation process,
wherein the ion implantation process implants germanium, tin, xenon, or argon.
In a similar field of endeavor, Xu teaches that the breakdown voltage of the dielectric layer (5, [0052]) is lowered by performing an ion implantation process to the dielectric layer ([0009], [0052]),
that applying the programming voltage to break down the dielectric layer (5) is after the performing of the ion implantation process ([0057]),
wherein the ion implantation process implants germanium, tin, xenon, or argon ([0052], argon),
for the purpose of “improving the consistency of the breakdown voltage of the antifuse dielectric layer” ([0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II with the ion implantation of the dielectric layer of Xu, for the purpose of “improving the consistency of the breakdown voltage of the antifuse dielectric layer” ([0009]).
Regarding claim 30, Feng I in view of Feng II and Xu teaches the limitations of claim 27. Feng II further teaches that a minimum distance between the gate contact and the source/drain contact is about 20 nm ([0071]).
However, Feng I in view of Feng II and Xu does not explicitly teach that a minimum distance between the gate contact and the source/drain contact is between about 5 nm and about 10 nm. Nonetheless, the skilled artisan would know too that the distance between the gate contact and source/drain contact impacts the breakdown voltage (Feng II, [0069]).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Feng I in view of Feng II and Xu that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired breakdown voltage, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long the minimum distance being between 5 nm and about 10 nm is used, as already suggested by Feng I in view of Feng II and Xu.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Feng I in view of Feng II and Xu.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 32, Feng I in view of Feng II teaches the limitations of claim 1. Feng II further teaches that a minimum distance between the gate contact and the source/drain contact is about 20 nm ([0071]).
Feng I in view of Feng II does not explicitly teach that a minimum distance between the first contact feature and the second contact feature is greater than a thickness of the gate dielectric layer.
In a similar field of endeavor, Wang teaches that the thickness of the gate dielectric layer (107, [0026]) is about 1 nm to 5 nm ([0026]), in order to increase packing density of the devices ([0002]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the gate dielectric layer thickness of Feng I in view of Feng II with the gate dielectric layer thickness of Wang so that a minimum distance between the gate contact and the source/drain contact is greater than a thickness of the gate dielectric layer, in order to increase packing density of the devices ([0002]).
Claims 8-10, 22-23, 25, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 108735710 A, citations made herein refer to the attached English Machine Translation, hereinafter “Feng I”) in view of Feng (CN 109786359 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on November 11, 2025, hereinafter “Feng II”) and Xu et al. (CN 105006449 A, citations made herein refer to the attached English Machine Translation), and further in view of Wang et al. (US 20170110577).
Regarding claim 8, Feng I in view of Feng II and Xu teaches the limitations of claim 6. Feng I in view of Feng II and Xu does not teach that the implantation process implants germanium (Ge) or tin (Sn).
In a similar field of endeavor, Wang teaches that the implantation process implants germanium (Ge) or tin (Sn) ([0049], Ge), in order to not “degrade the dielectric properties of ILD layers” ([0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II and Xu with the doping element of Wang, in order to not degrade the dielectric properties of the dielectric layer ([0049]).
Regarding claim 9, Feng I in view of Feng II, Xu, and Wang teaches the limitations of claim 8. Wang further teaches that the implantation process comprises an implantation dose between about 2x1014 atoms/cm2 and about 2x1015 atoms/cm2.
However, Feng I in view of Feng II, Xu, and Wang does not explicitly teach that the implantation process comprises an implantation dose between about 5x1014 atoms/cm2 and about 1x1015 atoms/cm2. Nonetheless, the skilled artisan would know too that the implantation dose would impact breakdown voltage (Xu, [0052], [0057]).
The specific claimed implantation doses, absent any criticality, is only considered to be the “optimum” voltages disclosed by Feng I in view of Feng II, Xu, and Wang that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired breakdown voltage, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long an implantation dose between about 5x1014 atoms/cm2 and about 1x1015 atoms/cm2 is used, as already suggested by Feng I in view of Feng II, Xu, and Wang.
Since the applicant has not established the criticality (see next paragraph) of the doses stated and since these doses are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Feng I in view of Feng II, Xu, and Wang.
Please note that the specification contains no disclosure of either the critical nature of the claimed voltages or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 10, Feng I in view of Feng II, Xu, and Wang teaches the limitations of claim 8. Wang further teaches that the implantation process comprises an ion implantation energy between about 20 keV and about 50 keV ([0049]).
However, Feng I in view of Feng II, Xu, and Wang does not explicitly teach that the implantation process comprises an ion implantation energy between about 5 keV and about 30 keV. Nonetheless, the skilled artisan would know too that ion implantation energy impacts breakdown voltage (Xu, [0052], [0057]).
The specific claimed ion implantation energies, absent any criticality, is only considered to be the “optimum” ion implantation energies disclosed by Feng I in view of Feng II, Xu, and Wang that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired breakdown voltage, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long an ion implantation energy between about 5 keV and about 30 keV. is used, as already suggested by Feng I in view of Feng II, Xu, and Wang.
Since the applicant has not established the criticality (see next paragraph) of the ion implantation energies stated and since these ion implantation energies are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Feng I in view of Feng II, Xu, and Wang.
Please note that the specification contains no disclosure of either the critical nature of the claimed lengths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 22, Feng I in view of Feng II and Xu teaches the limitations of claim 21. Feng II further teaches that a minimum distance between the gate contact and the source/drain contact is about 20 nm ([0071]).
Feng I in view of Feng II and Xu does not explicitly teach that a minimum distance between the gate contact and the source/drain contact is greater than a thickness of the gate dielectric layer.
In a similar field of endeavor, Wang teaches that the thickness of the gate dielectric layer (107, [0026]) is about 1 nm to 5 nm ([0026]), in order to increase packing density of the devices ([0002]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the gate dielectric layer thickness of Feng I in view of Feng II and Xu with the gate dielectric layer thickness of Wang so that a minimum distance between the gate contact and the source/drain contact is greater than a thickness of the gate dielectric layer, in order to increase packing density of the devices ([0002]).
Regarding claim 23, Feng I in view of Feng II, Xu, and Wang teaches the limitations of claim 22. Feng II further teaches that a minimum distance between the gate contact and the source/drain contact is about 20 nm ([0071]).
Wang teaches that the thickness of the gate dielectric layer (107, [0026]) is about 1 nm to 5 nm ([0026]).
However, Feng I in view of Feng II, Xu, and Wang does not explicitly teach that the minimum distance is between about 5 nm and about 10 nm and that the thickness is between about 1 nm and about 3 nm. Nonetheless, the skilled artisan would know too that the distance between the gate contact and source/drain contact and the thickness of the gate dielectric layer impacts the breakdown voltage (Feng II, [0069]).
The specific claimed distances, absent any criticality, is only considered to be the “optimum” distances disclosed by Feng I in view of Feng II, Xu, and Wang that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired breakdown voltage, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long the minimum distance being between about 5 nm and about 10 nm and the thickness being between about 1 nm and about 3 nm are used, as already suggested by Feng I in view of Feng II, Xu, and Wang.
Since the applicant has not established the criticality (see next paragraph) of the distances stated and since these distances are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Feng I in view of Feng II, Xu, and Wang.
Please note that the specification contains no disclosure of either the critical nature of the claimed distances or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 25, Feng I in view of Feng II and Xu teaches the limitations of claim 21. Feng I in view of Feng II and Xu does not teach that the dopant comprises germanium (Ge) or tin (Sn).
In a similar field of endeavor, Wang teaches that the dopant comprises germanium (Ge) or tin (Sn) ([0049], Ge), in order to not “degrade the dielectric properties of ILD layers” ([0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II and Xu with the doping element of Wang, in order to not degrade the dielectric properties of the dielectric layer ([0049]).
Regarding claim 28, Feng I in view of Feng II and Xu teaches the limitations of claim 27. Xu further teaches that the ion implanting process comprises an ion implantation energy between about 30 keV and about 80 keV ([0052]).
Feng I in view of Feng II and Xu does not teach that the ion implanting process comprises an ion implantation energy between about 5 keV and about 30 keV.
In a similar field of endeavor, Wang teaches that the implantation process comprises an ion implantation energy between about 20 keV and about 50 keV ([0049]), in order to “control the maximum penetration depth of the dopant atoms” ([0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II and Xu with the ion implantation energy of Wang, in order to “control the maximum penetration depth of the dopant atoms” ([0049]).
However, Feng I in view of Feng II, Xu, and Wang does not explicitly teach that the implantation process comprises an ion implantation energy between about 5 keV and about 30 keV. Nonetheless, the skilled artisan would know too that ion implantation energy impacts breakdown voltage (Xu, [0052], [0059]).
The specific claimed ion implantation energies, absent any criticality, is only considered to be the “optimum” ion implantation energies disclosed by Feng I in view of Feng II, Xu, and Wang that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired breakdown voltage, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long an ion implantation energy between about 5 keV and about 30 keV. is used, as already suggested by Feng I in view of Feng II, Xu, and Wang.
Since the applicant has not established the criticality (see next paragraph) of the ion implantation energies stated and since these ion implantation energies are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Feng I in view of Feng II, Xu, and Wang.
Please note that the specification contains no disclosure of either the critical nature of the claimed lengths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 108735710 A, citations made herein refer to the attached English Machine Translation, hereinafter “Feng I”) in view of Feng (CN 109786359 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on November 11, 2025, hereinafter “Feng II”) and Xu et al. (CN 105006449 A, citations made herein refer to the attached English Machine Translation), and Chao et al. (US 20190304989), and further in view of Feng et al. (CN 104347589 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on 5/27/2025, hereinafter “Feng III”).
Regarding claim 24, Feng I in view of Feng II and Xu teaches the limitations of claim 21. Feng I further teaches that the gate dielectric layer comprises a high-k dielectric material ([0060]).
Feng I in view of Feng II and Xu does not explicitly teach that the gate dielectric layer comprises hafnium oxide, wherein the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG).
In a similar field of endeavor, Chao teaches that the gate dielectric layer comprises hafnium oxide ([0028]), in order to make an antifuse element that “may be safer compared to a fuse element including a copper interconnect” ([0013]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the gate dielectric layer of Feng I in view of Feng II with the the gate dielectric layer of Chao, in order to make an antifuse element that may be safer compared to a fuse element including a copper interconnect ([0013]).
Feng I in view of Feng II, Xu, and Chao does not explicitly teach that the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG).
In a similar field of endeavor, Feng III teaches that the dielectric layer comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass (USG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), or boron doped silicon glass (BSG) ([0074]; USG, BPSG, PSG), for the purpose of “making the programming voltage controllable and more convenient” ([0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II, Xu, and Chao with the dielectric material of Feng III, for the purpose of “making the programming voltage controllable and more convenient” ([0031]).
Claims 26 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 108735710 A, citations made herein refer to the attached English Machine Translation, hereinafter “Feng I”) in view of Feng (CN 109786359 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on November 11, 2025, hereinafter “Feng II”) and Xu et al. (CN 105006449 A, citations made herein refer to the attached English Machine Translation), and further in view of Chao et al. (US 20190304989).
Regarding claim 26, Feng I in view of Feng II and Xu teaches the limitations of claim 21. Feng I in view of Feng II and Xu does not explicitly teach that the programming voltage is between about 2 volts and about 3 volts.
In a similar field of endeavor, Chao teaches that the programming voltage is less than or equal to 2.5 volts, in order to be high enough to break down the dielectric layer while being low enough to reduce power consumption ([0040]-[0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II and Xu with the programming voltage of Chao, in order to be high enough to break down the dielectric layer while being low enough to reduce power consumption ([0040]-[0042]).
Regarding claim 29, Feng I in view of Feng II and Xu teaches the limitations of claim 27. Feng I in view of Feng II and Xu does not explicitly teach that the programming voltage is between about 2 volts and about 3 volts.
In a similar field of endeavor, Chao teaches that the programming voltage is less than or equal to 2.5 volts, in order to be high enough to break down the dielectric layer while being low enough to reduce power consumption ([0040]-[0042]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II and Xu with the programming voltage of Chao, in order to be high enough to break down the dielectric layer while being low enough to reduce power consumption ([0040]-[0042]).
Claim 31 is rejected under 35 U.S.C. 103 as being unpatentable over Feng et al. (CN 108735710 A, citations made herein refer to the attached English Machine Translation, hereinafter “Feng I”) in view of Feng (CN 109786359 A, citations made herein refer to the English Machine Translation attached to the Office Action mailed on November 11, 2025, hereinafter “Feng II”), and further in view of Feng (US 20200020630, hereinafter “Feng IV”).
Regarding claim 31, Feng I in view of Feng II teaches the limitations of claim 1. Feng I in view of Feng II does not teach that the workpiece further comprises: a gate spacer disposed along a sidewall of the gate structure; and a contact etch stop layer over the source/drain feature, wherein the second contact feature is spaced apart from the gate spacer by the contact etch stop layer.
In a similar field of endeavor, Feng IV teaches, in Fig. 9, that the workpiece further comprises: a gate spacer (241, [0040]) disposed along a sidewall of the gate structure (210, [0040]); and a contact etch stop layer (231, [0037], Fig. 6 shows 231 configured as a contact etch stop layer) over the source/drain feature (250, [0040]), wherein the second contact feature (270, [0058]) is spaced apart from the gate spacer (241) by the contact etch stop layer (231) (see Fig. 9), in order to protect the gate and source/drain features during manufacturing the workpiece (see [0039]-[0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the method of Feng I in view of Feng II with the gate spacer and contact etch stop layer of Feng IV, in order to protect the gate and source/drain features during manufacturing the workpiece (see [0039]-[0040]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Feng (CN 110310942 A) teaches receiving a workpiece and applying a programming voltage to the workpiece similar to claim 1.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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