Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants Election without traverse of Group I, Species E, relating to claims 1-3, 5-9, 11-13, 21-27 in the reply filed on 5/14/2025 is acknowledged. Claims 4, 10 have been withdrawn because they are drawn to a nonelected invention.
Claim Objections
Claims 8 and 11-12 are objected to because of the following informalities:
Regarding claim 8, on line 5 the phrase "metal gate structure" is still present, this should be changed to "gate structure" to sync with other instances of the same limitation.
Regarding claim 11, on lines 2 and 3 the phrase "metal gate structure" is still present, this should be changed to "gate structure" to sync with other instances of the same limitation.
Regarding claim 12, on line 2 the phrase "metal gate structure" is still present, this should be changed to "gate structure" to sync with other instances of the same limitation.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5, 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier (US20230060619A1) in view of Wang et al. (US-20210091179-A1 referred as Wang).
Regarding claim 1. Frougier discloses a semiconductor structure, comprising:
a substrate ([0115], figure 33, the substrate #2210);
a plurality of semiconductor layers disposed over the substrate ([0117] [0119], figure 33 further viewed in figure 23, a plurality of semiconductor layers #2230 are disposed over the substrate #2210);
a gate structure disposed on and wrapping each of the semiconductor layers ([0132], figure 33, the gate structure #2810 is wrapped around each of the semiconductor layers #2230), wherein the gate structure includes a gate dielectric and a metal gate electrode ([0132], figure 28, the gate structure #2810 includes gate dielectric and metal gate electrodes as described);
a source/drain feature disposed over the substrate and adjacent the gate structure ([0135], figure 33, the source/drain feature #2610 is disposed over the substrate #2210 and adjacent to the gate structure #2810); and
a dielectric layer disposed between a bottommost surface of the gate structure and the substrate ([0137], figure 31, a dielectric layer #3110 disposed in between the bottommost surface of the gate structure #2810 and the substrate #3110).
Frougier lacks wherein the dielectric layer extends from an interface with the gate dielectric layer of the gate structure to an interface with the source/drain feature.
Wang discloses wherein the dielectric layer extends from an interface with the gate dielectric layer of the gate structure to an interface with the source/drain feature ([0045], figure 21a, wherein the dielectric layer #234 extends from an interface with the gate dielectric layer #262 of the gate structure #258 to an interface with the source/drain feature #240).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier to include proximate locations for the dielectric layer, gate structure, and s/d feature by their interfaces as taught by Wang in order to reduce latency, enhance device compactness, reduce overall use of material in manufacturing.
Regarding claim 3. Frougier as modified discloses the semiconductor structure of claim 1, wherein the dielectric layer includes a seam embedded therein ([0137], figure 33, the dielectric layer #3110 includes a seam #3310 embedded within).
Regarding claim 5. Frougier as modified discloses the semiconductor structure of claim 1, wherein the dielectric layer includes a tapered top surface extending downward and away from the source/drain feature in a cross-sectional view ([0137], figure 33, the dielectric layer #3110 includes a tapered top surface with portions extending downwards and away from the source/drain feature #2610 (specifically in parts where the interface is declined from the high indents into the stacked structure)).
Regarding claim 6. Frougier as modified discloses the semiconductor structure of claim 5, wherein the dielectric layer includes a seam embedded therein, and wherein the seam is tapered and extends from an interface with the source/drain feature ([0137], figure 33, the dielectric layer #3110 includes a seam #3310 which is tapered and is seen extending from an interface with the source/drain feature #2610 (as seen from the closest proximity from the seam #3310 to the s/d feature #2610 as the seam #3310 extends away). Please note if intending to overcome reference, the limitation must read having a physical contact from both elements).
Regarding claim 7. Frougier as modified discloses the semiconductor structure of claim 1, further comprising an inner spacer between the gate structure and the source/drain feature, wherein the inner spacer and the dielectric layer have the same composition ([0126, 0110], figure 25, the spacers #2510 placed in between the gate structure #2810 and source/drain feature #2610 has the same SiO2 composition as the dielectric layer #3110).
Claims 21-23, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier (US 20230060619 A1), in view of Chung et al. (US-20220165871-A1) and Jun et al. (US-20210242091-A1 referred as Jun #2).
Regarding claim 21. Froungier discloses a semiconductor structure, comprising: a stacked structure including a plurality of vertically arranged channel layers; a gate structure including a metal layer and a high-k dielectric layer, wherein the gate structure interleaves the plurality of vertically arranged channel layers in a cross-sectional view ([0132], figure 33, the stacked structure includes the gate structures #2810 interleaved by channel layers #2230. And additionally the gate structure #2810 includes high-k dielectric and at least one metal within as described and surrounding each of the plurality of vertically arranged channel layers #2230);
an isolation feature including a first layer and a second layer over the first layer ([0135-0136], figure 31, the isolation feature includes multiple layers such as first layer #2310 and second layer #3110. Its also noted that the second layer is over the first layer), wherein the isolation feature is disposed below the stacked structure ([0135], figure 31, the isolation feature #2310 and #3110 is disposed below the stacked structure);
a source/drain feature disposed adjacent and interfacing the stacked structure and the second layer of the isolation feature ([0135], figure 33, the source/drain feature #2610 is adjacent to the stacked structure and the second layer #2310. The stacked structure includes gate structures #2810 and channel layers #2230).
Froungier lacks a bottommost surface of the high-k dielectric layer of the gate structure contacts the isolation feature; and wherein the isolation feature includes a seam that contacts the source/drain feature.
Chung discloses a bottommost surface of the high-k dielectric layer of the gate structure contacts the isolation feature ([0038, 0045], figure 1a, a bottommost surface of the high-k dielectric layer of the gate structure #108 contacts the isolation feature #102. It is described that element #108 contains high k dielectric material).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier to have the gate structure high k dielectric layer having direct contact to the isolation feature as taught by Chung in order to create a more compact semiconductor structure with a greater device lifespan.
Frougier as modified by Lin still lacks wherein the isolation feature further includes a seam that contacts the source/drain feature.
Jun #2 discloses wherein the isolation feature further includes a seam that contacts the source/drain feature ([0064], figure 33, the isolation feature #46/48/42 further includes a seam #64 that contacts the source/drain feature #78 as illustrated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified by Lin to have the isolation feature further includes a seam that contacts the source/drain feature as taught by Jun #2 in order provide additional electrical safety, reduce weight, and distribute the weight across the device.
Regarding claim 22. Frougier as modified lacks wherein the isolation feature further includes a seam provides an air gap extending downward in a slanted direction away from the source/drain feature in the cross-sectional view.
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Annotated Close up of Figure 33
Jun #2 discloses wherein the isolation feature further includes a seam provides an air gap extending downward in a slanted direction away from the source/drain feature in the cross-sectional view ([0064], annotated close up of figure 33 close up seen above, the isolation feature #46/48/42 includes a seam #64 in contact with the source/drain feature #78 at contact #SLT. It is seen that the contact #SLT is in a slanted direction away from the source/drain feature #78).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified to have the isolation feature further includes a seam provides an air gap extending downward in a slanted direction away from the source/drain feature as taught by Jun #2 in order provide additional electrical safety, reduce weight, and distribute the weight across the device.
Regarding claim 23. Frougier as modified discloses wherein an entirety of the seam is disposed below the first layer and the second layer of the isolation feature, wherein the seam lacks an interface with the first layer ([0137], figure 33, there’s a portion of which the entirety of the seam #3310 is disposed below the first layer #2310 and second layer #3110 of the isolation feature with the seam lacking an interface with the first layer).
Regarding claim 25. Frougier as modified discloses wherein the first layer and the second layer contiguously extend from under the gate structure to between the gate structure and the source/drain feature ([0135], figure 31, the sidewall of the source/drain feature #2610 interfaces the isolation feature #2310 and #3110).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Frougier (US 20230060619 A1), Chung et al. (US-20220165871-A1) and Jun et al. (US-20210242091-A1 referred as Jun #2) in further view of Yegnashankaran (US-7042092-B1 referred as Yegnashankaran).
Regarding claim 27. Frougier as modified lacks wherein the isolation feature includes a third layer and a fourth layer below the seam disposed under the first layer and the second layer, wherein the third layer is comprised of the first material and the fourth layer is comprised of the second material.
Yegnashankaran discloses wherein the isolation feature includes a third layer and a fourth layer below the seam disposed under the first layer and the second layer ([col 1 lines 22-43], figure 2, the isolations feature includes multiple layers and a seam #210. The third layer #112 and the fourth layer #120 are disposed below the seam #210, first layer #140 and second layer #130), wherein the third layer is comprised of the first material and the fourth layer is comprised of the second material ([col 2 lines 0-15], figure 2, all the layers of the isolation feature includes SiO2 or any dielectric materials commonly used in the art).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified to have the isolation feature layers be positioned in order as taught by Yegnashankaran in order to enhance the manufacturing speed, increase the device integrity and to provide additional electrical isolation.
Regarding claim 26. Frougier as modified lacks wherein a sidewall of the source/drain feature interfaces the third layer.
Yegnashankaran discloses wherein a sidewall of the source/drain feature interfaces the third layer ([col 1 lines 30-35], figure 2, a sidewall of the source/drain feature #114 (as described the contact #114 leads to the source/drain feature of the device) interfaces the third layer #112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified to have wherein a sidewall of the source/drain feature interfaces the third layer as taught by Yegnashankaran in order to provide additional electrical protection, reduce future device failure, and to reduce short circuits within the device.
Allowable Subject Matter
Claims 8-9 and 11-13 are allowed (note claim 8 has a minor formality objection above, but would be considered allowable when corrected).
Regarding claim 8, the prior art does not teach or render obvious an isolation feature disposed below the stacked structure, wherein a bottommost portion of the gate structure includes a bottommost surface and a second surface opposing the bottommost surface, the bottommost surface comprised of the high-k gate dielectric layer, wherein the second surface engages a first channel layer of the channel layers; and a source/drain feature disposed adjacent the stacked structure; wherein the bottommost surface of the gate structure comprised of the high-k dielectric layer interfaces the isolation feature and the bottommost surface of the gate structure comprised of the high-k dielectric layer is slanted downward and away from the source/drain feature and in the combination as claimed.
Claims 9 and 11-13 include all the limitations of claim 8, therefore, are also allowable (though are officially 'objected' because they depend on claim 8).
Claim 28 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 05/07/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features are disclosed by the prior art by new prior art except for claim 8 and its respective dependent claims. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
As to claim 1 - Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Frougeir et al. in combination with newly cited reference to Wang et al. has been presented with regard to claim 1.
Furthermore, the applicant argues over the use of Changs et al. reference when it comes to mapping the gate dielectric layer #208 as a dielectric layer in the limitation of claim 1. Regardless of the material or the location of the layer #208, they are both still dielectric with purpose to insulate electricity therefore still valid to be used. Regardless, Changs et al. reference is no longer used in claim 1, therefore the argument is moot.
As to claim 8 - Applicant's amendments and arguments were persuasive. Upon further search and consideration, the claim is placed as allowable subject matter.
Furthermore, the applicant argues about the use of Juns et al. reference when it comes to rotating figure 12B since the rotation would create a new perspective of what is considered declined or inclined slopes. It is allowed in examination to rotated figures unless a clear reference point is used (such as a limitation describing directions or specified interfaces of elements such as bottommost/topmost). Regardless, claim 8 is placed in allowable subject matter therefore the argument is moot.
As to claim 21 - Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Frougeir et al. in combination with previously introduced reference to Chung et al. with further combination to Jun #2 et al. has been presented with regard to claim 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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