Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/02/2026 has been entered.
Election/Restrictions
Applicants Election without traverse of Group I, Species E, relating to claims 1-3, 5-9, 11-13, 21-27 in the reply filed on 5/14/2025 is acknowledged. Claims 4, 10 have been withdrawn because they are drawn to a nonelected invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 8, on lines 7-8 of the claim the limitation “wherein each of the first surface and the second surface are provided by the high-k gate dielectric layer”, which is unclear of the specific scope intended by “are provided”. Provided generally means something that is given by an element – for example – ‘weather protection is provided by the roof of the house’ (or what the seam provides in claim 22). But it is unclear exactly what the meaning of this claim language is and the specification does not use this word in this context. Is the purpose of this to say that the first and second surfaces are specifically of the high K dielectric layer? Or just part of the overall structure that would include the high-k dielectric layer and thus be able ‘to provide’. It is suggested Applicant make clear exactly what is meant by this by defining structures relative to the other structures (i.e. “a first surface of the high-k gate dielectric layer”).
Claims 9-13 include all the limitations of claim 8, therefore, are rejected for the same reason described above.
These claims are rejected below as best understood.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier (US20230060619A1) in view of Chang et al. (US-20220173311-A1).
Regarding claim 1. Frougier discloses a semiconductor structure, comprising:
a substrate ([0115], figure 33, the substrate #2210);
a plurality of semiconductor layers disposed over the substrate ([0117] [0119], figure 33 further viewed in figure 23, a plurality of semiconductor layers #2230 are disposed over the substrate #2210);
a gate structure disposed on and wrapping each of the semiconductor layers ([0132], figure 33, the gate structure #2810 is wrapped around each of the semiconductor layers #2230), wherein the gate structure includes a gate dielectric and a metal gate electrode ([0132], figure 28, the gate structure #2810 includes gate dielectric and metal gate electrodes as described);
a source/drain feature disposed over the substrate and adjacent the gate structure ([0135], figure 33, the source/drain feature #2610 is disposed over the substrate #2210 and adjacent to the gate structure #2810); and
a dielectric layer disposed between a bottommost surface of the gate structure and the substrate ([0137], figure 31, a dielectric layer #3110 disposed in between the bottommost surface of the gate structure #2810 and the substrate #3110).
Frougier lacks wherein a bottommost portion of the dielectric layer is closer to the bottommost surface of the gate structure than a bottommost part of the source/drain feature.
Chang et al. discloses wherein a bottommost portion of the dielectric layer is closer to the bottommost surface of the gate structure than a bottommost part of the source/drain feature ([0035], figure 1B, the bottommost portion of the dielectric layer #208 is closer to the bottommost surface of the gate structure #206 than to the bottommost part of the source/drain feature #210).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier to include proximate locations for the bottommost surface of the dielectric layer, gate structure, and s/d feature as taught by Chang et al. in order to reduce latency, enhance device compactness, reduce overall use of material in manufacturing.
Regarding claim 2. Frougier as modified discloses the semiconductor structure of claim 1, wherein the dielectric layer includes a first portion disposed between the bottommost surface of the gate structure and the substrate and a second portion disposed between the source/drain feature and the substrate ([0132], figure 31, the dielectric layer #3110 includes a first portion disposed in between the gate structure #2810 and the substrate #2210 with a second portion disposed in between the source/drain feature #2610 and the substrate #2210).
Regarding claim 3. Frougier as modified discloses the semiconductor structure of claim 1, wherein the dielectric layer includes a seam embedded therein ([0137], figure 33, the dielectric layer #3110 includes a seam #3310 embedded within).
Regarding claim 5. Frougier as modified discloses the semiconductor structure of claim 1, wherein the dielectric layer includes a tapered top surface extending downward from the source/drain feature ([0137], figure 33, the dielectric layer #3110 includes a tapered top surface extending downwards due to the source/drain feature #2610).
Regarding claim 6. Frougier as modified discloses the semiconductor structure of claim 5, wherein the dielectric layer includes a seam embedded therein, and wherein the seam is tapered ([0137], figure 33, the dielectric layer #3110 includes a seam #3310 which is tapered).
Regarding claim 7. Frougier as modified discloses the semiconductor structure of claim 1, further comprising an inner spacer between the gate structure and the source/drain feature, wherein the inner spacer and the dielectric layer have the same composition ([0126, 0110], figure 25, the spacers #2510 placed in between the gate structure #2810 and source/drain feature #2610 has the same SiO2 composition as the dielectric layer #3110).
Claims 8 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. (US-20230060619-A1 referred as Frougier), in view of Chung et al. (US-20220165871-A1 referred as Chung) and Jun et al. (US-20220109047-A1 referred as Jun).
Regarding claim 8. Frougier discloses a semiconductor structure, comprising:
a stacked structure including channel layers interleaved with a metal gate structure ([0132], figure 31 further in viewed of figure 23, the stacked structure includes gate structures #2810 interleaved by channel structures #2230), wherein the metal gate structure includes a high-k gate dielectric layer and a metal layer ([0132], figure 28, the gate structure #2810 includes gate dielectric and metal gate electrodes as described);
an isolation feature disposed below the stacked structure ([0135], figure 31, the isolation feature #3110 disposed below the stacked structure); and
a source/drain feature disposed adjacent the stacked structure ([0135], figure 33, the source/drain feature defined as #2610 is seen adjacent to the stacked structure being the gate structures #2810 and channel layers #2230).
Froguier lacks an isolation feature, wherein a bottommost portion of the metal gate structure includes a first surface that shares an interface with the isolation feature and a second surface opposing the first surface, wherein the second surface engages a first channel layer of the channel layers, wherein each of the first surface and the second surface are provided by the high-k gate dielectric layer; and
wherein the first surface of the metal gate structure interfacing the isolation feature is slanted downward and away from the source/drain feature.
Chung discloses an isolation feature, wherein a bottommost portion of the metal gate structure includes a first surface that shares an interface with the isolation feature and a second surface opposing the first surface, wherein the second surface engages a first channel layer of the channel layers ([0038], figure 1a, an isolation feature #102, wherein the bottommost portion of the metal gate structure #104 includes first surface that shares an interface with the isolation feature #102. The second surface of the metal gate structure #104 opposing the first surface engages a first channel layer #110), wherein each of the first surface and the second surface are provided by the high-k gate dielectric layer ([0038, 0045], figure 1a, the first surface of the metal gate structure #104 is provided by the high-k dielectric layer contained within the isolation layer #102. And the second surface of the metal gate structure #104 is provided by the high-k dielectric layer within the element #108).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier to include placements for the metal gate structure, isolation feature, and the channel layer as taught by Chung in order to enhance device compactness, weight distribution and manufacturing speed.
Frougier as modified by Chung still lacks wherein the first surface of the metal gate structure interfacing the isolation feature is slanted downward and away from the source/drain feature.
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Rotated and Annotated Figure 12B
Jun discloses wherein the first surface of the metal gate structure interfacing the isolation feature is slanted downward and away from the source/drain feature ([0105], figure 12B Rotated and Annotated seen above, the first surface #1S of the metal gate structure #426 interfacing the isolation feature #472 is seen slanted and downwards and away from the source/drain feature #411).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified by Chung to include further modifying the metal gate structure to have a first surface which is slanted and away from the source/drain feature as taught by Chung in order to reduce device failure, increase the devices lifetime, and to reduce electrical noise.
Regarding claim 11. Frougier as modified lacks wherein the metal layer of the metal gate structure has a bottommost surface adjacent to the first surface that is slanted downward.
MPEP 2144.04 IV – describes Changes in shape - In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified to include further include a metal layer within the metal gate structure, as known in the art, to have a bottommost surface adjacent to the first surface of the metal gate structure in order to create a more compact device by using less manufacturing resources, provide additional structural integrity, and to enhance the signal strength in the metal gate structure.
Regarding claim 12. Frougier as modified discloses wherein the inner spacer disposed between the metal gate structure and the source/drain feature and the isolation feature have the same composition ([0132], figure 28, the inner spacer #2510 (seen in figure 25) are disposed in between the metal gate structure #2810 and the source/drain feature #2610. The spacer #2510 have the same composition as the isolation feature #3110).
Regarding claim 13. Frougier as modified discloses the semiconductor structure of claim 8, wherein the isolation feature encloses an air gap ([0137], figure 33, the isolation feature #3110 includes an air gap #3310 enclosed within).
Claims 9 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier (US 20230060619 A1), and Chung et al. (US-20220165871-A1) in further view of Lee et al. (US-20160307927-A1).
Regarding claim 9. Frougier as modified lacks a semiconductor structure of claim 8, wherein the source/drain feature extends through the isolation feature to contact a raised portion of the substrate.
Lee et al. discloses a semiconductor structure of claim 8, wherein the source/drain feature extends through the isolation feature to contact a raised portion of the substrate ([109], figure 37, the source/drain feature #240 extends through the isolation feature #120 to contact a raised portion #105b of the substrate #100).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified to include placements the source/drain feature going through the isolation feature to contact the substrate as taught by Lee et al. in order to increase connectivity with less movable parts for an enhanced device lifetime.
Claims 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier (US 20230060619 A1), in view of Lin et al. (US-20220293729-A1 referred as Lin) and Jun et al. (US-20210242091-A1 referred as Jun #2).
Regarding claim 21. Froungier discloses a semiconductor structure, comprising: a stacked structure including a plurality of vertically arranged channel layers interleaved with a gate structure in a cross-sectional view ([0132], figure 33, the stacked structure includes the gate structures #2810 interleaved by channel layers #2230), the gate structure comprising a high-k gate dielectric and at least one metal layer surrounding each of the plurality of vertically arranged channel layers ([0132], figure 28, the gate structure #2810 includes high-k dielectric and at least one metal within as described and surrounding each of the plurality of vertically arranged channel layers #2230);
an isolation feature including a first layer and a second layer over the first layer ([0135-0136], figure 31, the isolation feature includes multiple layers such as first layer #2310 and second layer #3110. Its also noted that the second layer is over the first layer), wherein the isolation feature is disposed below the stacked structure ([0135], figure 31, the isolation feature #2310 and #3110 is disposed below the stacked structure);
a source/drain feature disposed adjacent and interfacing the stacked structure ([0135], figure 33, the source/drain feature #2610 is adjacent to the stacked structure. The stacked structure includes gate structures #2810 and channel layers #2230); and
a dielectric spacer disposed between the gate structure and the source/drain feature in the cross-sectional view, wherein the dielectric spacer includes a first spacer layer and a second spacer layer ([0126], figure 28, the dielectric spacer includes the first spacer layer #2510 and the second spacer layer #2430 (seen in figure 25) disposed in between the gate structures #2810 and channel layers #2230), wherein the first layer and the first spacer layer comprise a first material layer and the second layer and the second spacer layer comprise a second material layer (figure 31, the first layer #2310 and first spacer layer #2510 are made of first material layer SiO2 (described at [0120][0126]) and the second layer #3110 and second spacer layer #2430 are made of second material layer SiBCN (described at [0135][0123])), Froungier lacks a bottom of the gate structure contacts the isolation feature; and wherein the isolation feature further includes a seam that contacts the source/drain feature.
Lin discloses a bottom of the gate structure contacts the isolation feature ([0079, 0081], figure 10a, the gate electrode #54 represents the gate structure and the shallow trench isolation portion #12a represents the isolation feature).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier to have the gate structure having direct contact to the isolation feature as taught by Lin in order to create a more compact semiconductor structure with a greater device lifespan.
Frougier as modified by Lin still lacks wherein the isolation feature further includes a seam that contacts the source/drain feature.
Jun #2 discloses wherein the isolation feature further includes a seam that contacts the source/drain feature ([0064], figure 33, the isolation feature #46/48/42 further includes a seam #64 that contacts the source/drain feature #78 as illustrated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified by Lin to have the isolation feature further includes a seam that contacts the source/drain feature as taught by Jun #2 in order provide additional electrical safety, reduce weight, and distribute the weight across the device.
Regarding claim 22. Frougier as modified lacks wherein the isolation feature further includes a seam provides an air gap extending downward in a slanted direction away from the source/drain feature in the cross-sectional view.
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Annotated Close up of Figure 33
Jun #2 discloses wherein the isolation feature further includes a seam provides an air gap extending downward in a slanted direction away from the source/drain feature in the cross-sectional view ([0064], annotated close up of figure 33 close up seen above, the isolation feature #46/48/42 includes a seam #64 in contact with the source/drain feature #78 at contact #SLT. It is seen that the contact #SLT is in a slanted direction away from the source/drain feature #78).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified to have the isolation feature further includes a seam provides an air gap extending downward in a slanted direction away from the source/drain feature as taught by Jun #2 in order provide additional electrical safety, reduce weight, and distribute the weight across the device.
Regarding claim 23. Frougier as modified discloses wherein an entirety of the seam is disposed below the first layer and the second layer, wherein the seam lacks an interface with the first layer ([0137], figure 33, there’s a portion of which the entirety of the seam #3310 is disposed below the first layer #2310 and second layer #3110 with the seam lacking an interface with the first layer).
Regarding claim 24. Frougier as modified discloses wherein the seam extends to a sidewall of the source/drain feature ([0137], figure 33, the seam #3310 extends upwards to be at the sidewall of the source/drain #2610).
Regarding claim 25. Frougier as modified discloses wherein the first layer and the second layer contiguously extend from under the gate structure to between the gate structure and the source/drain feature ([0135], figure 31, the sidewall of the source/drain feature #2610 interfaces the isolation feature #2310 and #3110).
Regarding claim 26. Frougier as modified discloses wherein a sidewall of the source/drain feature interfaces the second layer ([0135], figure 31, the sidewall of the source/drain feature #2610 interfaces the isolation feature, second layer #3110).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Frougier (US 20230060619 A1), and Lin et al. (US-20220293729-A1 referred as Lin) in further view of Yegnashankaran (US-7042092-B1 referred as Yegnashankaran).
Regarding claim 27. Frougier as modified lacks wherein the isolation feature includes a third layer and a fourth layer below a seam disposed under the first layer and the second layer, wherein the third layer is the first material and the fourth layer is the second material.
Yegnashankaran discloses wherein the isolation feature includes a third layer and a fourth layer below a seam disposed under the first layer and the second layer ([col 1 lines 22-43], figure 2, the isolations feature includes multiple layers and a seam #210. The third layer #112 and the fourth layer #120 are disposed below the seam #210, first layer #140 and second layer #130), wherein the third layer is the first material and the fourth layer is the second material ([col 2 lines 0-15], figure 2, all the layers of the isolation feature includes SiO2 or any dielectric materials commonly used in the art).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Frougier as modified to have the isolation feature layers be positioned in order as taught by Lin in order to enhance the manufacturing speed, increase the device integrity and to provide additional electrical isolation.
Response to Arguments
Applicant's arguments filed 01/12/2026 have been fully considered but they are not persuasive.
It is noted that Applicant's arguments are related to the amended subject matter, simply stating the new amendments are not seen in the prior art. As is seen in the new rejection above, these amended features of claim 1 are disclosed by the prior art to Frougier et al. to read the gate structure containing a gate dielectric layer and metal gate electrode. The amended features of claim 8 and 21 are disclosed by new prior art. All the arguments relating to limitations previously presented and rejected in the last arguments will be addressed below.
As to claim 8 - "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Frougeir et al. as modified by Chung et al. in combination with newly cited reference to Jun et al. has been presented with regard to claim 8.
As to claim 21 - "Applicant's amendments and arguments were persuasive. Upon further search and consideration a new rejection using a different interpretation of Frougeir et al. as modified by Lin et al. in combination with newly cited reference to Jun #2 et al. has been presented with regard to claim 21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818