Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 2/4/2026 has been entered and considered. The amendments to claims 1, 8, 21, and 22, the cancellation of claims 3 and 15, and the addition of claims 28 and 29 are acknowledged.
Response to Arguments
Applicant’s arguments filed 2/4/2026 with respect to claim 1 have been fully considered and are persuasive. The rejection of claim 1 under 35 U.S.C. 103 has been withdrawn.
Applicant’s arguments with respect to claims 21-25 have been fully considered and are persuasive. The rejections of claim 21-25 under 35 U.S.C. 112 has been withdrawn.
Applicant's arguments with respect to claim 8 have been fully considered but they are not persuasive. After reconsideration of the prior art, the examiner understands that the cavity as taught in Goshal US 6204165 B1 may surround the ferroelectric device in Min US 20210217811 A1, such that the ferroelectric device is entirely within a projection of the cavity from a top view perspective.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 8, 9, 12, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Min US 20210217811 A1 (hereinafter referred to as Min), in view of Goshal US 6204165 B1 (hereinafter referred to as Goshal).
Regarding claim 8, Min teaches
A semiconductor structure (“a memory device” para. 0078 FIG. 21), comprising:
a semiconductor die (structure from “substrate 9” up to “dielectric cap layer 108” para. 0033-0035 FIG. 21) comprising a dielectric structure (“dielectric material layers (601, 610, 620, 630, 640)” para. 0034) and an interconnection structure (metal interconnect structures including “device contact via structures 612”, “first metal line via structures 622”, “second metal line via structures 632”, “third metal line via structures 642”, “first metal line structures 618”, “second metal line structures 638”, “third metal line structures 638”, and “fourth metal line structures 648” para. 0033 FIG. 21); and
a semiconductor device (device comprising “memory cell 101” surrounded by portions of “first dielectric matrix layer 176” and “second dielectric matrix layer 178” para. 0063-0064, 0071) stacked on the semiconductor die, the semiconductor device comprising a first conductive layer (“bottom electrodes 126, 128” para. 0058), a ferroelectric layer (“ferromagnetic hard layer 141” in the “SAF structure 140” para. 0044, 0051) on the first conductive layer, and a second conductive layer (“top electrode 160” para. 0051) on the ferroelectric layer, wherein a peripheral region of the ferroelectric layer is exposed by and surrounding the second conductive layer from a top view perspective (“memory cell 101” has tapered sidewalls, para. 0050. As such, “SAF structure 140”, which includes “ferromagnetic hard layer 141”, laterally extends past the “bottom electrodes 166,128” as seen in FIG. 21); and
an insulating support layer (“via-level dielectric layer 110” para. 0035) under the ferroelectric layer.
However, Min fails to teach having a cavity exposed from an upper surface of the semiconductor die and an interconnection structure below the cavity and the ferroelectric layer is directly over the cavity of the semiconductor die, the insulating support layer between the ferroelectric layer and the cavity, wherein the cavity is an enclosed space defined by the dielectric structure and the insulating support layer, wherein the semiconductor device is entirely within a projection of the cavity from a top view perspective.
Nevertheless, Goshal teaches gaps of “air 410” between “dielectric supports 420” and above “dielectric layer 114” (col 5 lines 1-4 FIG. 4G). “Dielectric supports 420” comprise “cladded copper interconnects 151, 153, 155, 157, 159, and 161” and “dielectric layers 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122 and 123” (col 5 lines 4-13). Air-gaps between metal lines reduce capacitance when compared to silicon oxide (col 1 lines 42-45). As further evidenced in Min, air has a lower dielectric constant than materials such as silicon oxide ad low-k dielectric materials (Min para. 0007). The “low-k dielectric cover 430” is analogous to the “dielectric cap layer 108” in Min (col 5 lines 14-15). By forming “air 410” gaps in the upper layers of interconnect structure in Min, the “memory cells 101” will be above the “air 410” gaps. As seen in FIG. 5, the remaining “dielectric supports 420” form islands within each “air gap 410” and the sizes of the gaps depends on the desired amount of insulation between “interconnects 151, 153, 155, 157, 159, and 161” (col 5 lines 16-25). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a reduction of capacitance, or an increase in isolation of each interconnect element, can be obtained by replacing portions of dielectric material with air as taught in Goshal. The air gap size determines the amount of insulation between interconnect structures, such that the gap may surround the overlapping ferroelectric layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure in Min with the cavity as taught in Goshal. Air is a material that better insulates the interconnect structure than silicon oxide, such that a cavity in a dielectric layer will improve the insulation between neighboring interconnect structures. The cavity surrounds the interconnect structure elements below the ferroelectric layer and may also surround the ferroelectric layer.
Regarding claim 9, Min, modified by Goshal, teach the semiconductor structure according to Claim 8, wherein the cavity is filled with air or an inert gas (gaps are “air 410”).
Regarding claim 12, Min, modified by Goshal, teach the semiconductor structure according to Claim 8, further comprising an IDV (“bottom electrode connection via structures (122, 124))” para. 0059) penetrating the semiconductor die and the insulating support layer to electrically connect the interconnection structure of the semiconductor die to the semiconductor device (“bottom electrode connection via structures (122, 124)” penetrates “via-level dielectric layer 110” and “dielectric cap layer 108” to couple “memory cells 101” to metal interconnect structures, para. 0060).
Regarding claim 14, Min, modified by Goshal, teach the semiconductor structure according to Claim 8, further comprising a plurality of semiconductor devices including the semiconductor device stacked on the semiconductor die (each “memory cell 101” with surrounding “first dielectric matrix layer 176” and “second dielectric matrix layer 178” can be considered a separate device), the dielectric structure has a plurality of cavities, and the ferroelectric layer of each of the semiconductor devices is directly above each of the cavities (The “memory cells 101” are over the different “air 410” gaps between the “dielectric supports 420” having interconnect structures as taught in Goshal.).
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Min US 20210217811 A1 (hereinafter referred to as Min), in view of Goshal US 6204165 B1 (hereinafter referred to as Goshal).
Regarding claim 21, Min teaches
A semiconductor structure (“a memory device” para. 0078 FIG. 21), comprising:
a first substrate (para. 0033-0035 FIG. 21) comprising a CMOS device (“Field effect transistors 700”, where “devices formed on the top surface of the substrate 9 may include complementary metal-oxide-semiconductor (CMOS) transistors”, para. 0031-0032);
a second substrate (device comprising “memory cell 101” surrounded by portions of “first dielectric matrix layer 176” and “second dielectric matrix layer 178” para. 0063-0064, 0071) comprising a ferroelectric memory (“memory cell 101”), wherein the ferroelectric memory comprises a first electrode (“bottom electrodes 126, 128” para. 0058), a ferroelectric layer (“ferromagnetic hard layer 141” in the “SAF structure 140” para. 0044, 0051) on the first electrode, and a second electrode (“top electrode 160” para. 0051) on the ferroelectric layer, wherein a peripheral region of the ferroelectric layer is exposed by and surrounds the second electrode from a top view perspective (“memory cell 101” has tapered sidewalls, para. 0050. As such, “SAF structure 140”, which includes “ferromagnetic hard layer 141”, laterally extends past the “bottom electrodes 166,128” as seen in FIG. 21);
wherein the second substrate is bonded to the upper surface of the first substrate (structure from “substrate 9” up to “dielectric cap layer 108” is directly below the device comprising “memory cell 101”)
However, Min fails to teach a recess disposed in the first substrate, the recess being exposed at an upper surface of the first substrate; and a cavity defined by the recess and arranged between the first substrate and the second substrate.
Nevertheless, Goshal teaches gaps of “air 410” between “dielectric supports 420” and above “dielectric layer 114” (col 5 lines 1-4 FIG. 4G). “Dielectric supports 420” comprise “cladded copper interconnects 151, 153, 155, 157, 159, and 161” and “dielectric layers 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122 and 123” (col 5 lines 4-13). Air-gaps between metal lines reduce capacitance when compared to silicon oxide (col 1 lines 42-45). As further evidenced in Min, air has a lower dielectric constant than materials such as silicon oxide ad low-k dielectric materials (Min para. 0007). The “low-k dielectric cover 430” is analogous to the “dielectric cap layer 108” in Min (col 5 lines 14-15). By forming “air 410” gaps in the upper layers of interconnect structure in Min, the “memory cells 101” will be above the “air 410” gaps. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a reduction of capacitance, or an increase in isolation of each interconnect element, can be obtained by replacing portions of dielectric material with air as taught in Goshal.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure in Min with the cavity as taught in Goshal. Air is a material that better insulates the interconnect structure than silicon oxide, such that a recess in a dielectric layer on the first substrate will improve the insulation between neighboring interconnect structures.
Min, modified by Goshal, further teaches
a cavity defined by the recess and arranged between the first substrate and the second substrate (the “dielectric material layers (601, 610, 620, 630, 640)” in Min now have “air gap 410” as taught in Goshal below the “via-level dielectric layer 110”, defining a cavity).
Regarding claim 22, Min teaches the semiconductor structure according to Claim 21, further comprising: an insulating support layer (“via-level dielectric layer 110” Min para. 0035) arranged between the first substrate and the second substrate, wherein the cavity is defined by the insulating support layer and the recess of the first substrate (the “dielectric material layers (601, 610, 620, 630, 640)” in Min now have “air gap 410” as taught in Goshal below the “via-level dielectric layer 110”, defining a cavity).
Regarding claim 23, Min teaches the semiconductor structure according to Claim 22, wherein the insulating support layer contacts the upper surface of the first substrate (“via-level dielectric layer 110” is in contact with “dielectric cap layer 108”).
Regarding claim 24, Min teaches the semiconductor structure according to Claim 21, wherein the cavity has vertical sidewalls from a cross-sectional view perspective (“air gaps 410” are shown in Goshal to have vertical ends due to vertical sidewalls of “dielectric supports 420”).
Allowable Subject Matter
Claims 1-2, 4, 6-7, and 26-27 are allowed.
The following is an examiner’s statement of reasons for allowance:
The most relevant prior art Gotkis fails to teach wherein the ferroelectric layer has a curvature, and the curvature carries at least partially through to an upper surface of the cavity nearest the ferroelectric layer. Likewise, Goshal also fails to teach this limitation. Therefore, claim 1 is allowed.
Claims 2, 4, 6-7, and 26-27 are allowed based on their dependency on claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 11, 13, 25, and 28-29 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the most relevant prior art Gotkis fails to teach wherein the ferroelectric layer has a curvature, and the curvature carries at least partially through to an upper surface of the cavity nearest the ferroelectric layer. Likewise, Goshal also fails to teach this limitation. Therefore, claim 11 is considered to contain allowable subject matter.
Regarding claim 13, Min and Goshal teach the formation of the cavity at an upper portion of the semiconductor die and the IDV penetrates this upper portion but is above the cavity. Min and Goshal fail to teach wherein the IDV extends along and spaced apart from a side of the cavity. Therefore, claim 13 is considered to contain allowable subject matter.
Regarding claim 25, the most relevant prior art Gotkis fails to teach wherein the cavity has curvature, curved sidewalls from a cross-sectional view perspective. Likewise, Goshal also fails to teach this limitation. Therefore, claim 25 is considered to contain allowable subject matter.
Regarding claim 28, the most relevant prior art Gotkis fails to teach wherein the ferroelectric layer has a curvature, and the curvature carries at least partially through to an upper surface of the cavity nearest the ferroelectric layer. Likewise, Goshal also fails to teach this limitation. Therefore, claim 28 is considered to contain allowable subject matter.
Regarding claim 29, Min and Goshal teach the formation of the cavity at an upper portion of the semiconductor die and the IDV penetrates this upper portion but is above the cavity. Min and Goshal fail to teach the inter die via (IDV) extending from a height over the ferroelectric memory and downward past a sidewall of the ferroelectric memory to make electrical contact with the interconnection structure of the first die and thereby couple the ferroelectric memory to the interconnection structure of the first die. Therefore, claim 29 is considered to contain allowable subject matter.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898