Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is a response to the amendment filed on 12/16/25. The applicant argument regarding Or-Bach et al. is not persuasive; therefore, all the rejections based on Or-Bach et al. is retained and repeated for the following reasons.
Summary of claims
Claims 1-30 are pending.
Claims 1-10, 21-22 and 28-30 are rejected.
Claims 23-27 are objected.
Claims 11-20 are cancelled
Oath/Declaration
The oath/declaration filed on July 07th, 2022 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10, 21-22 and 28-30 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Or-Bach et al. (US Pat. 9911627).
As to claim 1 the prior art teaches a method of manufacturing an integrated circuit (IC), the method comprising:
forming one or more decoupling capacitor (DCAP) cells, wherein each of the one or more DCAP cells comprises one or more polysilicon (PO) layers (see fig 3-4 col. 9 lines 8 to col. 10 lines 45; especially, Or-Bach et al. teach forming one or more decoupling capacitor (DCAP) cells, wherein each of the one or more DCAP cells comprises one or more polysilicon (PO) layers as fig 3-4 col. 9 lines 40 to col. 10 lines 25);
depositing a photoresist layer above the one or more PO layers of each of the one or more DCAP cells wherein the photoresist layer comprises one or more photoresist layer openings overlying of each of the one or more DCAP cells (see fig 38-42 col. 89 lines 38 to col. 93 lines 65; especially, Or-Bach et al. teach depositing a photoresist layer above the one or more PO layers of each of the one or more DCAP cells wherein the photoresist layer comprises one or more photoresist layer openings overlying of each of the one or more DCAP cells as fig 38-42 col. 89 lines 50 to col. 92 lines 50);
forming one or more PO layer openings in the one or more PO layers of each of the one or more DCAP cells based on the corresponding one or more photoresist layer openings (see fig 38-50 col. 92 lines 12 to col. 95 lines 45; especially, Or-Bach et al. teach forming one or more PO layer openings in the one or more PO layers of each of the one or more DCAP cells based on the corresponding one or more photoresist layer openings as fig 38-50 col. 92 lines 40 to col. 95 lines 15);
and removing the photoresist layer (see fig 37-47 col. 93 lines 27 to col. 96 lines 65; especially, Or-Bach et al. teach removing the photoresist layer as fig 37-47 col. 93 lines 45 to col. 96 lines 30).
As to claim 2 the prior art teaches wherein forming the one or more PO layer openings in the one or more PO layers of the one or more DCAP cells comprises performing an etching process (see fig 38-50 col. 91 lines 20 to col. 94 lines 30).
As to claim 3 the prior art teaches wherein the forming the one or more PO layer openings in the one or more PO layers of the one or more DCAP cells comprises forming the one or more PO layer openings according to a predetermined layout pattern of the corresponding DCAP cell (see fig 38-50 col. 93 lines 10 to col. 95 lines 60).
As to claim 4 the prior art teaches wherein the forming the one or more DCAP cells comprises forming each of the one or more DCAP cells four (4) poly pitches, six (6) poly pitches, eight (8) poly pitches, or twelve (12) poly pitches wide along an x-axis direction (see fig 3-4 col. 9 lines 40 to col. 10 lines 20).
As to claim 5 the prior art teaches wherein the forming the one or more DCAP cells comprises forming the one or more DCAP cells further comprising:
at least one first capacitor comprising a lowermost metal layer and an a second lowermost metal layer (see fig 3-7 col. 10 lines 15 to col. 12 lines 30);
and at least one second capacitor comprising at least one p-channel metal oxide semiconductor (PMOS) transistor (see fig 3-7 col. 11 lines 45 to col. 13 lines 45).
As to claim 6 the prior art teaches further comprising:
connecting a first terminal of the at least one first capacitor to a positive polarity of a power supply of the IC, and a second terminal of the at least one first capacitor to a negative polarity of the power supply (see fig 3-10 col. 13 lines 15 to col. 15 lines 20);
and connecting a first terminal of the at least one second capacitor to the positive polarity of the power supply, and a second terminal of the at least one second capacitor to the negative polarity of the power supply (see fig 3-10 col. 14 lines 60 to col. 16 lines 50).
As to claim 7 the prior art teaches wherein the forming the one or more photoresist layer openings is based on solving one or more DRC violations by manually placing the one or more DCAP cells at one or more locations of the one or more DRC violations (see fig 38-42 col. 90 lines 35 to col. 92 lines 60).
As to claim 8 the prior art teaches wherein the forming the one or more photoresist layer openings is based on solving to solve one or more DRC violations by:
placing one or more fill cells at one or more locations of the one or more DRC violations to solve the one or more DRC violations (see fig 38-42 col. 92 lines 40 to col. 95 lines 60);
and replacing the one or more fill cells by the one or more DCAP cells of same sizes (see fig 38-42 col. 94 lines 50 to col. 97 lines 60).
As to claim 9 the prior art teaches wherein the forming the one or more photoresist layer openings is based on solving the one or more DRC violations by replacing the one or more fill cells by the one or more DCAP cells of the same sizes if widths along an x-axis direction of the one or more fill cells are greater than or equal to a predetermined threshold value (see fig 42-48 col. 95 lines 30 to col. 98 lines 55).
As to claim 10 the prior art teaches wherein the at least one PMOS transistor is a fin field effect transistor (FinFET) (see fig 45-50 col. 100 lines 40 to col. 103 lines 60).
As to claim 21 the prior art teaches a method of manufacturing an integrated circuit (IC), the method comprising:
forming one or more decoupling capacitor (DCAP) cells, wherein each of the one or more DCAP cells comprises first and second gate conductor layers extending between first and second active areas and between second and third active areas (see fig 3-4 col. 9 lines 8 to col. 10 lines 45);
depositing a photoresist layer above the first and second gate conductor layers, wherein the photoresist layer comprises first and second photoresist layer openings overlying each of the one or more DCAP cells (see fig 38-42 col. 89 lines 38 to col. 93 lines 65);
forming a first gate conductor layer opening in the first gate conductor layer of the one or more DCAP cells based on the corresponding first photoresist layer opening and a second gate conductor layer opening in the second gate conductor layer each of the one or more DCAP cells based on the corresponding second photoresist layer opening (see fig 38-50 col. 92 lines 12 to col. 95 lines 45);
and removing the photoresist layer (see fig 37-47 col. 93 lines 27 to col. 96 lines 65).
As to claim 22 the prior art teaches wherein the forming the first gate conductor layer opening in the first gate conductor layer comprises forming the first gate conductor layer opening away from the first through fourth active areas in a first direction, and the forming the second gate conductor layer opening in the second gate conductor layer comprises forming the second gate conductor layer opening away from the first through fourth active areas in a second direction opposite the first direction (see fig 38-50 col. 91 lines 50 to col. 94 lines 20).
As to claim 28 the prior art teaches a method of manufacturing an integrated circuit (IC), the method comprising:
forming one or more decoupling capacitor (DCAP) cells, wherein each of the one or more DCAP cells comprises: one or more gate conductor layers (see fig 3-4 col. 9 lines 8 to col. 10 lines 45);
and at least one capacitive device comprising the one or more gate conductor layers (see fig 3-9 col. 10 lines 40 to col. 12 lines 50);
depositing a photoresist layer above the one or more gate conductor layers, wherein the photoresist layer comprises one or more photoresist layer openings, and at least one of the photoresist layer openings has a length greater than a maximum value of a design rule of the IC (see fig 38-42 col. 89 lines 38 to col. 93 lines 65);
forming one or more gate conductor layer openings in the one or more gate conductor layers based on the one or more photoresist layer openings (see fig 38-50 col. 92 lines 12 to col. 95 lines 45);
and removing the photoresist layer (see fig 37-47 col. 93 lines 27 to col. 96 lines 65).
As to claim 29 the prior art teaches wherein the least one capacitive device comprises a single capacitive device comprising a lowermost metal layer segment, a second lowermost metal layer segment, and the one or more gate conductor layers (see fig 3-9 col. 11 lines 50 to col. 13 lines 35).
As to claim 30 the prior art teaches wherein the least one capacitive device comprises:
a first PMOS capacitive device comprising a first one of the one or more gate conductor layers (see fig 3-12 col. 12 lines 40 to col. 14 lines 60);
and a second PMOS capacitive device comprising a second one of the one or more gate conductor layers (see fig 3-13 col. 14 lines 30 to col. 16 lines 40).
Allowable Subject Matter
Claims 23-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Remarks
Applicant’s response and remarks filed on 12/16/25 have been carefully reviewed. Applicant’s arguments have been fully considered but they are not persuasive. Key argument and their response related to the claims are listed as below:
Applicant contends that Or-Bach et al. do not describe “forming one or more decoupling capacitor (DCAP) cells, wherein each of the one or more DCAP cells comprises one or more polysilicon (PO) layers” probes as claimed, Examiner respectfully disagrees. The prior art (Shi et al US Pat. 9911627) do teach forming one or more decoupling capacitor (DCAP) cells, wherein each of the one or more DCAP cells comprises one or more polysilicon (PO) layers (see fig 3-4 col. 9 lines 8 to col. 10 lines 45; especially, Or-Bach et al. teach forming one or more decoupling capacitor (DCAP) cells, wherein each of the one or more DCAP cells comprises one or more polysilicon (PO) layers as fig 3-4 col. 9 lines 40 to col. 10 lines 25)
Applicant contends that Or-Bach et al. do not describe “depositing a photoresist layer above the one or more PO layers of each of the one or more DCAP cells wherein the photoresist layer comprises one or more photoresist layer openings overlying of each of the one or more DCAP cells” probes as claimed, Examiner respectfully disagrees. The prior art (Or-Bach et al. US Pat. 9911627) do teach depositing a photoresist layer above the one or more PO layers of each of the one or more DCAP cells wherein the photoresist layer comprises one or more photoresist layer openings overlying of each of the one or more DCAP cells (see fig 38-42 col. 89 lines 38 to col. 93 lines 65; especially, Or-Bach et al. teach depositing a photoresist layer above the one or more PO layers of each of the one or more DCAP cells wherein the photoresist layer comprises one or more photoresist layer openings overlying of each of the one or more DCAP cells as fig 38-42 col. 89 lines 50 to col. 92 lines 50).
Applicant contends that Or-Bach et al. do not describe “forming one or more PO layer openings in the one or more PO layers of each of the one or more DCAP cells based on the corresponding one or more photoresist layer openings” probes as claimed, Examiner respectfully disagrees. The prior art (Or-Bach et al. US Pat. 9911627) do teach forming one or more PO layer openings in the one or more PO layers of each of the one or more DCAP cells based on the corresponding one or more photoresist layer openings (see fig 38-50 col. 92 lines 12 to col. 95 lines 45; especially, Or-Bach et al. teach forming one or more PO layer openings in the one or more PO layers of each of the one or more DCAP cells based on the corresponding one or more photoresist layer openings as fig 38-50 col. 92 lines 40 to col. 95 lines 15)
Applicant contends that Or-Bach et al. do not describe “removing the photoresist layer” probes as claimed, Examiner respectfully disagrees. The prior art (Or-Bach et al. US Pat. 9911627) do teach removing the photoresist layer (see fig 37-47 col. 93 lines 27 to col. 96 lines 65; especially, Or-Bach et al. teach removing the photoresist layer as fig 37-47 col. 93 lines 45 to col. 96 lines 30)
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
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/BINH C TAT/Primary Examiner, Art Unit 2851