DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The objection to claim 14 made in the Non-Final Office Action mailed 04/24/2025 is rendered moot by cancelation of claim 14.
The amendments filed 07/18/2025 are noted.
Claims 1-11 remain pending; claims 12-16 are canceled.
Claims 1-11 have been fully considered in examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over US 20170373006 A1 (of record), hereafter “Adusumilli” in view of US 20140061919 A1 (of record), hereafter “Cohen”.
Regarding claim 1, Adusumilli teaches a semiconductor device (Fig. 12), comprising:
a substrate 50 [0052];
a first dielectric layer 52 [0052] positioned on the substrate 50 (Fig. 12), wherein the first dielectric layer 52 has an expanded hole 58 [0058] (see Fig. 8) defining a top opening (near wU [0059]) on a top surface of the first dielectric layer 52 (see Fig. 8) and a bottom opening (near wL [0059]) on a top surface of the substrate 50, wherein the expanded hole 58 has two sidewalls extended from the top opening wU to the bottom opening wL (see Fig. 8), wherein the sidewalls of the expanded hole 58 are curved surfaces (see Fig. 8) extended from the top opening wU to the bottom opening wL, wherein a width of the expanded is gradually reduced from a mid-portion (see w2 [0059]) of the expanded hole 58 towards the top wU and bottom openings wL thereof, such that a distance between the sidewalls at the top opening wU is gradually increased toward the mid-portion w2 (see Fig. 8) of the expanded hole 58 while the distance between the sidewalls at the bottom opening wL is gradually increased toward the mid-portion w2 (see Fig. 8) of the expanded hole 58;
a first conductive structure 64S [0070] positioned in the expanded hole 58 (see Figs. 8-12) of the first dielectric layer 52 and
comprising a bottle-shaped cross-sectional profile (see Fig. 12) corresponding to a shape of the expanded hole 58 (see Figs. 8 and 12),
wherein a top surface of the first conductive structure 64S is coplanar with a top surface of the first dielectric layer 52 (see Fig. 11 and [0070]);
a first conductive layer 62L [0063] (where ruthenium) positioned between the first conductive structure 64S and the first dielectric layer 52 (see Fig. 12) and between the first conductive structure 64S and the substrate 50 (Fig. 12);
an adhesive layer 60L ([0062,0038]; TiN layer; see note below) which is formed within the expanded hole 58, positioned between the first conductive layer 62L and the first dielectric layer 52 (see Fig. 12) and between the first conductive layer 62L and the substrate 50;
wherein the first conductive layer 62L is formed by a chemical vapor deposition process [0064] (see note below regarding CVD process and proceeding steps) comprising deposition cycles, wherein each of the deposition cycles comprises:
exposing the adhesive layer 60L to a pulse of reducing agent; and
exposing the adhesive layer 60L to a pulse of precursor;
wherein the adhesive layer 60L, the first conductive layer 62L, and the first conductive structure 64S together configure a composite contact structure (Fig. 12).
Adusumilli does not explicitly teach wherein an aspect ratio of the composite contact structure is greater than 7, but does show that the structure is a high aspect ratio structure (see Figs. 8 and 12, where the depth of the expanded hole 58 is significantly greater than the width at the top opening).
Cohen teaches a semiconductor structure (Fig. 4) with an aspect ratio of at least 7 (see Abstract).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the aspect ratio of Adusumilli greater than 7 in order to create a high aspect ratio connection to provide higher device integration [0070,0071], as motivated by Cohen.
Note: Layer 60 is disclosed as a “diffusion barrier” layer and not explicitly having an “adhesive” property. However, Adusumilli does teach 60 may be Ta, TaN, Ti, or TiN [0038] which is substantially the same as the composition disclosed in the instant application in [0041] disclosed to form an adhesive layer. Accordingly, the diffusion barrier layer 60 of Adusumilli is considered an adhesive layer.
{Note: the specific process and proceeding steps of the chemical vapor deposition are considered to be product-by-process limitations and do not necessarily require the resulting product to be structurally distinct from the feature described by the prior art. Accordingly, the structure of the prior art is understood to teach the structure described by the product by process limitations required by claim 1 (see MPEP 2113(I)).}
Claims 2-5 are rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli in view of Cohen, as applied to claim 1 above, and further in view of US 20130277797 A1, hereafter “Menath”.
Regarding claim 2, Adusumilli in view of Cohen teaches the semiconductor device of claim 1, and Adusumilli further teaches wherein the first conductive layer 62L comprises:
a sidewall portion positioned between the first conductive structure 64S and the first dielectric layer 52 (see Fig. 12) and positioned on two sidewalls of the first conductive structure 64S respectively (Fig. 12); and
a bottom portion positioned between the first conductive structure 64S and the substrate 50 (see Fig. 12) and positioned under a bottom wall of the first conductive structure 64S, wherein the sidewall portion of the first conductive layer 62L is extended from the bottom portion thereof to the top opening of the expanded hole (Fig. 12);
wherein the sidewall of the first conductive layer 62L is a curved sidewall corresponding to the sidewall of the expanded hole (Fig. 12).
Adusumilli does not explicitly teach wherein a thickness of the sidewall portion of the first conductive layer 62L is gradually reduced from bottom to top so as to define a maximum thickness of the sidewall portion of the first conductive layer 62L at the bottom opening of the expanded hole and a minimum thickness of the sidewall portion of the first conductive layer 62L at the top opening of the expanded hole, such that the thickness of the sidewall portion of the first conductive layer 62L at the bottom opening of the expanded hole is larger than the thickness of the sidewall portion of the first conductive layer 62L at the mid-portion of the expanded hole which is larger than the thickness of the sidewall portion of the first conductive layer 62L at the top opening of the expanded hole;
but does teach the sidewall thickness varying between different contact structures (see Fig. 12) and the allowable thickness being in a range from 2-80 nm [0064].
Menath teaches a semiconductor device comprising a conductive structure with curved surfaces (see Fig. 2I) wherein a barrier layer 252 [0060] may have a greatest thickness at the bottom of the opening 228 and be thinner in an upper part of the opening 228 [0060].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the conductive layer 62L of Adusumilli to have a greater thickness at the bottom and for the top to be less thick, as taught by Menath such that the thickness of 62L is greatest at the bottom of the sidewall portion, less great in the mid-portion of the sidewall portion and even less great at the top portion. One would expect such a result in the course of routine experimentation given variation in thickness is well-known, as taught by both Adusumilli and Menath (see [0064] and [0060] respectively) during deposition (e.g., due to exposed cross sections and gravity affecting process gasses), and Menath teaches such a profile is as acceptable and expected as a uniform profile [0060] (see MPEP 2144.05 (II)).
Regarding claim 3, Adusumilli in view of Cohen and Menath teaches the semiconductor device of claim 2, and Adusumilli further teaches wherein the adhesive layer 60L comprises:
a sidewall portion positioned between the sidewall portion of the first conductive layer 62L and the first dielectric layer 52 (see Fig. 12); and a bottom portion positioned between the bottom portion of the first conductive layer 62L and the substrate 50 (see Fig. 12);
wherein a thickness of the sidewall portion of the adhesive layer 60L is gradually reduced from bottom to top so as to define a maximum thickness of the sidewall portion of the adhesive layer 60L at the bottom opening of the expanded hole and a minimum thickness of the sidewall portion of the adhesive layer 60L at the top opening of the expanded hole, such that the thickness of the sidewall portion of the adhesive layer 60L at the bottom opening of the expanded hole is larger than the thickness of the sidewall portion of the adhesive layer 60L at the mid-portion of the expanded hole which is larger than the thickness of the sidewall portion of the adhesive layer 60L at the top opening of the expanded hole (see annotated Fig. 12 below).
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Regarding claim 4, Adusumilli in view of Cohen and Menath teaches the semiconductor device of claim 3, and Adusumilli further teaches wherein a thickness of the bottom portion of the adhesive layer 60L (interpreted as a bottommost surface) is greater than a thickness of the sidewall portion of the adhesive layer 60L (see Fig. 12 annotated above where corners are gradually thicker) at the bottom opening of the expanded hole (portion immediately above thickness of the bottom portion).
Regarding claim 5, Adusumilli in view of Cohen and Menath teaches the semiconductor device of claim 4, and Adusumilli and Menath further teaches wherein a thickness of the bottom portion of the first conductive layer 62L is greater than a thickness of the sidewall portion of the first conductive layer 62L (see Fig. 12 where thickness tapers toward the top opening and [0060] of Menath) at the bottom opening of the expanded hole.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli in view of Cohen and Menath as applied to claims 1-5 above, and further in view of US 20180040507 A1 (of record), hereafter “Reznicek”.
Regarding claim 6, Adusumilli in view of Cohen and Menath teaches the semiconductor device of claim 5, as discussed above.
Adusumilli does not teach wherein the first conductive layer 62L and the first conductive structure 64S comprise a same material, however, Adusumilli teaches the first conductive structure 64S is copper [0040] and the first conductive layer 62L is ruthenium [0040], further, with a cap layer 66 on the composite structure [0072] (see Fig. 12).
Reznicek teaches a semiconductor structure (Fig. 6) with a first conductive layer 18P of ruthenium [0036] and a first conductive structure (20S and 22P [0040] where 20S and 22P both comprise copper [0034]. Reznicek further teaches a process of doping the copper of the first conductive structure 20 with ruthenium (see [0034]) to form a cap region 22 [0034], such that the first conductive structure 20S and 22P and the first conductive layer 18P comprise a same material (ruthenium [0034,0036]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the method of forming the cap layer 22 of Reznicek, so as to dope the copper of the first conductive structure 64S of Adusumilli with ruthenium in place of cap layer 66, such that the first conductive structure 64S and the first conductive layer 62L comprise the same material (ruthenium), in order to further reduce the resistance (see abstract) while reducing the thickness of the device, as taught by Reznicek (where the cap layer is integrally formed with the conductive structure as opposed to being formed on top; see Fig. 6).
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Adusumilli in view of Cohen, Menath and Reznicek, as applied to claims 1-6 above, and further in view of US 20190164885 A1, hereafter “Yang”.
Regarding claim 7, Adusumilli in view of Cohen, Menath and Reznicek teach the semiconductor device of claim 6, and Adusumilli further teaches wherein the adhesive layer 60L comprises titanium nitride [0038] (same material as 18 [0062]).
Adusumilli does not teach wherein the first conductive layer 62L is formed of copper, a copper alloy, silver, gold, tungsten, aluminum, but rather, teaches the first conductive layer is formed of Ruthenium [0063].
Yang teaches a semiconductor device (Fig. 4) with a first conductive layer (reflow enhancement layer 26 [0046]) the may include copper, aluminum, or an alloy thereof [0046].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the first conductive layer 62L of Adusimilli to be copper or aluminum, as taught by Yang as a matter of substituting a material known to serve the same purpose (as a reflow layer) (see MPEP 2144.06 (II)) while choosing a suitable material to achieve the reflow desired with respect to the bulk layer deposited thereon, as taught by Yang [0046].
Regarding claim 8, Adusumilli in view of Cohen, Menath, Reznicek and Yang teach the semiconductor device of claim 7, and Adusumilli further teaches wherein a width of a middle portion w2 [0034] (Fig. 8) of the first conductive structure 64S (see Fig. 12) is greater than a width of a top portion (corresponding to wU) of the first conductive structure 64S or a width of a bottom portion (corresponding to wL) of the first conductive structure 64S.
Regarding claim 9, Adusumilli in view of Cohen, Menath, Reznicek and Yang teach the semiconductor device of claim 8, and Adusumilli further teaches wherein the width of the top portion wU of the first conductive structure 64S and the width of the bottom portion wL of the first conductive structure 64S are substantially the same (see Fig. 12, where the widths are not identical, due to slight variations in the thickness of layers 60L and 62L, see Fig. 12, but substantially the same).
Regarding claim 10, Adusumilli in view of Cohen, Menath, Reznicek and Yang teach the semiconductor device of claim 8, and Adusumilli further teaches wherein the width of the top portion wU of the first conductive structure 64S and the width of the bottom portion wL of the first conductive structure 64S are different (due to slight variations in the thickness of layers 60L and 62L, see Fig. 12).
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been considered, but are not persuasive.
Regarding claim 1, the applicant argues that the prior art fails to teach “wherein the first conductive layer is formed by a chemical vapor deposition process…[including subsequent processing steps]” (Remarks pgs. 6-7). The amended limitations recite a method of forming a device, and while the examiner recognizes that the prior art may not explicitly recite said method steps, the device claim is only limited by any structure that necessarily results from the process steps. If the specific method enables the structure to be materially different from that of the prior art, the applicant could amend the claims to further recite said material difference.
Regarding claim 2 (and likewise claim 4), the applicant argues that Adusumilli does not explicitly disclose the first conductive layer thins from bottom to top in the disclosure, and that the figures may be varied due to defects (Remarks pgs. 9-10). While Adusumilli et al. chose to depict the device so as to have varied thicknesses with respect to the top and bottom of the opening, it is appreciated by the examiner that with respect to the variations in layer 62L, the differences are so minute that they may have been unintended.
Accordingly, the examiner agrees with the applicant and has supplied a supplemental teaching reference demonstrating that during the deposition of layers on a curved surface by a CVD process may result in the thinning of said layer (see above).
Regarding claim 3 (and likewise claim 5), the applicant makes a similar argument to the one regarding claim 2. The examiner disagrees with the applicant, and finds that the variation in thickness of 60L in the figures is more defined that the variation with respect to layer 62L as discussed above (see for example, annotated Fig. 12 above). While the written description does not, in writing, describe a specific thickness variation profile, the disclosure is to be considered in its entirety, including the figures.
Further, the same rationale discussed above regarding claim 2, and the newly relied upon prior art, could likewise be used to describe the variations of thickness required in the adhesion layer of claim 3.
Accordingly, the examiner does not find these arguments persuasive and the rejection is maintained.
Regarding claims 7, the examiner finds these arguments persuasive. However, when performing an updated search, as necessitated by amendment, new prior art was discovered the remedies the deficiencies of the prior art of record. Accordingly, the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bruce Smith III whose telephone number is (571)272-5570. The examiner can normally be reached Monday - Friday; 8 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571)272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRUCE R. SMITH/ Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892