DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on February 19, 2026. Claims 1, 12 and 21 have been amended. New claim 24 has been added. Claims 5, 14-15 and 18- 20 have been
canceled. Currently, claims 1-4, 6-13, 16-17 and 21-24 are pending.
Applicant’s amendment to claim 21 successfully overcomes the 112(a) rejection of claim 21 and dependent claims set forth in the previous Office Action.
Applicant’s amendment to claim 12 successfully overcomes the 112(b) rejection of claim 12 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant's arguments filed on February 19, 2026 have been fully considered but they are not persuasive. The Applicant argues that “Swarbrick is explicitly focused on TSV…. However, TSV and other through interlayer vias vary according to their construction, termination and critical dimensions. For example, TSV are produced according to a front-end-of-line process for the fabrication of the chip itself (e.g., Bosch process). Conversely, a through-interlayer via laterally spaced from a semiconductor chip is necessarily performed separately from the manufacture of the chip. Thus, it is not obvious to substitute a process for a TSV in a device which explicitly recites no through via structure passes through the relevant semiconductor chips.” Applicant further argues regarding Hwang, “either of the "surface mount component 210" or "component 120" can include an active surface disposed away from the depicted bumps/pads/balls. For example, the surface mount component 210 can include bond wires to couple a die with the depicted balls 220. In another example, the "surface mount component 210" or "component 120" can include through-silicon vias (TSV) to couple an active surface on an opposite face with the depicted bumps/pads/balls. As discussed in further detail below, the appropriate legal standard to presume a presence of a feature that Hwang is silent to is inherency.”
The Examiner respectfully disagrees with the analysis. Hwang explicitly teaches a via 113a filled with metal material such as copper, serving as a pillar for interconnection. Swarbrick provides a generic teaching of copper pillar formation, including techniques for controlling via density, pitch and profile to meet varied interconnection requirements. Therefore, it is obvious to one skilled in the art seeking to adapt Hwang’s device for increased I/O requirements, would look to standard high-density interconnect techniques such as those in Swarbrick to optimize pillar pitch and density without undue experimentation.
Furthermore, it is obvious to form device as shown in the figures, where Hwang clearly shows that the via 113a does not pass through the electronic component 120 or the surface mount component 210. Applicant’s own disclosure does not explicitly recite the internal structure of the dies, nor does it inherently require a TSV not passing through them.
Hwang’s electronic component 120, implemented by a processor chip (e.g. CPU, GPU, FPGA, AP) or memory (e.g., DRAM, ROM) has an active surface facing and connected to the first RDL. Similarly, surface-mount component 210 (an active device like 120) has its active surface facing the electronic component 120 with electrical metal connector 220 connecting the chip to the second RDL, demonstrating a typical high density flip chip assembly arrangement.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation, “wherein a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6-11, 12-13, 16-17 and 21-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites, “the first semiconductor chip having an active surface…” where the first semiconductor chip is indefinite and lacks antecedent basis.
The claim further recites, “no through via structure passes through the first semiconductor chip or the second semiconductor chip”, where the through via structure is indefinite and lacks antecedent basis.
Claims 2-4 and 6-11 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Regarding claim 12, the claim recites, “no through via structure passes through the first semiconductor chip or the second semiconductor chip”, where the through via structure is indefinite and lacks antecedent basis.
Claims 13 and 16-17 depend upon claim 12 and do not rectify the problem therefore, they are also rejected.
Regarding claim 21, the claim recites, “a plurality of first semiconductor chips having active surfaces facing, disposed over, and electrically coupled with, a second redistribution structure on an opposite side as the plurality of conductive terminals” which is indefinite as it is structurally unclear and contradictory. The active surfaces face and are electrically coupled with the second redistribution structure but these active surfaces are not disposed on the second redistribution structure. If the active surface is disposed over the structure but also faces and electrically couples with it, this creates a physical contradiction in the spatial arrangement of the chip components.
The claim further recites, “wherein no through via structure passes through the first semiconductor chips;” which is indefinite and lacks antecedent basis. The claim previously recites a plurality of through via structures and plurality of first semiconductor chips.
The claim further recites, “wherein a diameter of each of the plurality of first through via structures…” which is indefinite and lacks antecedent basis.
Claims 22-24 depend upon claim 21 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Nelson (US 2019/0122985 A1; hereafter Nelson) and Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick).
Regarding claim 1, Hwang teaches a semiconductor device (see e.g., Figure 3), comprising:
a plurality of conductive terminals on a first side of the semiconductor device (see e.g., a first electrical connector metal 190 may be disposed in each of the first openings of the first passivation layer 170, Para [0060], Figure 3);
a first redistribution structure (see e.g., built-up wiring layer 132, Figure 3), coupled with the plurality of conductive terminals, including a plurality of first conductive elements, each of the plurality of first conductive elements having a first thickness (see e.g., built-up wiring layer 132 coupled to the electrical connector metal 190. The built-up wiring layer 132 has a plurality of conductive elements having a first thickness, Para [0043], Figure 3);
a second redistribution structure (see e.g., built-up wiring layer 142, Figure 3) disposed on a first side of the first redistribution structure away from the plurality of conductive terminals and including a plurality of second conductive elements, each of the plurality of second conductive elements having a second thickness (see e.g., built-up wiring layer 142 disposed on a side of the built-up wiring layer 132 away from the electrical connector metal 190. The built-up wiring layer 142 has a plurality of conductive elements having a second thickness, Para [0043], Figure 3);
a first semiconductor chip having an active surface facing, electrically coupled with, and disposed on a second side of the first redistribution structure opposite to its first side (see e.g., electronic component 120 has connection pad 120P disposed on its active surface which faces the other side of the built-up wiring layer 132, Paras [0034], [0051], [0052], Figure 3);
a second semiconductor chip having an active surface facing and electrically coupled with the active surface of the first semiconductor chip (see e.g., a surface mount component 210 having its active surface facing and electrically connected to the active surface of the electrical component 120, Para [0061], Figure 3), with the first redistribution structure and the second redistribution structure disposed between the first semiconductor chip and the second semiconductor chip (see e.g., the built-up wiring layers 132 and 142 are disposed between the electronic component 120 and the surface mount component 210, Figure 3);
a third redistribution structure (see e.g., third core wiring layer 112c, Figure 3) disposed opposite the first semiconductor chip from the first redistribution structure and including a plurality of third conductive elements, each of the plurality of third conductive elements having a third thickness; and (see e.g., The third core wiring layer 112c disposed opposite the electronic component 120 from the built-up wiring layer 132. The third core wiring layer 112c has a plurality of conductive elements having a third thickness, Para [0060], Figure 3
a plurality of first through via structures between the first redistribution structure and the third redistribution structure, laterally spaced from the first semiconductor chip (see e.g., through vias113a between the built-up wiring layer 132 and the third core wiring layer 112c laterally spaced from the electronic component 120, Para [0064], Figure 3);
and no through via structure passes through the first semiconductor chip or the second semiconductor chip (see e.g., the via 113a does not pass through the electronic component 120 or the surface mount component 210, Figure 3).
Hwang does not explicitly teach
“wherein the third thickness is substantially less than any of the first thickness or the second thickness”.
In a similar field of endeavor Nelson teaches
wherein the third thickness is substantially less than any of the first thickness or the second thickness (see e.g., as shown in modified Figure 1 the 3RS has less thickness than the thickness of 1RS and 2RS. The plurality of interconnects has different dimensions relative to function, purpose or operation of the interconnect. Interconnect 1505 has a thickness on the order of at least 0.67 times a gate pitch, interconnect 1506 has a thickness more than 100 times interconnect 1505 and interconnect 1507 has a thickness more than 10 times the thickness of interconnect 1506, Para [0027], Figure 1)
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Modified Figure 1 (Nelson)
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement Nelson’s teachings of the third thickness is substantially less than any of the first thickness or the second thickness in the device of Suk so that these RDLs have lower electrical resistance, enabling better signal integrity and power delivery, particularly when dealing with high-density interconnects and large numbers of I/O pins in advanced packaging technologies, where a larger current carrying capacity is needed due to the increased number of connections.
Hwang does not explicitly teach
“wherein a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures”.
In a similar field of endeavor Swarbrick teaches
wherein a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures (see e.g., the diameter of the plurality of pillars is 45µm with a designed 20µm space between them to achieve a pitch of 65µm. Hence, the diameter of the pillars is greater than 1.05 times the lateral spacing between them, Figures 5, 10-15).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Swarbrick teachings of a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures in the device of Hwang in order to provide a higher density of connections within a smaller area, leading to improved electrical performance, smaller chip sizes, and better thermal management.
Regarding claim 4, Hwang, as modified by Nelson and Swarbrick, teaches the limitations of claim 1, as mentioned above. Hwang further teaches
wherein the plurality of first through via structures are each configured to couple the third redistribution structure, through at least one of the first or the second redistribution structure, to the first semiconductor chip (see e.g., the through vias 113a couple the third core wiring layer 112c through built-up wiring layer 132 to the electronic device 210, Figure 3).
Regarding claim 8, Hwang, as modified by Nelson and Swarbrick, teaches the limitations of claim 1, as mentioned above. Hwang further teaches
further comprising:
a fourth redistribution structure disposed opposite the second redistribution structure from the first redistribution structure; and (see e.g., built-up wiring layer 152 disposed opposite the built-up wiring layer 142 from the built-up wiring layer 132, Para [0043], Figure 3)
the second semiconductor chip disposed on a first side of the fourth redistribution structure opposite to a second side of the fourth redistribution structure that faces the second redistribution structure (see e.g., the surface-mount component 210 is disposed on a first side of the built-up wiring layer 132 opposite to a second side of built-up wiring layer 132 that faces the built-up wiring layer 142, Para [0043], Figure 3).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Nelson (US 2019/0122985 A1; hereafter Nelson), Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick) and further in view of Chen et al. (US 2020/0395335 A1; hereafter Chen).
Regarding claim 2, Hwang, as modified by Nelson and Swarbrick, teaches the limitations of claim 1, as mentioned above. Hwang does not explicitly teach
“further comprising a third semiconductor chip disposed on the second side of the first redistribution structure and laterally spaced from the first semiconductor chip”.
In a similar field of endeavor Chen teaches
further comprising a third semiconductor chip disposed on the second side of the first redistribution structure and laterally spaced from the first semiconductor chip (see e.g., first semiconductor chip 100 and a second semiconductor chip 200 on the side of the RDL 2 laterally spaced from each other, Para [0019], Figure 1F).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chen’s teachings of further comprising a third semiconductor chip disposed on the second side of the first redistribution structure and laterally spaced from the first semiconductor chip in the device of Hwang since the field of semiconductor packaging is well-developed and the objective is to increase device density and functionality.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Nelson (US 2019/0122985 A1; hereafter Nelson), Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick) and Chen et al. (US 2020/0395335 A1; hereafter Chen) and further in view of Suk et al. (US 2023/0033087 A1; hereafter Suk).
Regarding claim 3, Hwang, as modified by Nelson, Swarbrick and Chen, teaches the limitations of claim 2 as mentioned above. Hwang does not explicitly teach
“wherein at least one of the plurality of first conductive elements is configured to carry at least one of a data signal or a clock signal between the first semiconductor chip and the third semiconductor chip”.
In a similar field of endeavor Suk teaches
wherein at least one of the plurality of first conductive elements is configured to carry at least one of a data signal or a clock signal between the first semiconductor chip and the third semiconductor chip (see e.g., signal redistribution patterns 610S, used as signal paths for inputting or outputting data signals to or from the first and second semiconductor chips 201 and 202, Para [0072], Figure 8B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Suk’s teachings of wherein at least one of the plurality of first conductive elements is configured to carry at least one of a data signal or a clock signal between the first semiconductor chip and the third semiconductor chip in the device of Hwang in order to achieve the predictable result of enabling necessary data and clock signal communication between adjacent chips mounted within the same package.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Nelson (US 2019/0122985 A1; hereafter Nelson), Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick) and further in view of Scanlan et al. (US 2015/0187710 A1; hereafter Scanlan).
Regarding claim 6, Hwang, as modified Nelson and Swarbrick, teaches the limitations of claim 1 as mentioned above. Hwang does not explicitly teach
“wherein the first thickness and the second thickness are each equal to or greater than about 10 microns (µm)”.
In a similar field of endeavor Scanlan teaches
wherein the first thickness and the second thickness are each equal to or greater than about 10 microns (µm) (see e.g., a plurality of thick RDL traces 40 for routing electrical signals from semiconductor die 24 to points external to a semiconductor package comprising the semiconductor die. Thick RDL traces can comprise a thickness in a range of 4-35 or 5-30.mu.m., Para [0051], Figures 1C-1E).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Scanlan’s teachings of the first thickness and the second thickness are each equal to or greater than about 10 microns (µm) in the device of Hwang since forming thick RDL traces allows for a single process and structure to provide benefits that would otherwise be accomplished with multiple processes and structures, such as the formation of separate redistribution layers and separate vertical interconnects, such as pillars or copper pillars.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Nelson (US 2019/0122985 A1; hereafter Nelson), Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick) and further in view of Suk et al. (US 2023/0033087 A1; hereafter Suk).
Regarding claim 7, Hwang, as modified by Nelson and Swarbrick, teaches the limitations of claim 1, as mentioned above. Hwang does not explicitly teach
“wherein at least one of the plurality of first conductive elements is configured to carry a first supply voltage to the first semiconductor chip, and at least one of the plurality of second conductive elements is configured to carry a second supply voltage to the first semiconductor chip”.
However, Hwang broadly teaches that its core wirings, 112a, 112b, 112c and 112d may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern and the like, indicating that the use of these layers for power distribution is within the scope of its general disclosure.
In a similar field of endeavor Suk teaches
wherein at least one of the plurality of first conductive elements is configured to carry a first supply voltage to the first semiconductor chip (see e.g., signal redistribution patterns 610S, used as signal paths for inputting or outputting data signals to or from the semiconductor chips 201/202, Para [0072], Figure 8B), and at least one of the plurality of second conductive elements is configured to carry a second supply voltage to the first semiconductor chip (see e.g., signal redistribution patterns 620S maybe disposed on the signal redistribution pattern 610S for inputting or outputting data signals to or from the semiconductor chips 201/202, Para [0079], Figure 8B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Suk’s teachings of wherein at least one of the plurality of first conductive elements is configured to carry a first supply voltage to the first semiconductor chip, and at least one of the plurality of second conductive elements is configured to carry a second supply voltage to the first semiconductor chip in the device of Hwang in order to achieve predictable result of supplying necessary operating voltages to the semiconductor chips using conventional RDL power distribution networks.
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Nelson (US 2019/0122985 A1; hereafter Nelson), Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick) and further in view of Jeng et al. (US 2018/0068978 A1; hereafter Jeng).
Regarding claim 9, Hwang, as modified by Nelson and Swarbrick, teaches the limitations of claim 8 as mentioned above. Hwang does not explicitly teach
“further comprising: a plurality of second through via structures laterally spaced from the third semiconductor chip”.
In a similar field of endeavor Jeng teaches
further comprising: a plurality of second through via structures laterally spaced from the third semiconductor chip (see e.g., a plurality of conductive post 781 laterally spaced apart from the third chip 50, Para [0056], Figure 7).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Jeng’s teachings of further comprising: a plurality of second through via structures laterally spaced from the third semiconductor chip in the device of Hwang in order to provide connections between the packages in a stacked chip structure.
Regarding claim 11, Hwang, as modified by Nelson and Swarbrick, teaches the limitations of claim 8 as mentioned above. Hwang does not explicitly teach
“further comprising a fourth semiconductor chip disposed opposite the third semiconductor chip from the fourth redistribution structure, wherein the fourth semiconductor chip includes at least one memory device”.
In a similar field of endeavor Jeng teaches
further comprising a fourth semiconductor chip (see e.g., one or more fifth chip 82, Para [0054], Figure 7) disposed opposite the third semiconductor chip from the fourth redistribution structure (see e.g., fifth chip 82 disposed opposite the third chip 50 from RDL 70, Figure 7), wherein the fourth semiconductor chip includes at least one memory device (see e.g., the fifth chip 82 is a package such as a memory package, Para [0054], Figure 7).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Jeng’s teachings of a fourth semiconductor chip disposed opposite the third semiconductor chip from the fourth redistribution structure, wherein the fourth semiconductor chip includes at least one memory device in the device of Hwang so that an integrated semiconductor circuit containing hundreds to millions of electrical components capable of performing wide range of functions such as signal processing, high speed calculations can be formed.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Nelson (US 2019/0122985 A1; hereafter Nelson), Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick) and Jeng et al. (US 2018/0068978 A1; hereafter Jeng) and further in view of Guzek et al. (US 2011/0215464 A1; hereafter Guzek).
Regarding claim 10, Hwang, as modified by Nelson, Swarbrick and Jeng, teaches the limitations of claim 9 as mentioned above. Hwang does not explicitly teach
“wherein a first density of the plurality of first through via structures is substantially greater than a second density of the plurality of second through via structures”.
In a similar field of endeavor Guzek teaches
wherein a first density of the plurality of first through via structures (see e.g., package interconnects 273, 274, 275 and 276, Para [0019], Figure 4) is substantially greater than a second density of the plurality of second through via structures (see e.g., plurality of interconnects 651 used to electrically couple the die 610 to the package 201 are less in number than the package interconnects 273, 274, 275 and 276, Para [0025], Figure 21).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Guzek’s teachings of a first density of the plurality of first through via structures is substantially greater than a second density of the plurality of second through via structures in the device of Hwang so that in a package on package (PoP) structure the through-vias connecting the packages maybe formed at the periphery and in the central portion chips maybe mounted reducing the overall thickness of the PoP structure.
Claims 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Chen et al. (US 2020/0395335 A1; hereafter Chen), Suk et al. (US 2023/0033087 A1; hereafter Suk) and Jeng et al. (US 2018/0068978 A1; hereafter Jeng).
Regarding claim 12, Hwang teaches a semiconductor device (see e.g., Figure 3), comprising:
a first redistribution structure including a plurality of first conductive elements (see e.g., built-up wiring layer 132 including a plurality of conductive elements, Para [0043], Figure 3);
a second redistribution structure disposed on a first side of the first redistribution structure and including a plurality of second conductive elements (see e.g., built-up wiring layer 142 disposed n a first side of the built-up wiring layer 132 and includes a plurality of conductive elements, Para [0043], Figure 3);
a first semiconductor chip having active surfaces facing, electrically coupled with, and disposed on a second side of the first redistribution structure opposite to its first side (see e.g., electronic component 120 has connection pad 120P disposed on its active surface which faces the second side of the built-up wiring layer 132, Paras [0034], [0051], [0052], Figure 3),
wherein the first conductive elements are configured to carry at least one of a data signal or a clock signal between a first semiconductor chip ….. (see e.g., built-up wiring layer 132 may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. The signal (S) pattern may include various signals other than a ground (GND) pattern, a power (PWR) pattern, and the like, a data signal, and the like, for example. The wiring layer 132 is connected to the active surface of the electronic component 120, Para [0056], Figure 3);
a plurality of first through via structures, each of which is laterally spaced from the first semiconductor chips (see e.g., through vias 113a between the built-up wiring layer 132 and the third core wiring layer 112c laterally spaced from the electronic component 120, Para [0064], Figure 3);
a third redistribution structure disposed opposite the second redistribution structure from the first redistribution structure (see e.g., built-up wiring layer 152 disposed opposite the built-up wiring layer 142 from the built-up wiring layer 132, Figure 3);
a third semiconductor chip having an active surface facing, electrically coupled with, and disposed on a first side of the third redistribution structure opposite to a second side of the third redistribution structure that faces the second redistribution structure, such that the active surface of the third semiconductor chip faces towards the active surfaces of the first semiconductor chip; and (see e.g., a surface mount component 210 having its active surface facing and electrically connected to the active surface of the electrical component 120 via the second electrical connector metal 220. The surface mount component 210 is disposed on the first side of the built-up wiring layer 152 opposite to its second side that faces built-up wiring layer 142, Para [0061], Figure 3)
and wherein no through via structure passes through the first semiconductor chip …. (see e.g., through via 113a does not pass through the electronic component 120, Figure 3)
Hwang does not explicitly teach
“a second semiconductor chip having active surfaces facing, electrically coupled with, and disposed on a second side of the first redistribution structure opposite to its first side
the first semiconductor chip and the second semiconductor chip being laterally spaced apart from each other;
a plurality of first through via structures, each of which is laterally spaced from the first and second semiconductor chips;
the active surface of the third semiconductor chip faces towards the active surfaces of the first semiconductor chip and the second semiconductor chip;”
In a similar field of endeavor Chen teaches
a second semiconductor chip having active surfaces facing, electrically coupled with, and disposed on a second side of the first redistribution structure opposite to its first side (see e.g., semiconductor chips 100 and 200 have their active surfaces facing and electrically coupled with, and disposed on a side of RDL 2, Para [0021], Figure 1F)
the first semiconductor chip and the second semiconductor chip being laterally spaced apart from each other (see e.g., the semiconductor chips 100 and 200 are laterally spaced apart from each other, Figure 1F);
a plurality of first through via structures, each of which is laterally spaced from the first and second semiconductor chips (see e.g., the through integrated fan-out vias TIV laterally spaced apart from the semiconductor chips 100 and 200, Para [0022], Figure 1F);
the active surface of the third semiconductor chip faces towards the active surfaces of the first semiconductor chip and the second semiconductor chip (see e.g., the active surfaces of semiconductor chips 100 and 200 face the active surfaces of chips 300 and 400, Figure 1F);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chen’s teachings of a second semiconductor chip having active surfaces facing, electrically coupled with, and disposed on a second side of the first redistribution structure opposite to its first side the first semiconductor chip and the second semiconductor chip being laterally spaced apart from each other; a plurality of first through via structures, each of which is laterally spaced from the first and second semiconductor chips; the active surface of the third semiconductor chip faces towards the active surfaces of the first semiconductor chip and the second semiconductor chip and in the device of Hwang in order to achieve predictable results by optimizing planar density and vertical integration of multiple semiconductor chips within the same package.
Hwang does not explicitly teach
“wherein the first conductive elements are configured to carry at least one of a data signal or a clock signal between a first semiconductor chip and a second semiconductor chip;
wherein at least one of the plurality of first through via structures is configured to deliver a supply voltage, through one of the first or the second redistribution structure, to the first and second semiconductor chips”,
However, Hwang broadly teaches that its core wirings, 112a, 112b, 112c and 112d may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern and the like, indicating that the use of these layers for power distribution is within the scope of its general disclosure.
In a similar field of endeavor Suk teaches
wherein the first conductive elements are configured to carry at least one of a data signal or a clock signal between a first semiconductor chip and a second semiconductor chip (see e.g., redistribution patterns 610PG include ground/power redistribution patterns and 610S include signal redistribution patterns. The lower signal redistribution patterns 610S may be disposed on the signal structures 300S and may be electrically connected to the signal structures 300S. The signal structures 300S may be electrically connected to the semiconductor chip 201/202 through the signal conductive patterns 130S. The signal structures 300S may be used to transmit data signals to an external device or the semiconductor chip 201/202, Paras [0061], [0062], [0070], [0072], Figure 8B);
wherein at least one of the plurality of first through via structures is configured to deliver a supply voltage, through one of the first or the second redistribution structure, to the first and second semiconductor chips (see e.g., the conductive structure 300 includes ground/power structures 300PG and signals structures 300S. The conductive structures 300 may be used as electrical conduction paths between the first redistribution substrate 100 and the second redistribution substrate 600. For example, the ground/power structures 300PG may be used to deliver the ground or power voltage. The signal structures 300S may be used to transmit data signals to an external device or the semiconductor chip 200, Paras [0061] – [0064], Figure 1D and 8B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Suk’s teachings of wherein at least one of the plurality of first through via structures is configured to deliver a supply voltage, through one of the first or the second redistribution structure, to the first and second semiconductor chips in the device of Hwang in order to achieve predictable result of supplying necessary operating voltages to the semiconductor chips using conventional RDL power distribution networks.
Hwang does not explicitly teach
“a plurality of second through via structures laterally spaced from the third semiconductor chip;”
In a similar field of endeavor Jeng teaches
a plurality of second through via structures laterally spaced from a third semiconductor chip (see e.g., a plurality of conductive post 781 laterally spaced apart from the third chip 50, Para [0056], Figure 7).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Jeng’s teachings of further comprising: a plurality of second through via structures laterally spaced from the third semiconductor chip in the device of Hwang in order to provide connections between the packages in a stacked chip structure.
Regarding claim 17, Hwang, as modified by Chen, Suk and Jeng, teaches the limitations of claim 12 as mentioned above. Hwang does not explicitly teach
“further comprising a fourth semiconductor chip disposed opposite the third semiconductor chip from the third redistribution structure, wherein the fourth semiconductor chip includes at least one memory device”.
In a similar field of endeavor Jeng teaches
further comprising a fourth semiconductor chip (see e.g., one or more fifth chip 82, Para [0054], Figure 7) disposed opposite the third semiconductor chip from the third redistribution structure (see e.g., fifth chip 82 disposed opposite the third chip 50 from RDL 70, Figure 7), wherein the fourth semiconductor chip includes at least one memory device (see e.g., the fifth chip 82 is a package such as a memory package, Para [0054], Figure 7).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Jeng’s teachings of a fourth semiconductor chip disposed opposite the third semiconductor chip from the third redistribution structure, wherein the fourth semiconductor chip includes at least one memory device in the device of Hwang so that an integrated semiconductor circuit containing hundreds to millions of electrical components capable of performing wide range of functions such as signal processing, high speed calculations can be formed.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Chen et al. (US 2020/0395335 A1; hereafter Chen), Suk et al. (US 2023/0033087 A1; hereafter Suk) and Jeng et al. (US 2018/0068978 A1; hereafter Jeng) and further in view of Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick).
Regarding claim 13, Hwang, as modified by Chen, Suk and Jeng, teaches the limitations of claim 12, as mentioned above. Hwang does not explicitly teach
“wherein a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures”.
In a similar field of endeavor Swarbrick teaches
wherein a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures (see e.g., the diameter of the plurality of pillars is 45µm with a designed 20µm space between them to achieve a pitch of 65µm. Hence, the diameter of the pillars is greater than 1.05 times the lateral spacing between them, Figures 5, 10-15).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Swarbrick teachings of a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures in the device of Hwang in order to provide a higher density of connections within a smaller area, leading to improved electrical performance, smaller chip sizes, and better thermal management.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Chen et al. (US 2020/0395335 A1; hereafter Chen), Suk et al. (US 2023/0033087 A1; hereafter Suk) and Jeng et al. (US 2018/0068978 A1; hereafter Jeng) and further in view of Guzek et al. (US 2011/0215464 A1; hereafter Guzek).
Regarding claim 16, Hwang, as modified by Chen, Suk and Jeng, teaches the limitations of claim 12 as mentioned above. Hwang does not explicitly teach
“wherein a first density of the plurality of first through via structures is substantially greater than a second density of the plurality of second through via structures”.
In a similar field of endeavor Guzek teaches
wherein a first density of the plurality of first through via structures (see e.g., package interconnects 273, 274, 275 and 276, Para [0019], Figure 4) is substantially greater than a second density of the plurality of second through via structures (see e.g., plurality of interconnects 651 used to electrically couple the die 610 to the package 201 are less in number than the package interconnects 273, 274, 275 and 276, Para [0025], Figure 21).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Guzek’s teachings of a first density of the plurality of first through via structures is substantially greater than a second density of the plurality of second through via structures in the device of Hwang so that in a package on package (PoP) structure the through-vias connecting the packages maybe formed at the periphery and in the central portion chips maybe mounted reducing the overall thickness of the PoP structure.
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Chen et al. (US 2020/0395335 A1; hereafter Chen), Suk et al. (US 2023/0033087 A1; hereafter Suk), Nelson et al. (US 2019/0122985 A1; hereafter Nelson) and Swarbrick et al., (2017. “High Density, Tall Cu Pillars for 3D Packaging.” IMAPSource Proceedings 2017 (1): 346–52. https://doi.org/10.4071/isom-2017-WP15_017; hereafter Swarbrick).
Regarding claim 21, Hwang teaches a semiconductor device (see e.g., Figure 3), comprising:
a plurality of conductive terminals on a first side of the semiconductor device (see e.g., a first electrical connector metal 190 may be disposed in each of the first openings of the first passivation layer 170, Para [0060], Figure 3);
a first redistribution structure (see e.g., third core wiring layer 112c, Figure 3) disposed proximal to, and electrically coupled with, the plurality of conductive terminals (see e.g., the third core wiring layer 112c disposed proximal and electrically coupled to the first electrical connector metal 190, Para [0060], Figure 3);
a first semiconductor chips having active surfaces facing, disposed over, and electrically coupled with, a second redistribution structure on an opposite side as the plurality of conductive terminals (see e.g., electronic component 120 has connection pad 120P disposed on its active surface which faces and electrically connects with the first wiring built-up layer 132, Paras [0034], [0051], [0052], Figure 3);
a plurality of through-via structures extending between the first redistribution structure and the second redistribution structure (see e.g., a plurality of through vias 113a extending between the first core wiring layer 112c and the built-up wiring layer 132, Para [0064], Figure 3), the first semiconductor chips vertically spacing the first redistribution structure from the second redistribution structure (see e.g., the electronic component 120 vertically spacing the third core wiring layer 112c from the built-up wiring layer 132, Figure 3);
wherein no through via structure passes through the first semiconductor chips; and (see e.g., via 113a does not pass through the electronic component 120, Figure 3)
a third redistribution structure (see e.g., built-up wiring layer 142, Figure 3), disposed on an opposite side of the second redistribution structure as the first semiconductor chips (see e.g., built-up wiring layer 142 disposed on an opposite side of the built-up wiring layer 132 as the electronic component 120, Para [0043], Figure 3), the third redistribution structure configured to electrically couple a second semiconductor chip with the plurality of conductive terminals (see e.g., the built-up wiring layer 142 configured to electrically couple the surface mount component 210 with the first electrical connector metal 190, Para [0061], Figure 3), wherein the third redistribution structure is disposed between the second semiconductor chip and the first semiconductor chips (see e.g., the built-up wiring layer 142 disposed between the surface mount component 210 and the electronic component 120, Figure 3).
Hwang does not explicitly teach
“a plurality of first semiconductor chips having active surfaces facing, disposed over, and electrically coupled with, the first redistribution structure on an opposite side as the plurality of conductive terminals
the plurality of first semiconductor chips vertically spacing the first redistribution structure from the second redistribution structure”;
In a similar field of endeavor Chen teaches
a plurality of first semiconductor chips having active surfaces facing, disposed over, and electrically coupled with, the first redistribution structure on an opposite side as the plurality of conductive terminals (see e.g., first and second semiconductor chips 100 and 200 respectively have active surfaces facing, disposed over and electrically coupled with the RDL2; Examiner’s interpretation: the limitation interpreted as shown in Figure 1h)
the plurality of first semiconductor chips vertically spacing the first redistribution structure from the second redistribution structure (see e.g., the first and second semiconductor chips 100 and 200 respectively vertically spacing RDL1 from RDL2, Figure 1F).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chen’s teachings of a plurality of first semiconductor chips having active surfaces facing, disposed over, and electrically coupled with, the first redistribution structure on an opposite side as the plurality of conductive terminals
the plurality of first semiconductor chips vertically spacing the first redistribution structure from the second redistribution structure in the device of Hwang in order to achieve predictable results by optimizing planar density and vertical integration of multiple semiconductor chips within the same package.
Hwang does not explicitly teach
“…. a second redistribution structure which is substantially thicker than the first redistribution structure
a third redistribution structure which is substantially thicker than the first redistribution structure”,
In a similar field of endeavor Nelson teaches
…. a second redistribution structure which is substantially thicker than the first redistribution structure;
a third redistribution structure which is substantially thicker than the first redistribution structure (see e.g., as shown in modified Figure 1 the redistribution structures above the semiconductor chips are thicker than the redistribution structure below the semiconductor chips. The plurality of interconnects has different dimensions relative to function, purpose or operation of the interconnect. Interconnect 1505 has a thickness on the order of at least 0.67 times a gate pitch, interconnect 1506 has a thickness more than 100 times interconnect 1505 and interconnect 1507 has a thickness more than 10 times the thickness of interconnect 1506, Para [0027], Figure 1).
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement Nelson’s teachings of …. a second redistribution structure which is substantially thicker than the first redistribution structure; a third redistribution structure which is substantially thicker than the first redistribution structure in the device of Hwang so that these RDLs have lower electrical resistance, enabling better signal integrity and power delivery, particularly when dealing with high-density interconnects and large numbers of I/O pins in advanced packaging technologies, where a larger current carrying capacity is needed due to the increased number of connections.
Hwang does not explicitly teach
“a third redistribution structure, disposed on an opposite side of the second redistribution structure as the plurality of first semiconductor chips,
wherein the third redistribution structure is disposed between the second semiconductor chip and the plurality of first semiconductor chips”.
In a similar field of endeavor Suk teaches
a third redistribution structure (see e.g., third redistribution structure including 620PG and 620S, Figure 8B, Para [0078]), disposed on an opposite side of the second redistribution structure as the plurality of first semiconductor chips (see e.g., the third redistribution structure including 620PG and 620S disposed on an opposite side of second distribution structure including 610PG and 610S as the plurality of semiconductor chips 201/202, Figure 8B),
wherein the third redistribution structure is disposed between the second semiconductor chip and the plurality of first semiconductor chips (see e.g., the third distribution structure including 620PG and 620S is disposed between the semiconductor chip 721 and the plurality of semiconductor chips 201/202, Figure 8B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Suk’s teachings of a third redistribution structure, disposed on an opposite side of the second redistribution structure as the plurality of first semiconductor chips,
wherein the third redistribution structure is disposed between the second semiconductor chip and the plurality of first semiconductor chips in the device of Hwang in order to achieve predictable result of enabling necessary electrical connectivity and signal routing between vertically stacked semiconductor chips.
Hwang does not explicitly teach
“wherein a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures”.
In a similar field of endeavor Swarbrick teaches
wherein a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures (see e.g., the diameter of the plurality of pillars is 45µm with a designed 20µm space between them to achieve a pitch of 65µm. Hence, the diameter of the pillars is greater than 1.05 times the lateral spacing between them, Figures 5, 10-15).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Swarbrick teachings of a diameter of each of the plurality of first through via structures is greater than about 1.05 times a lateral spacing between adjacent ones of the plurality of first through via structures in the device of Hwang in order to provide a higher density of connections within a smaller area, leading to improved electrical performance, smaller chip sizes, and better thermal management.
Regarding claim 22, Hwang, as modified by Chen, Nelson, Suk and Swarbrick, teaches the limitations of claim 21 as mentioned above. Hwang further teaches
wherein the first semiconductor chips comprise a compute device (see e.g., electronic component 120 may be configured as an IC in which several hundred to several million or more devices are integrated in a single chip. For example, the electronic component 120 may be implemented by a processor chip such as a central processing unit (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, and the like, an application processor (AP), Para [0051], Figure 3) and the second semiconductor chip comprises a memory device for the compute device (see e.g., the surface mount component 210 may also be implemented by a memory such as a volatile memory (e.g., a DRAM), a non-volatile memory (e.g., a ROM and a flash memory), or the like, Paras [0051], [0061], Figure 3).
Hwang does not explicitly teach
“wherein the plurality of first semiconductor chips comprise a compute device”
In a similar field of endeavor Suk teaches
wherein the plurality of first semiconductor chips comprise a compute device (see e.g., the semiconductor chip 201/202 (equivalent to chip 200 of Figure 7B) maybe a logic chip including an application specific integrated circuit (ASIC) chip or application processor (AP) chip. The ASIC chip may include an application specific integrated circuit. In another example embodiment, the semiconductor chip 200 may include a central processing unit (CPU) or a graphic processing unit (GPU) Paras [0057], [0106], Figures 7B and 8B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement to implement Suk’s teachings of wherein the plurality of first semiconductor chips comprise a compute device in the device of Hwang in order to utilize existing chip technology (ASICs, CPUs, GPUs) for their intended computational purposes in a conventional manner.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Chen et al. (US 2020/0395335 A1; hereafter Chen), Suk et al. (US 2023/0033087 A1; hereafter Suk) and Nelson et al. (US 2019/0122985 A1; hereafter Nelson), wherein a diameter of each of the plurality of first through via structures and further in view of Jeng et al. (US 2018/0068978 A1; hereafter Jeng).
Regarding claim 23, Hwang, as modified by Chen, Nelson, Suk and Swarbrick, teaches the limitations of claim 21 as mentioned above. Hwang
“further comprising:
a plurality of second through via structures laterally spaced from the second semiconductor chip and configured to electrically couple with a third semiconductor chip disposed on an opposite side of the second semiconductor chip as the plurality of first semiconductor chips”.
In a similar field of endeavor Jeng teaches
further comprising: a plurality of second through via structures (see e.g., conductive post 781, Para [0056], Figure 7) laterally spaced from the second semiconductor chip (see e.g., conductive post 781 laterally spaced from the third chip 50, Figure 7) and configured to electrically couple with a third semiconductor chip disposed on an opposite side of the second semiconductor chip as the plurality of first semiconductor chips (see e.g., the conductive post 781 is electrically coupled to the conductive bump 782 and the one or more fifth chip 82. The fifth chip 82 is disposed on an opposite side of fifth chip 50 as the plurality of chips 30/36, Paras [0054], [0056], Figure 7).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Jeng’s teachings of further comprising: a plurality of second through via structures laterally spaced from the second semiconductor chip and configured to electrically couple with a third semiconductor chip disposed on an opposite side of the second semiconductor chip as the plurality of first semiconductor chips in the device of Hwang in order to provide connections between the packages in a stacked chip structure.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. (US 2021/0183784 A1; hereafter Hwang) in view of Chen et al. (US 2020/0395335 A1; hereafter Chen), Suk et al. (US 2023/0033087 A1; hereafter Suk) and Nelson et al. (US 2019/0122985 A1; hereafter Nelson), wherein a diameter of each of the plurality of first through via structures and further in view of Kim et al. (US 2020/0294979 A1; hereafter Kim).
Regarding claim 24, Hwang, as modified by Chen, Nelson, Suk and Swarbrick, teaches the limitations of claim 21 as mentioned above. Hwang does not explicitly teach
“wherein the second semiconductor chip is disposed over a lateral spacing between two of the plurality of first semiconductor chips”.
A rearrangement of parts is held to be an obvious matter of design choice. See In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); See also In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
In a similar field of endeavor Kim teaches
wherein the second semiconductor chip is disposed over a lateral spacing between two of the plurality of first semiconductor chips (see e.g., memory device 131 disposed over a lateral spacing between first semiconductor device 110 and the second semiconductor device 120, Paras [0032], [0034], Figure 2A).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Kim’s teachings of wherein the second semiconductor chip is disposed over a lateral spacing between two of the plurality of first semiconductor chips in the device of Hwang as this modification represents a mere optimization of electrical connections and a predictable rearrangement of parts to solve the common engineering challenge of reducing interconnection lengths between electronic components.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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