DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/15/2025 has been entered.
Response to Arguments
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections above.
Regarding the argument for claim 8, Applicant argues that Kim fails to teach “wherein a bottommost [surface] of the second dielectric layer is higher than a top surface of the conductive contact”. However, under BRI, a top surface could mean either the top surface of element 171 or the top surface of element 172 as both are components of the conductive contact 170 and the claim does not require a “topmost” surface. Kim shows a bottommost surface to be above the top surface of element 172, making it above a top surface of the conductive contact.
Status of the Claims
Claims 1-26 are pending in the application and are currently being examined. Claims 1, 8, 21, and 24 have been amended. Claims 15-20 have been canceled. No new claims have been added.
Claim Objections
Claim 1 is objected to because of the following informalities:
Amended claim 1 recites “a first metal surrounding the via contact and including a sidewall which extends into the conductive contact and which interfaces the conductive contact”. The phrase “which interfaces the conductive contact” can be interpreted to mean the first metal interfaces the conductive contact or the sidewall interfaces the conductive contact. For the purposes of furthering prosecution, Examiner with interpret the limitation to mean “and which the sidewall interfaces the conductive contact”, as explained in Applicant’s Remarks.
Claim 8 is objected to because of the following informalities:
Amended claim 8 recites “wherein a bottommost of the second dielectric layer is higher than a top surface of the conductive contact”. This appears to be a typo meant to say “wherein a bottommost surface of the second dielectric layer is higher than a top surface of the conductive contact”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 8-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2022/0085179 A1, hereafter Kim).
Regarding claim 8, in Fig. 2 Kim teaches a semiconductor device comprising:
a substrate (100 and AP1, [0035]);
a source/drain region (150, [0071]) disposed in the substrate (100 and AP1);
a silicide structure (155, [0082]) disposed on the source/drain region (150);
a first dielectric layer (first interlayer insulating layer, 191, [0074]) disposed over the substrate (100 and AP1);
a conductive contact (170, [0076]) disposed in the first dielectric layer (191) and over the silicide structure (155);
a second dielectric layer (second interlayer insulating layer, 192, [0102]) disposed over the first dielectric layer (191);
a via contact (first connection contact filling, 182, [0103]) disposed in the second dielectric layer (192) and connected to the conductive contact (170);
a third dielectric layer (third interlayer insulating layer, 193, [0118]) disposed over the second dielectric layer (192);
a conductive line (wiring filling layer, 207b, [0121]) disposed in the third dielectric layer (193) and connected to the via contact (182); and
a first metal (first connection contact barrier, 181, [0103]) disposed around the via contact (182) and disposed between the conductive contact (170) and the conductive line (207b), a bottom surface of the via contact (182) being lower than a top surface of the conductive contact (170, see annotated Fig. 3),
wherein a bottommost of the second dielectric layer (192) is higher than a top surface of the conductive contact (170). Kim shows the second dielectric 192 to be deposited on the top surface of element 172, a component of the conductive contact 170, making the bottommost surface of the second dielectric to be above a top surface of the conductive contact.
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Regarding claim 9, in Fig. 2 Kim teaches semiconductor device as claimed in claim 8, wherein the first metal (first connection contact barrier, 181, [0103]) can be made of titanium [0117], one of the possible metals in the present claim.
Regarding claim 10, in Fig. 2 Kim teaches the semiconductor device as claimed in claim 9, wherein the first metal (first connection contact barrier, 181, [0103]) and the conductive contact (170, [0076]) are made of different materials, and the first metal (181) and the conductive line (wiring filling layer, 207b, [0121]) are made of different materials.
Kim discloses the conductive contact (170) can be made of can be made of a combination of cobalt (171, [0100]) and molybdenum (172, [0101]), both different materials than the first metal (181). Kim also discloses that the conductive line (207b) can be made of molybdenum (207b, [0122]), a different material than the first metal (181).
Regarding claim 11, in Fig. 2 Kim teaches the semiconductor device as claimed in claim 8, wherein:
the via contact (first connection contact filling, 182, [0103]) has a first surface (see annotated Fig. 2) connected to the conductive contact (170, [0076]), a second surface opposite (see annotated Fig. 2) to the first surface and connected to the conductive line (wiring filling layer, 207b, [0121]), and a third surface (see annotated Fig. 2) connected between the first surface and the second surface; and
the first metal (first connection contact barrier, 181, [0103]) is disposed on the third surface of the via contact (182).
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Regarding claim 12, in Fig. 2 Kim teaches the semiconductor device as claimed in claim 11, wherein the first metal (first connection contact barrier, 181, [0103]) is further disposed on the first surface (see annotated Fig. 2) of the via contact (first connection contact filling, 182, [0103]).
Regarding claim 13, in Fig. 2 Kim teaches the semiconductor device as claimed in claim 12, further comprising a second metal (206b and 207a, [0122]) that is disposed on the second surface (see annotated Fig. 2) of the via contact (first connection contact filling, 182, [0103]) and around the conductive line (wiring filling layer, 207b, [0121]). Note that 206b and 207a can both be comprised of tungsten [0122].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Liang et al. (US 2020/0105577 A1, hereafter Liang).
Regarding claim 1, in Fig. 2 Kim teaches a semiconductor device comprising:
a substrate (100 and AP1, [0035]);
a source/drain region (150, [0071]) disposed in the substrate (100 and AP1);
a silicide structure (155, [0082]) disposed on the source/drain region (150);
a first dielectric layer (first interlayer insulating layer, 191, [0074]) disposed over the substrate (100 and AP1);
a conductive contact (170, [0076]) disposed in the first dielectric layer (191) and over the silicide structure (155);
a second dielectric layer (second interlayer insulating layer, 192, [0102]) disposed over the first dielectric layer (191);
a via contact (first connection contact filling, 182, [0103]) disposed in the second dielectric layer (192) and connected to the conductive contact (170); and
a first metal (first connection contact barrier, 181, [0103]) surrounding the via contact (182) and including a sidewall which extends into the conductive contact (170, see annotated Fig. 3).
Kim does not teach the sidewall interfacing the conductive contact. However, Liang shows in Fig. 27A a similar device to Kim in which a via contact surrounded by a first metal (380, [0053]) extends into the conductive contact (330 and 320, [0043]) and a sidewall interfaces the conductive contact (see annotated Fig. 27A). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to have element 172 ([0084]) to fill the gaps between the via and the conductive contact as shown in Liang to get the expected result of a via with more contact area to the conductive contact, ensuring a more reliable electrical connection.
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Regarding claim 2, Kim in view of Liang teaches the semiconductor device of claim 1, wherein the first metal (first connection contact barrier of Kim, 181, [0103]) can be made of titanium [0117], one of the possible metals in the present claim.
Regarding claim 3, Kim in view of Liang teaches semiconductor device as claimed in claim 2, wherein the first metal (first connection contact barrier of Kim, 181, [0103]) and the conductive contact (170, [0076]) are made of different materials. Kim discloses the conductive contact can be made of a combination of cobalt (171, [0100]) and molybdenum (172, [0101]), both different metals than the first metal of claim 2.
Regarding claim 4, Kim in view of Liang teaches the semiconductor device as claimed in claim 1. Kim further discloses:
the via contact (first connection contact filling, 182, [0103]) has a first surface (see annotated Fig. 2) connected to the conductive contact (170, [0076]), a second surface (see annotated Fig. 2) opposite to the first surface, and a third surface (see annotated Fig. 2) connected between the first surface and the second surface; and
the first metal (first connection contact barrier, 181, [0103]) is disposed on the third surface of the via contact (182).
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Regarding claim 5, Kim in view of Liang teaches the semiconductor device as claimed in claim 4. Kim further teaches in Fig. 2, the first metal (first connection contact barrier, 181, [0103]) is further disposed on the first surface of the via contact (first connection contact filling, 182, [0103]). Kim teaches a metal layer (206a) disposed onto the second surface (see annotated Fig. 2) that can be comprised of titanium [0122], the same metal as layer 181 [0117].
Regarding claim 6, Kim in view of Liang teaches the semiconductor device as claimed in claim 5, Kim further teaches in Fig. 2, the semiconductor device further comprising a second metal (206b, [0122]) that is disposed on the second surface (see annotated Fig. 2) of the via contact (first connection contact filling, 182, [0103]).
Claim 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 8 above, in view of Gonzalez et al. (US 2002/0020835 A1, hereafter Gonzalez).
Regarding claim 14, in Fig. 2 Kim teaches the semiconductor device of claim 8. Kim fails to disclose a spacer that is disposed between the conductive contact and the conductive line and that surrounds the via contact, the first metal being disposed between the spacer and the via contact.
However, in Fig. 7 Gonzalez discloses a via contact (opening 10, [0026] filled with the second metal layer 22, [0036]) formed in a dielectric (12, [0026]). A spacer (18, [0037]) is formed between the via contact (10 and 22) and the dielectric (12). This spacer allows for smaller via shapes without compromising electrical contacts [0037] Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Kim to include the spacer taught by Gonzalez in order to reduce the resistance of the via, as Gonzalez states in [0037].
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Liang as applied to claims 1 above, in view of Gonzalez et al. (US 2002/0020835 A1, hereafter Gonzalez).
Regarding claim 7, Kim in view of Liang teaches the semiconductor device of claim 1. Kim in view of Liang fails to disclose a spacer that is disposed between the second dielectric layer and the via contact, the first metal being disposed between the spacer and the via contact.
However, in Fig. 7 Gonzalez discloses a via contact (opening 10, [0026] filled with the second metal layer 22, [0036]) formed in a dielectric (12, [0026]). A spacer (18, [0037]) is formed between the via contact (10 and 22) and the dielectric (12). This spacer allows for smaller via shapes without compromising electrical contacts [0037] Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Kim in view of Liang to include the spacer taught by Gonzalez in order to reduce the resistance of the via, as Gonzalez states in [0037].
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Liang in view of Liu et al. (US 2022/0165616 A1, hereafter Liu) and in further view of Wang et al. (US 2021/0118801 A1, hereafter Wang).
Regarding claim 21, in Fig. 2 Kim discloses semiconductor device comprising:
a substrate (100 and AP1, [0035]);
a source/drain region (150, [0071]) disposed in the substrate (100 and AP1);
a silicide structure (155, [0082]) disposed on the source/drain region (150);
a first dielectric layer (first interlayer insulating layer, 191, [0074]) disposed over the substrate (100 and AP1);
a conductive contact (170, [0076]) disposed in the first dielectric layer (191) and over the silicide structure (155);
a second dielectric layer (second interlayer insulating layer, 192, [0102]) opposite to the first dielectric layer;
a via contact (first connection contact filling, 182, [0103]) disposed in the second dielectric layer (192); and
a first metal (first connection contact barrier, 181, [0103]) surrounding the via contact (182).
Kim fails to disclose a first etch stop layer disposed on the first dielectric layer and the conductive contact opposite to the substrate.
However, in Fig. 25 Liu teaches a semiconductor device similar to Kim with a provided etch stop layer (2051, [0032]-) deposited onto contact plugs (115, 0032]) and dielectric layer (113, [0033]) opposite of the substrate (101, [0026]) in order to pattern openings [0034]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor of Kim with the additional etch stop layer of Liu to get the expected result of patterning as desired for the product.
Kim also fails to disclose a via contact interfacing the conductive contact.
However, in Fig. 8, Wang teaches a similar device with a via contact (gate contact, 235, [0032]) including a first metal surrounding the via contact on the sidewalls but not the bottom surface (see annotated Fig. 8), allowing the via contact to interface the conductive contact (gate structure, 206, [0020]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim in view of Liu by removing the first metal on the bottom surface of the contact via in order to reduce contact resistance, as Wang teaches in [0032].
Kim in view of Liu and in further view of Wang does not teach a sidewall that includes a lower portion disposed below the first etch stop layer and interfacing the conductive contact. However, Liang shows in Fig. 27A a similar device to Kim in view of Liu and in view of Wang in which a via contact surrounded by a first metal (380, [0053]) extends into the conductive contact (330 and 320, [0043]) and a sidewall interfaces the conductive contact (see annotated Fig. 27A). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim in view of Liu and in view of Wang to have element 172 ([0084]) to fill the gaps between the via and the conductive contact as shown in Liang to get the expected result of a via with more contact area to the conductive contact, ensuring a more reliable electrical connection.
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Regarding claim 22, Kim in view of Liang in view of Liu and in further view of Wang disclose the semiconductor device of claim 21. Kim further discloses in Fig. 3 Kim further discloses the via contact (first connection contact filling, 182, [0103]) extends into the conductive contact (170, [0076]) (see annotated Fig. 3).
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Claims 23-26 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Liang in view of Liu and in further view of Wang as applied to claim 21 above, and further in view of Gonzalez.
Regarding claim 23, Kim in view of Liang in view of Liu and in further view of Wang teach the semiconductor device of claim 21. Kim in view of Liu and in further view of Wang fail to disclose a spacer that is disposed in the second dielectric layer and first etch stop layer, and the first metal being disposed between the spacer and the via contact.
However, in Fig. 7 Gonzalez discloses a via contact (opening 10, [0026] filled with the second metal layer 22, [0036]) formed in a dielectric (12, [0026]). A spacer (18, [0037]) is formed between the via contact (10 and 22) and the dielectric (12). This spacer allows for smaller via shapes without compromising electrical contacts [0037]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Kim to include the spacer taught by Gonzalez in order to reduce the resistance of the via, as Gonzalez states in [0037].
Regarding claim 24, Kim in view of Liang in view of Liu and in further view of Wang and further in view of Gonzalez teach the semiconductor device of claim 23. In Fig. 7 Gonzalez shows the spacer (18, [0037]) covering the wall surface of the via (opening 10, [0026] filled with the second metal layer 22, [0036]). As this is the location of the first metal of Kim in view of Liang in view of Liu and in further view of Wang and further in view of Gonzalez, the spacer is inherently covering an upper portion of the first metal.
Regarding claim 25, Kim in view of Liang in view of Liu and in further view of Wang and further in view of Gonzalez teach the semiconductor device of claim 23. In Fig. 2 Kim further discloses a conductive line (wiring line, 207, [0120]) disposed on the second dielectric layer (second interlayer insulating layer, 192, [0102]) and the first metal (first connection contact barrier, 181, [0103]) opposite to the first dielectric layer (first interlayer insulating layer, 191, [0074]), and being electrically connected to the via contact (first connection contact filling, 182, [0103]). As the semiconductor taught by Kim in view of Liu and in further view of Wang and further in view of Gonzalez teach a spacer in contact with the via, the conductive wire (207) of Kim is also disposed on the spacer.
Regarding claim 26, Kim in view of Liang in view of Liu and in further view of Wang and further in view of Gonzalez teach the semiconductor device of claim 25. In Fig. 2 of Kim, the conductive wire (wiring line, 207, [0120]) includes a barrier layer (207a, [0121]) disposed on the second dielectric layer (second interlayer insulating layer, 192, [0102]), the spacer (as in the semiconductor device of Kim in view of Liu and in further view of Wang and further in view of Gonzalez), the first metal (first connection contact barrier, 181, [0103]), and the via contact (first connection contact filling, 182, [0103]), and a conductive layer (207b, [0121]). Kim fails to disclose a first and second liner between the barrier and conductive filling layer.
However, in Fig. 47 Liu discloses a component similar to the conductive wire of Kim (conductive component, see annotated Fig. 47). This conductive component comprises a barrier layer (1501, [0105]), a first liner layer (adhesion layer, 1901, [0105]) covering the barrier layer (1501), a second liner layer (seed layer, 2001, [0105]) covering the first liner layer (1901), and a conductive layer (2003) filling in a space defined by the second liner layer (2001). The addition of the first liner (1901) layer is to protect the dielectric layers from diffusion and metallic poisoning, and Liu states in paragraph [0031]. The addition of the seed layer is well known in the art to act as a diffusion barrier much like element 1901 of Liu. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the conductive wire of Kim with the additional layers disclosed by Liu in the conductive component.
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892