DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicants' arguments involve discussing why the previously cited prior art documents fail to disclose the amended limitations. Examiner finds this argument persuasive and has brought in an additional reference to address the amended claim limitations. The applicability of the reference to the amended elements is discussed in the claim rejections below.
Regarding the claim objections in the non-final rejection of 1/27/2026, Applicant’s amendments are sufficient to remedy the informalities. As such, claims 1 and 8 are no longer objected to, as the objections are hereby withdrawn.
Status of the Claims
Claims 1-6, 8-14, and 21-27 are pending in the application and are currently being examined. Claims 1, 8, and 21 have been amended. Claims 7 and 15-20 have been canceled. New claim 27 has been added.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (US 2023/0053379 A1, hereafter Choi).
Regarding claim 8, in Fig. 15 Choi teaches semiconductor device comprising:
a substrate (100 and AP1, [0039]);
a source/drain region (150, [0067]) disposed in the substrate (100 and AP1);
a silicide structure (155, [0109]) disposed on the source/drain region (150);
a first dielectric layer (first interlayer insulating layer, 191, [0099]) disposed over the substrate (100 and AP1);
a conductive contact (170, [0037]) disposed in the first dielectric layer (191) and over the silicide structure (155);
a second dielectric layer (second interlayer insulating layer, 192, [0130]) disposed over the first dielectric layer (191);
a via contact (first via filling, 180b, [0137]) disposed in the second dielectric layer (192) and connected to the conductive contact (170);
a third dielectric layer (third interlayer insulating layer, 193, [0142]) disposed over the second dielectric layer (192);
a conductive line (205b, [0146]) disposed in the third dielectric layer (193) and connected to the via contact (180b); and
a first metal (via barrier layer, 180a, [0137]) disposed around the via contact (180b) and disposed between the conductive contact (170) and the conductive line (205b), a bottom surface of the via contact (180b) being lower than a top surface of the conductive contact (170, seen more clearly in Fig. 17),
wherein a bottommost surface of the second dielectric layer is higher than a topmost surface of the conductive contact, (see annotated Figs. 15 and 17). Choi states that 170_US may include a convex curved portion. This curved portion makes it so the topmost surface of the contact is above the bottommost surface of the second dielectric. However, if the convex portion were removed (see annotated Figs. 15 and 17), the bottommost surface of the second dielectric would be higher than a topmost surface of the conductive contact.
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Regarding claim 9, Choi teaches the semiconductor device as claimed in claim 8, wherein the first metal (via barrier layer, 180a, [0137]) includes W, Mo, Ru, Ti, or combinations thereof. Choi specifically teaches that the via barrier layer may comprise titanium ([0138]).
Regarding claim 10, Choi teaches the semiconductor device as claimed in claim 9, wherein the first metal (via barrier layer, 180a, [0137]) and the conductive contact (170, [0037]) are made of different materials, and the first metal (180a) and the conductive line (205b, [0146]) are made of different materials.
Choi discloses the conductive contact (170) can be made of can be made of a combination of cobalt (171, [0128]) and molybdenum (172, [0129]), both different materials than the first metal (181). Choi also discloses that the conductive line (205b) can be made of molybdenum ([0146]), a different material than the first metal (181).
Regarding claim 11, Choi teaches the semiconductor device as claimed in claim 8, wherein:
the via contact (first via filling, 180b, [0137]) has a first surface (see annotated Fig. 15) connected to the conductive contact (170, [0037]), a second surface (see annotated Fig. 15) opposite to the first surface and connected to the conductive line (205b, [0146]), and a third surface (see annotated Fig. 15) connected between the first surface and the second surface; and
the first metal (via barrier layer, 180a, [0137]) is disposed on the third surface of the via contact (180b).
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Regarding claim 12, Choi teaches the semiconductor device as claimed in claim 11, wherein the first metal (via barrier layer, 180a, [0137]) is further disposed on the first surface (see annotated Fig. 15) of the via contact (first via filling, 180b, [0137]).
Regarding claim 13, Choi teaches the semiconductor device as claimed in claim 12, further comprising a second metal (205a, [0145]) that is disposed on the second surface (see annotated Fig. 15) of the via contact (first via filling, 180b, [0137]) and around the conductive line (205b, [0146]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6, 14, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi, and further in view of Gonzalez et al. (US 2002/0020835 A1, hereafter Gonzalez).
Regarding claim 1, Fig. 15 of Choi teaches a semiconductor device comprising:
a substrate (100 and AP1, [0039]);
a source/drain region (150, [0067]) disposed in the substrate (100 and AP1);
a silicide structure (155, [0109]) disposed on the source/drain region (150);
a first dielectric layer (first interlayer insulating layer, 191, [0099]) disposed over the substrate (100 and AP1);
a conductive contact (170, [0037]) disposed in the first dielectric layer (191) and over the silicide structure (155);
a second dielectric layer (second interlayer insulating layer, 192, [0130]) disposed over the first dielectric layer (191);
a via contact (first via filling, 180b, [0137]) disposed in the second dielectric layer (192) and connected to the conductive contact (170); and
a first metal (via barrier layer, 180a, [0137]) surrounding the via contact (180b) and including a sidewall which extends into the conductive contact (170, seen more clearly in Fig. 17), the sidewall interfacing the conductive contact (170, see annotated Fig. 17),
wherein the semiconductor device further comprises an etch stop layer (195, [0131]) that is disposed on the first dielectric layer (191) and the conductive contact (170),
Choi fails to teach the etch stop layer is spaced apart from the sidewall of the first metal.
However, in Fig. 7 Gonzalez discloses a via contact (opening 10, [0026] filled with the second metal layer 22, [0036]) formed in a dielectric (12, [0026]). A spacer (18, [0037]) is formed between the via contact (10 and 22) and the dielectric (12). This spacer allows for smaller via shapes without compromising electrical contacts [0037] Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Choi to include the spacer taught by Gonzalez in order to reduce the resistance of the via, as Gonzalez states in [0037].
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Regarding claim 2, Choi in view of Gonzalez teach the semiconductor device as claimed in claim 1, wherein the first metal (via barrier layer, 180a, [0137]) includes W, Mo, Ru, Ti, or combinations thereof. Choi specifically teaches that the via barrier layer may comprise titanium ([0138]).
Regarding claim 3, Choi in view of Gonzalez teach the semiconductor device as claimed in claim 2, wherein the first metal (via barrier layer, 180a, [0137]) and the conductive contact (170, [0037]) are made of different materials. Choi discloses the conductive contact can be made of a combination of cobalt (171, [0128]) and molybdenum (172, [0129]), both different metals than the first metal of claim 2.
Regarding claim 4, Choi in view of Gonzalez teach the semiconductor device as claimed in claim 1. Choi further teaches wherein:
the via contact (first via filling, 180b, [0137]) has a first surface (see annotated Fig. 15) connected to the conductive contact (170, [0037]), a second surface (see annotated Fig. 15) opposite to the first surface, and a third surface (see annotated Fig. 15) connected between the first surface and the second surface; and
the first metal (via barrier layer, 180a, [0137]) is disposed on the third surface of the via contact (180b).
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Regarding claim 5, Choi in view of Gonzalez teach the semiconductor device as claimed in claim 4. Fig. 15 of Choi further teaches the first metal (via barrier layer, 180a, [0137]) is further disposed on the first surface (see annotated Fig. 15) of the via contact (first via filling, 180b, [0137]).
Regarding claim 6, Choi in view of Gonzalez teach the semiconductor device as claimed in claim 4. Fig. 15 of Choi further teaches a second metal (205a, [0145]) that is disposed on the second surface (see annotated Fig. 15) of the via contact (first via filling, 180b, [0137]).
Regarding claim 14, Choi teaches the semiconductor device as claimed in claim 8. Choi fails to teach a spacer that is disposed between the conductive contact and the conductive line and that surrounds the via contact (first via filling, 180b, [0137]), the first metal (via barrier layer, 180a, [0137]) being disposed between the spacer and the via contact (180b).
However, in Fig. 7 Gonzalez discloses a via contact (opening 10, [0026] filled with the second metal layer 22, [0036]) formed in a dielectric (12, [0026]). A spacer (18, [0037]) is formed between the via contact (10 and 22) and the dielectric (12). This spacer allows for smaller via shapes without compromising electrical contacts [0037] Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Choi to include the spacer taught by Gonzalez in order to reduce the resistance of the via, as Gonzalez states in [0037].
Regarding claim 27, Choi in view of Gonzalez teach the semiconductor device as claimed in claim 1. Fig. 15 of Choi further teaches wherein a bottom surface of the etch stop layer (195, [0131]) interfaces a top surface of the first dielectric layer (first interlayer insulating layer, 191, [0099]), and a top surface of the etch stop layer (195) interfaces a bottom surface of the second dielectric layer (second interlayer insulating layer, 192, [0130]). While not shown well in either Fig. 15 or 17, Choi states in [0131] that the lower etch stop layer may be extended along the upper surface of the first insulating layer 191, meaning the bottom surface of the etch stop layer interfaces the top surface of the first dielectric layer.
Claim(s) 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Wang et al. (US 2021/0118801 A1, hereafter Wang), and further in view of Gonzalez.
Regarding claim 21, Fig. 15 of Choi teaches a semiconductor device comprising:
a substrate (100 and AP1, [0039]);
a source/drain region (150, [0067]) disposed in the substrate (100 and AP1);
a silicide structure (155, [0109]) disposed on the source/drain region (150);
a first dielectric layer (first interlayer insulating layer, 191, [0099]) disposed over the substrate (100 and AP1);
a conductive contact (170, [0037]) disposed in the first dielectric layer (191) and over the silicide structure (155);
a first etch stop layer (195, [0131]) disposed on the first dielectric layer (191) and the conductive contact (170) opposite to the substrate (100 and AP1);
a second dielectric layer (second interlayer insulating layer, 192, [0130]) disposed on the first etch stop layer (195) opposite to the first dielectric layer (191);
a via contact (first via filling, 180b, [0137]) disposed in the second dielectric layer (192) and the first etch stop layer (195); and
a first metal (via barrier layer, 180a, [0137]) surrounding the via contact (180b), and including a sidewall (see annotated Fig. 15) that includes a lower portion (see annotated Fig. 15) disposed below the first etch stop layer (195).
Choi fails to disclose a via contact interfacing the conductive contact.
However, in Fig. 8, Wang teaches a similar device with a via contact (gate contact, 235, [0032]) including a first metal surrounding the via contact on the sidewalls but not the bottom surface (see annotated Fig. 8), allowing the via contact to interface the conductive contact (gate structure, 206, [0020]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Choi by removing the first metal on the bottom surface of the contact via in order to reduce contact resistance, as Wang teaches in [0032].
Choi fails to teach the etch stop layer is spaced apart from the sidewall of the first metal.
However, in Fig. 7 Gonzalez discloses a via contact (opening 10, [0026] filled with the second metal layer 22, [0036]) formed in a dielectric (12, [0026]). A spacer (18, [0037]) is formed between the via contact (10 and 22) and the dielectric (12). This spacer allows for smaller via shapes without compromising electrical contacts [0037] Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Choi to include the spacer taught by Gonzalez in order to reduce the resistance of the via, as Gonzalez states in [0037].
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Regarding claim 22, Choi in view of Wang and in further view of Gonzalez teach the semiconductor device as claimed in claim 21. Choi further teaches wherein the via contact (first via filling, 180b, [0137]) extends into the conductive contact (170, [0037]).
Regarding claim 23, Choi in view of Wang and in further view of Gonzalez teach the semiconductor device as claimed in claim 21. Choi in view of Wang and in further view of Gonzalez do not explicitly teach a spacer disposed in the second dielectric layer and the first etch stop layer, and the first metal being disposed between the spacer and the via contact.
However, in Fig. 7 Gonzalez discloses a via contact (opening 10, [0026] filled with the second metal layer 22, [0036]) formed in a dielectric (12, [0026]). A spacer (18, [0037]) is formed between the via contact (10 and 22) and the dielectric (12). This spacer allows for smaller via shapes without compromising electrical contacts [0037]. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Choi to include the spacer taught by Gonzalez in order to reduce the resistance of the via, as Gonzalez states in [0037].
Regarding claim 24, Choi in view of Wang and in further view of Gonzalez teach the semiconductor device as claimed in claim 23, wherein the spacer covers an upper portion of the first metal. Gonzalez shows the spacer (18, [0037]) covering the wall surface of the via (opening 10, [0026] filled with the second metal layer 22, [0036]). As this is the location of the first metal of Choi in view of Wang and further in view of Gonzalez, the spacer is inherently covering an upper portion of the first metal.
Regarding claim 25, Choi in view of Wang and in further view of Gonzalez teach the semiconductor device as claimed in claim 23. Choi further discloses a conductive line (205b, [0146]) disposed on the second dielectric layer (second interlayer insulating layer, 192, [0130]) and the first metal (via barrier layer, 180a, [0137]) opposite to the first dielectric layer (first interlayer insulating layer, 191, [0099]), and being electrically connected to the via contact (first via filling, 180b, [0137]). As the semiconductor taught by Choi in view of Wang and further in view of Gonzalez teach a spacer in contact with the via, the conductive wire (207) of Choi is also disposed on the spacer.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Wang in view of Gonzalez as applied to claim 23 above, and further in view of Liu et al. (US 2022/0165616 A1, hereafter Liu).
Regarding claim 26, Choi in view of Wang and in further view of Gonzalez teach the semiconductor device as claimed in claim 25, wherein the conductive line includes:
a barrier layer (205a, [0145]) disposed on the second dielectric layer (second interlayer insulating layer of Choi, 192, [0130]), the spacer (18 of Gonzalez, [0037]), the first metal (via barrier layer of Choi, 180a, [0137]), and the via contact (first via filling of Choi, 180b, [0137]).
Choi in view of Wang and in further view of Gonzalez fails to disclose a first and second liner between the barrier and conductive layer filling in a space defined by the second liner layer.
However, in Fig. 47 Liu discloses a component similar to the conductive wire of Choi (conductive component, see annotated Fig. 47). This conductive component comprises a barrier layer (1501, [0105]), a first liner layer (adhesion layer, 1901, [0105]) covering the barrier layer (1501), a second liner layer (seed layer, 2001, [0105]) covering the first liner layer (1901), and a conductive layer (2003) filling in a space defined by the second liner layer (2001). The addition of the first liner (1901) layer is to protect the dielectric layers from diffusion and metallic poisoning, and Liu states in paragraph [0031]. The addition of the seed layer is well known in the art to act as a diffusion barrier much like element 1901 of Liu. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the conductive wire of Choi in view of Wang and in further view of Gonzalez with the additional layers disclosed by Liu in the conductive component.
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Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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