DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-14, 16-18, is/are rejected under 35 U.S.C. 103 as being unpatentable over U. S. Patent Application Publication No. 2019/0250501 (hereinafter referred to as Sriraman) in view of U. S. Patent Application Publication No. 2018/0365370 (hereinafter referred to as Egan).
Sriraman, in the abstract, in [0004], [0008], [0041], [0098], and [0214], discloses a stack (target layer) over a substrate wherein the substrate can be a dielectric layer, and forming a photoresist pattern (via lithography) overlying the stack wherein the photoresist pattern is based on a design layout (electronic design, claimed IC layout), and Sriraman, in [0008], and [0039]-[0041], [0118], and [0055], and [0174], discloses determining etch parameters that include physical and chemical parameters (plurality of etch parameters) such as layer to be etched (claimed target layer material), and using the layout (model) and using the determined parameters to etch the underlying stack (substrate) through the photoresist pattern (transferring the photoresist pattern). Sriraman, in [0004]-[0009], and [0067], discloses estimating one or more quantities of the etch process parameters and determining corrections (errors) to the etch profile model and modifying the initial design layout, and repeating corrections (at least once or twice) based on the estimated quantity characteristic (EPE, edge placement error ) so as modify the design layout further and optimize the computerized etch profile model, and Sriraman, in [0056], and [0117], discloses that the etch model parameters are tuned and adjusted during the optimization and after computing a an optimized profile, the controller may adjust the operation parameters in response to the computed profile varying different input parameters (claims 1, 4, and 10). Sriraman, in [0039], discloses that the etch parameter (used for the dry etch) includes plasma power, pressure, flow rate (gas flow) etc. (claims 2, and 12). Sriraman, in [0165], discloses that pattern loading is taken into consideration for design layout (claim 3). Sriraman, in [0234], discloses the substrate layer on which the processing is performed can be silicon dioxide (transparent dielectric) (claim 7). Sriraman, in [0039], and [0055], discloses that the etch profile model is based on plasma parameters such as fluxes of gas phase species such as ions, neutrals, photons etc., and their threshold energy, flux of etchant etc. (claim 8). Sriraman, in [0039], and [0058], discloses that the variables that are used to create the etch profile model include etch rate, the substrate to be etched (underlying layer), the etch reaction rate (claim 9). Sriraman, in [0053], [0165], discloses the corrections adjusted in the etch profile include CD (variations in CD i.e., CD uniformity) (claim 11). Sriraman, in [0043]-[0045], discloses that the gas composition is one of the variables to be considered for etch profile so as to optimize the etch model, and Sriraman, in [0095], discloses that the model parameters include material composition of the substrate to be etched (claim 13). Sriraman, in [0053]-[0056], [0061], discloses that the etch profile model takes into account the etch profile feature wherein the etching causes the sidewall to be tapered or have a bow sidewall or rounded bottom etc., (anisotropic etching) and adjusting angular distribution of the particles used in the plasma etching process (i.e., correcting or adjusting degree of anisotropic etching) (claim 14). Sriraman, in [0234], discloses that the processing can be performed on metal layer or oxides (dielectric layers, hardmask) (claims 16-17). Sriraman, in [0095], and [0115], material on the substrate/wafer to be etched is a layer or a stack of layers and is planar (flat top surface) (claim 18).
The difference between the claims and Sriraman is that Sriraman does not disclose including a simulation process that simulates the behavior of the plasma and/or the surface etch behavior/reactions of the target layer based on the information from the IC layout or using the simulation to generate process parameters.
Egan, in the abstract, in [0005], [0007]-[0009], [0040], [0043], discloses using the model to simulate a virtual fabrication process (executing a modeling process) and Egan, in [0045], and [0064]-[0065], discloses that the simulation (virtual fabrication) of plasma etches can be included in the process sequence (integrated process flow) which enables the modeling of wide-range of processes and material-specific etch behavior, wherein the plasma etch simulated includes etch behavior, and is based on types of etch and the type of material being etched wherein the modeling process is based on the mask or layout (IC information) in the design data.
Therefore, it would be obvious to a skilled artisan to modify Sriraman by implementing the simulation based on the model as part of the process sequence as taught by Egan because Sriraman in [0072], and [0107], discloses the use of simulations for extracting information of desired structures to be formed, and Egan, in [0065] discloses that simulating plasma etches enables the capture of a wide range of physical etch behavior and Egan, in [0072], discloses that simulating the etch processes in the virtual fabrication environments enables different surface evolution techniques and Egan, in [0070], discloses that virtual fabrication environment enables including multi-material, multi-physics etch parameters in the modeling process in order to enable the determination of multiple types of etch behavior including etch speed (rate) which is a function of both local surface orientation and local material type.
Claim(s) 5-6, 15, and 19-20, is/are rejected under 35 U.S.C. 103 as being unpatentable over U. S. Patent Application Publication No. 2019/0250501 (hereinafter referred to as Sriraman) in view of U. S. Patent Application Publication No. 2018/0365370 (hereinafter referred to as Egan), as applied to claims 1-4, 7-14, 16-18, and further in view of U. S. Patent Application Publication No. 2011/0217633 (hereinafter referred to as Hosoya).
Sriraman, in the abstract, in [0004], [0008], [0041], [0098], and [0214], discloses a stack (target layer) over a substrate wherein the substrate can be a dielectric layer, and forming a photoresist pattern (via lithography) overlying the stack wherein the photoresist pattern is based on a design layout (electronic design, claimed IC layout), and Sriraman, in [0008], and [0039]-[0041], [0118], and [0055], and [0174], discloses determining etch parameters that include physical and chemical parameters (plurality of etch parameters) such as layer to be etched (claimed target layer material), and using the layout (model) and using the determined parameters to etch the underlying stack (substrate) through the photoresist pattern (transferring the photoresist pattern). Sriraman, in [0039], and [0045], discloses that the etch parameters includes pressure (chamber pressure), plasma power (RF power) and reactant flow rate (gas flow rate) and that the etch profile model include such parameters as part of the process parameter. Sriraman, in [0056], and [0117], discloses that the etch model parameters are tuned and adjusted during the optimization and after computing an optimized etch profile, the controller may adjust the operation parameters in response to the computed profile varying different input parameters. Sriraman, in [0053], [0165], discloses the corrections adjusted in the etch profile include CD (variations in CD i.e., CD uniformity), and Sriraman, in [0043]-[0045], discloses that the gas composition is one of the variables to be considered for etch profile so as to optimize the etch model (claim 19).
The difference between the claims and Sriraman is that Sriraman does not disclose using a simulation process based on the model to generate the process parameters. Sriraman does not disclose that the layer to be etched (substrate to be etched) is a light shielding layer (light absorption layer) or that the stack on the substrate is a reflective multi-layer (claims 5-6). Sriraman does not disclose that the lithography process performed on the photoresist is a maskless lithography (claim 15). Sriraman does not disclose the formation of a light absorption layer of tantalum recited in claim 20.
Egan, in the abstract, in [0005], [0007]-[0009], [0040], discloses using the model to simulate a virtual fabrication process (executing a modeling process). Egan ,in [0008], and [0045], discloses that implementing the modeling as a virtual fabrication as part of the process sequence enables the determination of parameters for an etch process.
The difference between the claims and Sriraman in view of Egan is that Sriraman in view of Egan does not disclose that the layer to be etched (substrate to be etched) is a light shielding layer (light absorption layer) or that the stack on the substrate is a reflective multi-layer (claims 5-6). Sriraman in view of Egan does not disclose that the lithography process performed on the photoresist is a maskless lithography (claim 15). Sriraman in view of Egan does not disclose the formation of a light absorption layer of tantalum recited in claim 20.
Hosoya, in [0005], [0077], [0083], and [0091], discloses that the resist pattern formed on the reflective mask blank is formed by a maskless lithography process (electron beam writing), wherein the mask blank includes a multilayer reflective film formed on the substrate, an absorber film (light shielding, light absorption layer) formed on the reflective multilayer stack, wherein the absorber film comprises tantalum.
Therefore, it would be obvious to a skilled artisan to modify Sriraman by implementing the simulation based on the model as part of the process sequence as taught by Egan because Sriraman in [0072], and [0107], discloses the use of simulations for extracting information of desired structures to be formed, and Egan, in [0065] discloses that simulating plasma etches enables the capture of a wide range of physical etch behavior and Egan, in [0072], discloses that simulating the etch processes in the virtual fabrication environments enables different surface evolution techniques and Egan, in [0070], discloses that virtual fabrication environment enables including multi-material, multi-physics etch parameters in the modeling process in order to enable the determination of multiple types of etch behavior including etch speed (rate) which is a function of both local surface orientation and local material type. It would be obvious to a skilled artisan to modify Sriraman in view of Egan by forming the claimed reflective mask blank layers on the substrate and use the maskless lithography process as taught by Hosoya because Sriraman teaches forming multilayer stack on the substrate and that the substrate to be etched can include different material layers and sequentially deposited layers, and Sriraman teaches performing lithography to pattern the photoresist and does not limit the lithography process to a masked process, and Sriraman in [0165], [0166], and [0189], discloses that the etch process and correction strategy and the modified layout used is for designing and generating an etch photomask design that would be used and implemented for generating a photomask, and does not prohibit the mask from being a reflective photomask and Hosoya, in [0108], uses design rule to generate a reflective mask.
Response to Arguments
Applicant’s arguments, see Amendment and Remarks, filed September 24, 2025, with respect to the rejection(s) of claim(s) 1-20 under 35 U.S.C. 102(a)(1) and 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Egan. See paragraph nos. 3, and 4, above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daborah Chacko-Davis whose telephone number is (571) 272-1380. The examiner can normally be reached on 9:30AM-6:00PM EST Mon-Fri. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark F. Huff can be reached on (571) 272-1385. The fax phone number for the organization where this application or proceeding is assigned is 571-272-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DABORAH CHACKO-DAVIS/Primary Examiner, Art Unit 1737 December 19, 2025.