Prosecution Insights
Last updated: August 17, 2026
Application No. 17/837,312

HEAT DISSIPATION STRUCTURES FOR INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME

Non-Final OA §102§103
Filed
Jun 10, 2022
Examiner
GUPTA, RAJ R
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
82%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
425 granted / 622 resolved
At TC average
Moderate +14% lift
Without
With
+13.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 12m
Avg Prosecution
14 currently pending
Career history
638
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
55.0%
+15.0% vs TC avg
§102
22.3%
-17.7% vs TC avg
§112
17.0%
-23.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 622 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, Species 1 (claims 1-3, 5-14, and 21-26) in the reply filed on 7/9/2025 is acknowledged. Claim 4 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 2, 5, 6, 9, 11-14, 21, 23, and 25 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yu et al. (US 2021/0327866). With regard to claim 1, Yu teaches, in Fig. 1M, a device comprising: a package substrate (200); an interposer (306) having a first side bonded to the package substrate (bottom side in figure, through 204); a first die (302) bonded to a second side of the interposer (top side in figure), the second side being opposite the first side; a ring (112) on the package substrate, wherein the ring surrounds the first die and the interposer (see Fig. 1F); a molding compound (114) disposed between the ring and the first die, wherein the molding compound is in physical contact with the ring (see figure); and a plurality of thermal-conductive layers (116A-C) over and in physical contact with the molding compound and the first die, wherein the molding compound is disposed between the plurality of thermal-conductive layers and the ring (see figure). With regard to claim 2, Yu teaches, in Fig. 1M, a cooling device (120) over and coupled to the plurality of thermal-conductive layers with a thermal interface material (118A-C). With regard to claim 5, Yu teaches, in Fig. 1M, an underfill (314) between the package substrate and the interposer, wherein the underfill is in physical contact with the molding compound (see figure). With regard to claim 6, Yu teaches, in Fig. 1M, that the plurality of thermal-conductive layers comprises: a first thermal-conductive layer (116A); a second thermal-conductive layer (116B) over the first thermal-conductive layer; a third thermal-conductive layer (116C) over the second thermal-conductive layer, wherein the first thermal-conductive layer, the second thermal-conductive layer, and the third thermal- conductive layer comprise different materials ([0042]); and a copper layer (118, [0044]) over the third thermal-conductive layer. With regard to claim 9, Yu teaches, in Fig. 1M, a device comprising: a package component (300) comprising: a first die (302); and an interposer (306); a substrate (200) electrically connected to the first die, wherein the interposer is disposed between the first die and the substrate; a ring (112) attached to the substrate; a molding compound (114) surrounding the package component, wherein the molding compound is disposed between inner sidewalls of the ring and sidewalls of the package component; and a first thermal-conductive layer (116A) over the ring, the molding compound and the package component; and a heat dissipation structure (120) over and coupled to the first thermal-conductive layer, wherein the heat dissipation structure is different from the first thermal-conductive layer (see figure). With regard to claim 11, Yu teaches, in Fig. 1M, that the first thermal-conductive layer comprises copper ([0042]). With regard to claim 12, Yu teaches, in Fig. 1M, a plurality of thermal-conductive layers (116B, 116C, 118A-C) disposed between the first thermal-conductive layer and the package component, the plurality of thermal-conductive layers comprising: a second thermal-conductive layer (116B) over and in physical contact with the package component and the molding compound; a third thermal-conductive layer (116C) over the second thermal-conductive layer; and a fourth thermal-conductive layer (118) over the third thermal-conductive layer, wherein the fourth thermal-conductive layer and the first thermal-conductive layer are in physical contact (see figure). With regard to claim 13, Yu teaches, in Fig. 1M, that the first thermal-conductive layer, the second thermal-conductive layer, the third thermal-conductive layer, and the fourth thermal-conductive layer comprise different materials ([0042], [0044]). With regard to claim 14, Yu teaches, in Fig. 1M, that sidewalls of the plurality of thermal- conductive layers are aligned with sidewalls of the first-thermal conductive layer (see figure). With regard to claim 21, Yu teaches, in Fig. 1M, a device comprising: a ring (112) over and attached to a package substrate (200); an interposer (306) bonded to the package substrate; a first die (302) coupled to the interposer, wherein the ring surrounds the first die and the interposer; a molding compound (114) disposed between the ring and the first die; a plurality of thermal-conductive layers (116A-C) over and in physical contact with the molding compound and the first die; and a cooling device (120) over and coupled to the plurality of thermal-conductive layers with a thermal interface material (118). With regard to claim 23, Yu teaches, in Fig. 1M, a first underfill (314) between the package substrate and the interposer, wherein the first underfill is in physical contact with the molding compound. With regard to claim 25, Yu teaches, in Fig. 1M, that the plurality of thermal-conductive layers comprises: a first thermal-conductive layer (116A); a second thermal-conductive layer (116B) over the first thermal-conductive layer; a third thermal-conductive layer (116C) over the second thermal-conductive layer, wherein the first thermal-conductive layer, the second thermal-conductive layer, and the third thermal-conductive layer comprise different materials ([0042]); and a copper layer (118C) over the third thermal-conductive layer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3, 10, and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2021/0327866) in view of Gaulin et al. (US 2019/0371696). With regard to claim 3, Yu teaches most of the limitations of this claim as set forth above with regard to claim 2. Yu does not explicitly teach that the cooling device comprises a liquid cooled cold-plate, a heat pipe cooling device, or a fan cooling device. Gaulin teaches teach that the cooling device comprises a liquid cooled cold-plate, a heat pipe cooling device, or a fan cooling device ([0043]), “for absorbing excessive or unwanted heat from the die,” ([0043]). Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Yu with the cooling device of Gaulin for absorbing excessive or unwanted heat from the die. With regard to claim 10, Yu teaches most of the limitations of this claim as set forth above with regard to claim 9. Yu also teaches, in Fig 1M, that the heat dissipation structure is coupled to the first thermal-conductive layer with a thermal interface material (118). Yu does not explicitly teach that the heat dissipation structure comprises a liquid cooled cold-plate, a heat pipe cooling device, or a fan cooling device. Gaulin teaches teach that the heat dissipation structure comprises a liquid cooled cold-plate, a heat pipe cooling device, or a fan cooling device ([0043]), “for absorbing excessive or unwanted heat from the die,” ([0043]). Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Yu with the heat dissipation structure of Gaulin for absorbing excessive or unwanted heat from the die. With regard to claim 22, Yu teaches most of the limitations of this claim as set forth above with regard to claim 21. Yu does not explicitly teach that the cooling device comprises a liquid cooled cold-plate, a heat pipe cooling device, or a fan cooling device. Gaulin teaches teach that the cooling device comprises a liquid cooled cold-plate, a heat pipe cooling device, or a fan cooling device ([0043]), “for absorbing excessive or unwanted heat from the die,” ([0043]). Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Yu with the cooling device of Gaulin for absorbing excessive or unwanted heat from the die. Claim(s) 7, 8, and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2021/0327866) in view of Swaminathan et al. (US 2019/0393121). With regard to claim 7, Yu teaches most of the limitations of this claim as set forth above with regard to claim 6. Yu also teaches, in Fig 1M, that the first thermal-conductive layer is aluminum, the second thermal-conductive layer is titanium ([0042]). Yu does not explicitly teach that the third thermal-conductive layer is nickel vanadium. Swaminathan teaches that the third thermal-conductive layer is nickel vanadium ([0036]) to, “assist with minimizing interface thermal resistance,” ([0036]). Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Yu with the material of Swaminathan to assist with minimizing interface thermal resistance. With regard to claim 8, Yu teaches most of the limitations of this claim as set forth above with regard to claim 6. Yu also teaches, in Fig 1M, that the first thermal-conductive layer is aluminum, the second thermal-conductive layer is titanium ([0042]). Yu does not explicitly teach that the third thermal-conductive layer is nickel copper. Swaminathan teaches that the third thermal-conductive layer is nickel copper ([0036]) to, “assist with minimizing interface thermal resistance,” ([0036]). Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Yu with the material of Swaminathan to assist with minimizing interface thermal resistance. With regard to claim 26, Yu teaches most of the limitations of this claim as set forth above with regard to claim 25. Yu also teaches, in Fig 1M, that the first thermal-conductive layer is aluminum, the second thermal-conductive layer is titanium ([0042]). Yu does not explicitly teach that the third thermal-conductive layer is nickel vanadium. Swaminathan teaches that the third thermal-conductive layer is nickel vanadium ([0036]) to, “assist with minimizing interface thermal resistance,” ([0036]). Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Yu with the material of Swaminathan to assist with minimizing interface thermal resistance. Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2021/0327866) in view of Lin et al. (US 2021/0366889). With regard to claim 24, Yu teaches most of the limitations of this claim as set forth above with regard to claim 23. Yu does not explicitly teach a second underfill between the first die and the interposer, wherein the interposer is disposed between the first underfill and the second underfill. Lin teaches, in Fig 7, a second underfill (UF1) between the first die (120a) and the interposer (INT), wherein the interposer is disposed between the first underfill (UF2) and the second underfill so that, “reliability of the conductive bumps 122a and the conductive bumps 122b may be improved,” ([0015]). Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Yu with the interposer configuration of Lin to improve bump reliability. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAJ R GUPTA whose telephone number is (571)270-5707. The examiner can normally be reached 9:30AM-4PM, 8PM-10PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 5712721236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RAJ R GUPTA/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 10, 2022
Application Filed
Jul 31, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12707961
METHOD OF FORMING A CAP LAYER FOR SEALING AN AIR GAP, AND SEMICONDUCTOR DEVICE
4y 6m to grant Granted Aug 11, 2026
Patent 12701761
SIC MOSFET WITH REDUCED ON-RESISTANCE
4y 5m to grant Granted Aug 04, 2026
Patent 12690476
SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF FORMATION
3y 11m to grant Granted Jul 21, 2026
Patent 12684893
REFLECTIVE SEMICONDUCTOR DEVICE WITH MIRROR ELEMENTS HAVING TWO OXIDE LAYERS OVER ALUMINUM LAYER, AND RELATED METHOD
4y 1m to grant Granted Jul 14, 2026
Patent 12653070
SEMICONDUCTOR STRUCTURE HAVING CONDUCTIVE PAD WITH PROTRUSION AND MANUFACTURING METHOD THEREOF
2y 12m to grant Granted Jun 09, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
82%
With Interview (+13.6%)
2y 12m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 622 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month