DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to Amendments/Remarks filed on July 01, 2026.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the recited “an upper layer comprising a catalyst and a lower layer…a topmost surface of the liner is in contact with a bottommost surface of the second graphene cap” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The recited liner (107) with the newly recited “upper and lower layers” is shown as a single layer. It is not clear whether the “topmost surface of the liner” is only directed to the recited “upper layer”. It is also not clear whether the upper and lower layers are conformally formed such that the upper layer is subsequently deposited on the lower layer, where both the lower and upper layers share a common topmost surface.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 30-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claims 30-33, it is not clear what “ranging from about the thickness of the first graphene cap/liner/other graphene cap” is directed to. Thus, the limitations render the claims indefinite and clarification is required. Further, regarding claim 32, the limitation “the recess” lacks sufficient antecedent basis. Thus, the limitation renders the claim indefinite and clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8, 11-13 21-24, and 30-34 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0006425 A1 to Wada et al. (“Wada”) in view of U.S. Patent Application Publication No. 2008/0308939 A1 to Matsunaga (“Matsunaga”)/U.S. Patent Application Publication No. 2015/0097261 A1 to Harris (“Harris”) and U.S. Patent Application Publication No. 2014/0291819 A1 to Barth (“Barth”)/U.S. Patent Application Publication No. 2016/0027738 A1 to Murray et al. (“Murray”). As to claim 1, although Wada in view of Matsunaga/Harris discloses a method, comprising: forming a transistor structure (¶ 0042/Transistor level) on a semiconductor substrate (1/200); forming a contact layer (3/¶ 0023/Tungsten contact plug) for contacts to source, drain, and gate terminals of the transistor structure (¶ 0042/Transistor level); and forming a graphene-clad metal interconnect (10, 30, 90), comprising: depositing a first inter-layer dielectric (ILD) layer (4, 5) over the contact layer (3/¶ 0023/Tungsten contact plug); forming, in the first ILD layer (4, 5), a metal layer that comprises: a first graphene cladding (33a, 93) on sidewalls and a lower surface of the metal layer; and a first graphene cap (33b); depositing a second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization) over the metal layer; etching an opening (96a, 96b/152, 154) in the second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization); and filling the opening (96a, 96b/152, 154) with: a liner (11, 12, 91, 92) on sidewall and horizontal surfaces of the opening (96a, 96b/152, 154), wherein the liner (11, 12, 91, 92) comprises an upper layer (12, 92) comprising a catalyst (12, 92) and a lower layer (11, 91); a second graphene cladding (33a, 93) on sidewall and horizontal surfaces of the liner (11, 12, 91, 92); a metal fill (14, 34, 94) on the second graphene cladding (33a, 93); and a second graphene cap (33b) over the metal fill (14, 34, 94) and the liner (11, 12, 91, 92), wherein a topmost surface (at 12, 92) of the liner (11, 12, 91, 92) is in contact with a bottommost surface of the second graphene cap (33b) (See Wada Fig. 1, Fig. 4, Fig. 9, Fig. 23, Fig. 24, ¶ 0032-¶ 0038, ¶ 0040, ¶ 0042-¶ 0047, ¶ 0063, ¶ 0064, ¶ 0092-¶ 0097, ¶ 0212-¶ 0229, Matsunaga Fig. 1, Fig. 7, Fig. 8, ¶ 0002-¶ 0005, ¶ 0023, ¶ 0024, ¶ 0035, ¶ 0052, ¶ 0056, and Harris Fig. 1), where the contact layer for contacts to source, drain, and gate terminals of the transistor structure provides signal path and control to the transistor structure that is well known in the art. Further, the graphene-clad metal interconnect comprises the same/similar dual damascene structures in several intermediate and global levels to provide connection to the top and external of the transistor structure such that the graphene cladding, metal, and graphene cap are repetitively formed throughout the intermediate and global levels, Wada and Matsunaga/Harris do not further disclose etching a portion of the first graphene cap. However, Barth does disclose etching a portion of the first graphene cap (222) (See Fig. 2, Fig. 10, ¶ 0042, ¶ 0043, ¶ 0045, ¶ 0050, ¶ 0089) and Murray also discloses etching a portion of the first cap (312) (See Fig. 4, Fig. 5, Fig. 7, ¶ 0026, ¶ 0040, ¶ 0044, ¶ 0049, ¶ 0050). In view of the teachings of Barth and Murray, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wada and Matsunaga/Harris to have etching a portion of the first graphene cap because etching the first graphene cap exposes the metal layer and the further textured metal layer aids the adhesion of subsequently formed graphene-clad metal interconnects to further reduce overall via resistance (See Barth ¶ 0042, ¶ 0043, ¶ 0050 and Murray ¶ 0049). As to claim 2, Wada in view of Matsunaga further discloses wherein forming the graphene-clad metal interconnect (10, 30, 90) further comprises forming the liner (11, 12, 91, 92) adjacent to the first graphene cladding (33a, 93) (See Wada Fig 9, Fig. 23). As to claim 3, Wada in view of Matsunaga further discloses wherein the liner (11, 12, 91, 92) surrounds the first and second graphene claddings (33a, 93) (See Wada Fig 9, Fig. 23). As to claim 4, Wada in view of Matsunaga further discloses wherein the liner (11, 12, 91, 92) surrounds the first graphene cladding (33a, 93) and the second graphene cladding (33a, 93) on surfaces of the opening (96a, 96b/152, 154), and wherein the opening (96a, 96b/152, 154) is a dual damascene opening (96a, 96b/152, 154) (See Wada Fig. 9, Fig. 23 and Matsunaga Fig. 7, Fig. 8). As to claim 5, Wada further discloses wherein forming the liner (11, 12, 91, 92) comprises forming a layer of cobalt, tantalum, ruthenium, and combinations thereof (See ¶ 0035, ¶ 0037). As to claim 6, Wada further discloses wherein forming the graphene-clad metal interconnect (10, 30, 90) comprises selectively forming the second graphene cladding (33a, 93) on the liner (11, 12, 91, 92) (See ¶ 0063). As to claim 7, Wada further discloses wherein selectively forming the second graphene cladding (33a, 93) comprises depositing carbon atomic layers in one or more of a chemical vapor deposition (CVD) process, a plasma vapor deposition (PVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and an atomic layer deposition (ALD) process (See ¶ 0063). As to claim 8, Wada in view of Matsunaga further discloses wherein forming the first and second graphene claddings (33a, 93) and the first and second graphene caps (33b) comprise surrounding the metal fill (14, 34, 94) with a multi-layer graphene film (See ¶ 0038). As to claim 11, although Wada in view of Matsunaga/Harris discloses a method, comprising: forming a transistor (¶ 0042/Transistor level) on a semiconductor substrate (1/200); coupling a contact layer (3/¶ 0023/Tungsten contact plug) to the transistor (¶ 0042/Transistor level); and coupling a patterned metal interconnect (10, 30, 90) to the contact layer (3/¶ 0023/Tungsten contact plug), wherein the patterned metal interconnect (10, 30, 90) comprises: first and second graphene-clad metal lines comprising first and second graphene claddings (33a, 33b, 93), respectively, wherein the first and second graphene claddings (33a, 33b, 93) comprise first and second graphene caps (33b), respectively; a liner (11, 12, 91, 92) adjacent to the second graphene cladding (33a, 33b, 93), wherein: the liner (11, 12, 91, 92) comprises an upper layer (12, 92) comprising a catalyst (12, 92) and a lower layer (11, 91); and a topmost surface (at 12, 92) of the liner (11, 12, 91, 92) is in contact with a bottommost surface of the second graphene cap (33b); and a via (¶ 0023) coupling the first and second graphene-clad metal lines to each other (See Wada Fig. 1, Fig. 4, Fig. 9, Fig. 23, Fig. 24, ¶ 0032-¶ 0038, ¶ 0040, ¶ 0042-¶ 0047, ¶ 0063, ¶ 0064, ¶ 0092-¶ 0097, ¶ 0212-¶ 0229, Matsunaga Fig. 1, Fig. 7, Fig. 8, ¶ 0002-¶ 0005, ¶ 0023, ¶ 0024, ¶ 0035, ¶ 0052, ¶ 0056, and Harris Fig. 1), where the contact layer to the transistor provides signal path and control to the transistor that is well known in the art. Further, the contact layer, patterned metal interconnect, and via are provided throughout several intermediate and global levels to provide connections between repetitively formed graphene-clad metal lines to the top and external of the transistor, Wada and Matsunaga/Harris do not further disclose wherein the via is recessed into a portion of the first graphene cap. However, Barth does disclose wherein the via is recessed into a portion of the first graphene cap (222) (See Fig. 2, Fig. 10, ¶ 0042, ¶ 0043, ¶ 0045, ¶ 0050, ¶ 0089) and Murray also discloses wherein the via (110, 120) is recessed into a portion of the first cap (312) (See Fig. 4, Fig. 5, Fig. 7, ¶ 0026, ¶ 0040, ¶ 0044, ¶ 0049, ¶ 0050). In view of the teaching of Barth, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wada and Matsunaga/Harris to have wherein the via is recessed into a portion of the first graphene cap because the via into the first graphene cap further exposes the metal lines and the further textured metal lines aid the adhesion of subsequently formed graphene-clad metal lines to further reduce overall via resistance (See Barth ¶ 0042, ¶ 0043, ¶ 0050 and Murray ¶ 0049). As to claim 12, Wada in view of Matsunaga discloses further comprising depositing an etch stop layer (6/210, 426) on the first and second graphene-clad metal lines (See Wada Fig. 9, ¶ 0047 and Matsunaga Fig. 1, ¶ 0023, ¶ 0035). As to claim 13, Wada in view of Matsunaga/Harris further discloses wherein the liner (11, 12, 91, 92) is a first liner (11, 12, 91, 92), and coupling the patterned metal interconnect (10, 30, 90) to the contact layer (3/¶ 0023/Tungsten contact plug) comprises: depositing a graphene layer (33a, 93) on the contact layer (3/¶ 0023/Tungsten contact plug); depositing a first metal layer (14, 34, 94) on the graphene layer (33a, 93); removing selected portions of the first metal layer (14, 34, 94) to form a patterned metal line; conformally depositing graphene (33a, 93) on top and sidewall surfaces of the patterned metal line to form the first graphene-clad metal line; conformally depositing an etch stop layer (6/210, 426) over the graphene (33a, 93); depositing an inter-layer dielectric (ILD) (dielectric film of IM, SG, GL/Intermediate, Global metallization) over the etch stop layer (6/210, 426); forming the via (¶ 0023) in the ILD (dielectric film of IM, SG, GL/Intermediate, Global metallization), the etch stop layer (6/210, 426), the graphene cap (33a, 93), and the first metal layer (14, 34, 94); conformally depositing a second liner (11, 12, 91, 92) on a bottom and sidewall surfaces of the via (¶ 0023) to form a liner-clad via; and repeating the depositing, removing, and conformally depositing, to form the second graphene-clad metal line in the liner-clad via (See Wada, Matsunaga, and Harris). As to claim 21, although Wada in view of Matsunaga/Harris discloses a method, comprising: forming a transistor structure (¶ 0042/Transistor level) on a semiconductor substrate (1/200); forming a contact layer (3/¶ 0023/Tungsten contact plug) on the transistor structure (¶ 0042/Transistor level); and forming a graphene-clad metal interconnect (10, 30, 90), comprising: depositing a first inter-layer dielectric (ILD) layer (4, 5) over the contact layer (3/¶ 0023/Tungsten contact plug); forming, in the first ILD layer (4, 5), a metal layer (14, 34, 94) that comprises a first graphene cladding (33a, 33b, 93) surrounding the metal layer (14, 34, 94); depositing a second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization) over the metal layer (14, 34, 94); forming an opening (96a, 96b/152, 154) in the second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization); conformally depositing a liner (11, 12, 91, 92) on bottom and sidewall surfaces of the opening (96a, 96b/152, 154), wherein the liner (11, 12, 91, 92) comprises an upper layer (12, 92) comprising a catalyst (12, 92) and a lower layer (11, 91); and filling the opening (96a, 96b/152, 154) with a metal fill (14, 34, 94) surrounded by a second graphene cladding (33a, 33b, 93), wherein: the second graphene cladding (33a, 33b, 93) comprises a graphene cap (33b); and a topmost surface (at 12, 92) of the liner (11, 12, 91, 92) is in contact with a bottommost surface of the second graphene cap (33b) (See Wada Fig. 1, Fig. 4, Fig. 9, Fig. 23, Fig. 24, ¶ 0032-¶ 0038, ¶ 0040, ¶ 0042-¶ 0047, ¶ 0063, ¶ 0064, ¶ 0092-¶ 0097, ¶ 0212-¶ 0229, Matsunaga Fig. 1, Fig. 7, Fig. 8, ¶ 0002-¶ 0005, ¶ 0023, ¶ 0024, ¶ 0035, ¶ 0052, ¶ 0056, and Harris Fig. 1), where the contact layer on the transistor structure provides signal path and control to the transistor structure that is well known in the art. Further, the graphene-clad metal interconnect comprises the same/similar dual damascene structures in several intermediate and global levels to provide connection to the top and external of the transistor structure such that the graphene cladding and metal are repetitively formed throughout the intermediate and global levels, Wada and Matsunaga/Harris do not further disclose forming the opening in the metal layer. However, Barth does disclose forming the opening in the metal layer (220) (See Fig. 2, Fig. 10, ¶ 0042, ¶ 0043, ¶ 0045, ¶ 0050, ¶ 0089) and Murray also discloses forming the opening (520, 530) in the metal layer (208) (See Fig. 4, Fig. 5, Fig. 7, ¶ 0026, ¶ 0040, ¶ 0044, ¶ 0049, ¶ 0050). In view of the teaching of Barth, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wada and Matsunaga/Harris to have forming the opening in the metal layer because the textured metal layer aids the adhesion of subsequently formed graphene-clad metal interconnects to further reduce overall via resistance (See Barth ¶ 0042, ¶ 0043, ¶ 0050 and Murray ¶ 0049). As to claim 22, Wada in view of Matsunaga further discloses wherein forming the graphene-clad metal interconnect (10, 30, 90) further comprises forming the liner (11, 12, 91, 92) adjacent to the first graphene cladding (33a, 33b, 93) (See Wada Fig. 9, Fig. 23). As to claim 23, Wada in view of Matsunaga further discloses wherein the liner (11, 12, 91, 92) surrounds the first and second graphene claddings (33a, 33b, 93) (See Wada Fig. 9, Fig. 23). As to claim 24, Wada in view of Matsunaga further discloses wherein the liner (11, 12, 91, 92) surrounds the first graphene cladding (33a, 33b, 93) and the second graphene cladding (33a, 33b, 93) on surfaces of the opening (96a, 96b/152, 154), and wherein the opening (96a, 96b/152, 154) is a dual damascene opening (96a, 96b/152, 154) (See Wada Fig. 9, Fig. 23 and Matsunaga Fig. 7, Fig. 8). As to claim 30, Wada in view of Barth and Murray further discloses wherein: a height (115 nm) of the opening (110, 120) ranges from about one half a thickness (25 nm) of the first graphene cap to about five times the thickness (25 nm) of the first graphene cap; and etching the opening (110, 120) from the height (115 nm) ranging from about the thickness (25 nm) of the first graphene cap to about five times the thickness (25 nm) of the first graphene cap further comprises etching a portion of the metal layer (208) (See Barth Fig. 5, ¶ 0037, ¶ 0038) (Notes: the limitation “about” is not explicitly defined such that the imitation is met). As to claim 31, Wada in view of Barth and Murray further discloses wherein: a height (125 nm) of the opening (110, 120) ranges from about one half a thickness (50 nm) of the liner to about five times the thickness (50 nm) of the liner; and etching the opening (110, 120) from the height (125 nm) ranging from about the thickness (50 nm) of the liner to about five times the thickness (50 nm) of the liner further comprises etching a portion of the metal layer (208) (See Barth Fig. 5, ¶ 0037, ¶ 0038, ¶ 0041) (Notes: the limitation “about” is not explicitly defined such that the imitation is met). As to claim 32, Wada in view of Barth and Murray further discloses wherein: a height (115 nm) of the recess ranges from about one half a thickness (25 nm) of the first graphene cap to about five times the thickness (25 nm) of the first graphene cap, wherein for the height (115 nm) ranging from about the thickness (25 nm) of the first graphene cap to about five times the thickness (25 nm) of the first graphene cap, the via is further recessed into a portion of the first metal line (208) (See Barth Fig. 5, ¶ 0037, ¶ 0038) (Notes: the limitation “about” is not explicitly defined such that the imitation is met). As to claim 33, Wada in view of Barth and Murray further discloses wherein: forming the metal layer (14, 34, 94/208) further comprises forming another graphene cap (33b) on the metal layer (14, 34, 94/208), forming the opening (96a, 96b/152, 154/110, 120) in the second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization) further comprises forming an opening in a portion of the other graphene cap (33b); and a height (115 nm) of the opening (96a, 96b/152, 154/110, 120) ranges from about one half a thickness (25 nm) of the other graphene cap (33b) to about five times the thickness (25 nm) of the other graphene cap (33b), wherein for the height (115 nm) ranging from about the thickness (25 nm) of the other graphene cap (33b) to about five times the thickness (25 nm) of the other graphene cap (33b), the opening is further formed in a portion of the metal layer (14, 34, 94/208) (See Barth Fig. 5, ¶ 0037, ¶ 0038) (Notes: the limitation “about” is not explicitly defined such that the imitation is met). Further, the applicant also has not established the critical nature of the “about one half a thickness of the first graphene cap/liner to about five times the thickness”. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims….In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to have various ranges. It would also have been obvious to one of ordinary skill in the art at the time the invention was made to discover the optimum or workable ranges by routine experimentations to adjust the height and the thickness in view of overall device dimensions and barrier and catalytic properties. See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
As to claim 34, Wada further discloses wherein: the first graphene cladding (33a, 33b, 93) comprises another graphene cap (33b); and the top surface (at 12, 92) of the liner (11, 12, 91, 92) is in contact with a bottommost surface of the other graphene cap (33b) (See Wada Fig. 9).
Claim(s) 35 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0006425 A1 to Wada et al. (“Wada”), U.S. Patent Application Publication No. 2008/0308939 A1 to Matsunaga (“Matsunaga”)/U.S. Patent Application Publication No. 2015/0097261 A1 to Harris (“Harris”), and U.S. Patent Application Publication No. 2014/0291819 A1 to Barth (“Barth”)/U.S. Patent Application Publication No. 2016/0027738 A1 to Murray et al. (“Murray”) as applied to claim 1 above, and further in view JP-3588612-B2 to 羽多野 et al. (“羽多野”). As to claim 35, although Wada discloses wherein the lower layer (11) comprises a barrier layer of TaN, TiN, Ta, Ti, a laminated structure of different materials (See ¶ 0035), Wada does not further disclose wherein the lower layer comprises an aluminum-copper alloy material. However, 羽多野 does disclose wherein the lower layer (43) comprises an aluminum-copper alloy material (See ¶ 0066). In view of the teaching of 羽多野, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Wada to have wherein the lower layer comprises an aluminum-copper alloy material because aluminum-copper alloy along with other well-known barrier materials are high melting point metals and having a desired dual damascene structure (See ¶ 0066).
Response to Arguments
Applicant's arguments with respect to claims 1, 11, and 21 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815
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