DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 27, 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21-24, 26-27, and 29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 21, the limitation “a thickness of first graphene cap” lacks sufficient antecedent basis. Although there are first and second graphene claddings, it is not clear where “first graphene cap” is established or formed and whether the first graphene cap is directed to the first graphene cladding or the second graphene cladding. Thus, the limitation renders the claims indefinite and clarification is required. As to claim 27, the limitation “the height” lacks sufficient antecedent basis. Thus, the limitation renders the claim indefinite and clarification is required. As to claim 29, the limitation “the thickness of the graphene cap” lacks sufficient antecedent basis. Thus, the limitation renders the claim indefinite and clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-9, 11-13 21-24, and 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0006425 A1 to Wada et al. (“Wada”) in view of U.S. Patent Application Publication No. 2008/0308939 A1 to Matsunaga (“Matsunaga”)/U.S. Patent Application Publication No. 2015/0097261 A1 to Harris (“Harris”) and U.S. Patent Application Publication No. 2014/0291819 A1 to Barth (“Barth”)/U.S. Patent Application Publication No. 2016/0027738 A1 to Murray et al. (“Murray”). As to claim 1, although Wada in view of Matsunaga/Harris discloses a method, comprising: forming a transistor structure (¶ 0042/Transistor level) on a semiconductor substrate (1/200); forming a contact layer (3/¶ 0023/Tungsten contact plug) for contacts to source, drain, and gate terminals of the transistor structure (¶ 0042/Transistor level); and forming a graphene-clad metal interconnect (10, 30, 90), comprising: depositing a first inter-layer dielectric (ILD) layer (4, 5) over the contact layer (3/¶ 0023/Tungsten contact plug); forming, in the first ILD layer (4, 5), a metal layer that comprises: a first graphene cladding (33a, 93) on sidewalls and a lower surface of the metal layer; and a first graphene cap (33b); depositing a second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization) over the metal layer; etching an opening (96a, 96b/152, 154) in the second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization); and filling the opening (96a, 96b/152, 154) with: a liner (11, 12, 91, 92) on sidewall and horizontal surfaces of the opening (96a, 96b/152, 154); a second graphene cladding (33a, 93) on sidewall and horizontal surfaces of the liner (11, 12, 91, 92); a metal fill (14, 34, 94) on the second graphene cladding (33a, 93); and a second graphene cap (33b) over the metal fill (14, 34, 94) (See Wada Fig. 1, Fig. 4, Fig. 9, Fig. 23, Fig. 24, ¶ 0032-¶ 0038, ¶ 0040, ¶ 0042-¶ 0047, ¶ 0063, ¶ 0064, ¶ 0092-¶ 0097, ¶ 0212-¶ 0229, Matsunaga Fig. 1, Fig. 7, Fig. 8, ¶ 0002-¶ 0005, ¶ 0023, ¶ 0024, ¶ 0035, ¶ 0052, ¶ 0056, and Harris Fig. 1), where the contact layer for contacts to source, drain, and gate terminals of the transistor structure provides signal path and control to the transistor structure that is well known in the art. Further, the graphene-clad metal interconnect comprises the same/similar dual damascene structures in several intermediate and global levels to provide connection to the top and external of the transistor structure such that the graphene cladding, metal, and graphene cap are repetitively formed throughout the intermediate and global levels, Wada and Matsunaga/Harris do not further disclose etching a portion of the first graphene cap, and a portion of the metal layer, wherein a thickness of the liner is substantially equal to a thickness of the first graphene cap. However, Barth does disclose etching a portion of the first graphene cap (222), and a portion of the metal layer (220), wherein a thickness (5 nm) of the liner (218) is substantially equal to a thickness (5 nm) of the first graphene cap (222) (See Fig. 2, Fig. 10, ¶ 0042, ¶ 0043, ¶ 0045, ¶ 0050, ¶ 0089) and Murray also discloses etching a portion of the first cap (312), and a portion of the metal layer (208) (See Fig. 4, Fig. 5, Fig. 7, ¶ 0026, ¶ 0040, ¶ 0044, ¶ 0049, ¶ 0050). In view of the teachings of Barth and Murray, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wada and Matsunaga/Harris to have etching a portion of the first graphene cap, and a portion of the metal layer, wherein a thickness of the liner is substantially equal to a thickness of the first graphene cap because the textured metal layer aids the adhesion of subsequently formed graphene-clad metal interconnects to further reduce overall via resistance. Further, the liner and the first graphene cap are generally formed from 5 nm to 15/20 nm, where other suitable thicknesses are applicable (See Barth ¶ 0042, ¶ 0043, ¶ 0050 and Murray ¶ 0049). As to claim 2, Wada in view of Matsunaga further discloses wherein forming the graphene-clad metal interconnect (10, 30, 90) further comprises forming the liner (11, 12, 91, 92) adjacent to the first graphene cladding (33a, 93) (See Wada Fig 9, Fig. 23). As to claim 3, Wada in view of Matsunaga further discloses wherein the liner (11, 12, 91, 92) surrounds the first and second graphene claddings (33a, 93) (See Wada Fig 9, Fig. 23). As to claim 4, Wada in view of Matsunaga further discloses wherein the liner (11, 12, 91, 92) surrounds the first graphene cladding (33a, 93) and the second graphene cladding (33a, 93) on surfaces of the opening (96a, 96b/152, 154), and wherein the opening (96a, 96b/152, 154) is a dual damascene opening (96a, 96b/152, 154) (See Wada Fig. 9, Fig. 23 and Matsunaga Fig. 7, Fig. 8). As to claim 5, Wada further discloses wherein forming the liner (11, 12, 91, 92) comprises forming a layer of cobalt, tantalum, ruthenium, and combinations thereof (See ¶ 0035, ¶ 0037). As to claim 6, Wada further discloses wherein forming the graphene-clad metal interconnect (10, 30, 90) comprises selectively forming the second graphene cladding (33a, 93) on the liner (11, 12, 91, 92) (See ¶ 0063). As to claim 7, Wada further discloses wherein selectively forming the second graphene cladding (33a, 93) comprises depositing carbon atomic layers in one or more of a chemical vapor deposition (CVD) process, a plasma vapor deposition (PVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and an atomic layer deposition (ALD) process (See ¶ 0063). As to claim 8, Wada in view of Matsunaga further discloses wherein forming the first and second graphene claddings (33a, 93) and the first and second graphene caps (33b) comprise surrounding the metal fill (14, 34, 94) with a multi-layer graphene film (See ¶ 0038). As to claim 9, Wada further discloses wherein the metal fill (14, 34, 94) comprises one or more of copper, cobalt, tungsten, ruthenium, and tantalum (See ¶ 0040). As to claim 11, although Wada in view of Matsunaga/Harris discloses a method, comprising: forming a transistor (¶ 0042/Transistor level) on a semiconductor substrate (1/200); coupling a contact layer (3/¶ 0023/Tungsten contact plug) to the transistor (¶ 0042/Transistor level); and coupling a patterned metal interconnect (10, 30, 90) to the contact layer (3/¶ 0023/Tungsten contact plug), wherein the patterned metal interconnect (10, 30, 90) comprises: first and second graphene-clad metal lines comprising first and second graphene claddings (33a, 93), respectively, wherein the first graphene cladding (33a, 93) comprises a graphene cap (33a, 93); a liner (11, 12, 91, 92) adjacent to the second graphene cladding (33a, 93); and a via (¶ 0023) coupling the first and second graphene-clad metal lines to each other (See Wada Fig. 1, Fig. 4, Fig. 9, Fig. 23, Fig. 24, ¶ 0032-¶ 0038, ¶ 0040, ¶ 0042-¶ 0047, ¶ 0063, ¶ 0064, ¶ 0092-¶ 0097, ¶ 0212-¶ 0229, Matsunaga Fig. 1, Fig. 7, Fig. 8, ¶ 0002-¶ 0005, ¶ 0023, ¶ 0024, ¶ 0035, ¶ 0052, ¶ 0056, and Harris Fig. 1), where the contact layer to the transistor provides signal path and control to the transistor that is well known in the art. Further, the contact layer, patterned metal interconnect, and via are provided throughout several intermediate and global levels to provide connections between repetitively formed graphene-clad metal lines to the top and external of the transistor, Wada and Matsunaga/Harris do not further disclose wherein a thickness of the liner is substantially equal to a thickness of the graphene cap and wherein the via is recessed into the first metal line. However, Barth does disclose wherein a thickness (5 nm) of the liner (218) is substantially equal to a thickness (5 nm) of the graphene cap (222) and wherein the via is recessed into the first metal line (220) (See Fig. 2, Fig. 10, ¶ 0042, ¶ 0043, ¶ 0045, ¶ 0050, ¶ 0089) and Murray also discloses wherein the via (110, 120) is recessed into the first metal line (208) (See Fig. 4, Fig. 5, Fig. 7, ¶ 0026, ¶ 0040, ¶ 0044, ¶ 0049, ¶ 0050). In view of the teaching of Barth, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wada and Matsunaga/Harris to have wherein a thickness of the liner is substantially equal to a thickness of the graphene cap and wherein the via is recessed into the first metal line because the textured first metal line aids the adhesion of subsequently formed graphene-clad metal lines to further reduce overall via resistance. Further, the liner and the graphene cap are generally formed from 5 nm to 15/20 nm, where other suitable thicknesses are applicable (See Barth ¶ 0042, ¶ 0043, ¶ 0050 and Murray ¶ 0049). As to claim 12, Wada in view of Matsunaga is discloses further comprising depositing an etch stop layer (6/210, 426) on the first and second graphene-clad metal lines (See Wada Fig. 9, ¶ 0047 and Matsunaga Fig. 1, ¶ 0023, ¶ 0035). As to claim 13, Wada in view of Matsunaga/Harris further discloses wherein the liner (11, 12, 91, 92) is a first liner (11, 12, 91, 92), and coupling the patterned metal interconnect (10, 30, 90) to the contact layer (3/¶ 0023/Tungsten contact plug) comprises: depositing a graphene layer (33a, 93) on the contact layer (3/¶ 0023/Tungsten contact plug); depositing a first metal layer (14, 34, 94) on the graphene layer (33a, 93); removing selected portions of the first metal layer (14, 34, 94) to form a patterned metal line; conformally depositing graphene (33a, 93) on top and sidewall surfaces of the patterned metal line to form the first graphene-clad metal line; conformally depositing an etch stop layer (6/210, 426) over the graphene (33a, 93); depositing an inter-layer dielectric (ILD) (dielectric film of IM, SG, GL/Intermediate, Global metallization) over the etch stop layer (6/210, 426); forming the via (¶ 0023) in the ILD (dielectric film of IM, SG, GL/Intermediate, Global metallization), the etch stop layer (6/210, 426), the graphene cap (33a, 93), and the first metal layer (14, 34, 94); conformally depositing a second liner (11, 12, 91, 92) on a bottom and sidewall surfaces of the via (¶ 0023) to form a liner-clad via; and repeating the depositing, removing, and conformally depositing, to form the second graphene-clad metal line in the liner-clad via (See Wada, Matsunaga, and Harris). As to claim 21, although Wada in view of Matsunaga/Harris discloses a method, comprising: forming a transistor structure (¶ 0042/Transistor level) on a semiconductor substrate (1/200); forming a contact layer (3/¶ 0023/Tungsten contact plug) on the transistor structure (¶ 0042/Transistor level); and forming a graphene-clad metal interconnect (10, 30, 90), comprising: depositing a first inter-layer dielectric (ILD) layer (4, 5) over the contact layer (3/¶ 0023/Tungsten contact plug); forming, in the first ILD layer (4, 5), a metal layer (14, 34, 94) that comprises a first graphene cladding (33a, 93) surrounding the metal layer (14, 34, 94); depositing a second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization) over the metal layer (14, 34, 94); forming an opening (96a, 96b/152, 154) in the second ILD layer (dielectric film of IM, SG, GL/Intermediate, Global metallization); conformally depositing a liner (11, 12, 91, 92) on bottom and sidewall surfaces of the opening (96a, 96b/152, 154); and filling the opening (96a, 96b/152, 154) with a metal fill (14, 34, 94) surrounded by a second graphene cladding (33a, 93) (See Wada Fig. 1, Fig. 4, Fig. 9, Fig. 23, Fig. 24, ¶ 0032-¶ 0038, ¶ 0040, ¶ 0042-¶ 0047, ¶ 0063, ¶ 0064, ¶ 0092-¶ 0097, ¶ 0212-¶ 0229, Matsunaga Fig. 1, Fig. 7, Fig. 8, ¶ 0002-¶ 0005, ¶ 0023, ¶ 0024, ¶ 0035, ¶ 0052, ¶ 0056, and Harris Fig. 1), where the contact layer on the transistor structure provides signal path and control to the transistor structure that is well known in the art. Further, the graphene-clad metal interconnect comprises the same/similar dual damascene structures in several intermediate and global levels to provide connection to the top and external of the transistor structure such that the graphene cladding and metal are repetitively formed throughout the intermediate and global levels, Wada and Matsunaga/Harris do not further disclose forming the opening in the metal layer; wherein a thickness first graphene cap is substantially equal to a thickness of the liner . However, Barth does disclose forming the opening in the metal layer (220); wherein a thickness (5 nm) first graphene cap (222) is substantially equal to a thickness (5 nm) of the liner (218) (See Fig. 2, Fig. 10, ¶ 0042, ¶ 0043, ¶ 0045, ¶ 0050, ¶ 0089) and Murray also discloses forming the opening (520, 530) in the metal layer (208) (See Fig. 4, Fig. 5, Fig. 7, ¶ 0026, ¶ 0040, ¶ 0044, ¶ 0049, ¶ 0050). In view of the teaching of Barth, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Wada and Matsunaga/Harris to have forming the opening in the metal layer; wherein a thickness first graphene cap is substantially equal to a thickness of the liner because the textured metal layer aids the adhesion of subsequently formed graphene-clad metal interconnects to further reduce overall via resistance. Further, the liner and the first graphene cap are generally formed from 5 nm to 15/20 nm, where other suitable thicknesses are applicable (See Barth ¶ 0042, ¶ 0043, ¶ 0050 and Murray ¶ 0049). As to claim 22, Wada in view of Matsunaga further discloses wherein forming the graphene-clad metal interconnect (10, 30, 90) further comprises forming the liner (11, 12, 91, 92) adjacent to the first graphene cladding (33a, 93) (See Wada Fig. 9, Fig. 23). As to claim 23, Wada in view of Matsunaga further discloses wherein the liner (11, 12, 91, 92) surrounds the first and second graphene claddings (33a, 93) (See Wada Fig. 9, Fig. 23). As to claim 24, Wada in view of Matsunaga further discloses wherein the liner (11, 12, 91, 92) surrounds the first graphene cladding (33a, 93) and the second graphene cladding (33a, 93) on surfaces of the opening (96a, 96b/152, 154), and wherein the opening (96a, 96b/152, 154) is a dual damascene opening (96a, 96b/152, 154) (See Wada Fig. 9, Fig. 23 and Matsunaga Fig. 7, Fig. 8). As to claim 26, Wada further discloses wherein forming the graphene-clad metal interconnect (10, 30, 90) further comprises selectively forming the second graphene cladding (33a, 93) on the liner (11, 12, 91, 92) (See ¶ 0063). As to claim 27, Wada in view of Barth further discloses wherein the height of the opening in the first graphene cap (33b/222) and the portion of the metal layer (220) is substantially equal to two times the thickness (5 nm) of the first graphene cap (222) (See Barth Fig. 10) (Notes: FIG. 10 of Barth conveys the “substantially equal to two times the thickness” as “substantially” is not particularly defined, where the thickness of the first graphene cap is also adjustable). As to claim 28, Wada in view of Barth further discloses wherein a height of the via (¶ 0023) recessed into the first metal line (220) is substantially equal to the thickness of the graphene cap (222) (See Barth Fig. 10) (Notes: FIG. 10 of Barth conveys the “substantially equal to the thickness of the graphene cap” as “substantially” is not particularly defined, where the thickness of the graphene cap is also adjustable). As to claim 29, Wada in view of Barth further discloses wherein a height of the metal fill (14, 34, 94/220) in the opening is substantially equal to the thickness of the graphene cap (See Barth Fig. 10) (Notes: FIG. 10 of Barth conveys the “substantially equal to the thickness of the graphene cap” as “substantially” is not particularly defined).
Response to Arguments
Applicant's arguments with respect to claims 1, 11, and 21 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/DAVID CHEN/Primary Examiner, Art Unit 2815