DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to claim(s) 8, 24, and 31 filed on 10/12/2026 have been fully considered for examination based on their merits. The previously presented claim(s) 9-17, 25-30, and 32-33 have been considered. Claim(s) 1-7, and 18-23 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 8-13, filed 08/10/2026, with respect to the rejection(s) of claim(s) 8-12, and 16-17 under 35 U.S.C. 102(a)(1) and claim(s) 13-15, and 24-33 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of HUNG2.
Regarding Claim 8. The Applicant argues (see Remarks, page 10) that HUNG (relabeled in this office action, [hereinafter OA] as HUNG1) fails to disclose or suggest at least, “forming a second metal layer on the first metal layer and sidewall of the opening.” The Applicant further argues that HUNG (relabeled in this office action, [hereinafter OA] as HUNG1) in paragraph [0031], the formation of TiSi layer, 32 includes silicon atoms, and cannot be interpreted as the claimed first metal layer. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of HUNG2 teaches in Figure 9, a method of forming a semiconductor device, comprising: forming a second metal layer, 54 on the first metal layer, 50, and the sidewall of the opening, 48, wherein the second metal layer is in contact with the first metal layer is free of silicon, because the first metal layer is preferably composed of Ni or Ti, and the second metal layer is composed of elements such as Ta, Mo etc. which are free of silicon before the silicidation by rapid thermal annealing (RTA) processes.
Regarding Claim 24. The Applicant argues (see Remarks, page 10) that HUNG (relabeled in this OA as HUNG1) fails to disclose or suggest at least, “after forming the second metal layer, performing a first annealing process on the first and second metal layers free of silicon simultaneously, so as to silicidize the first metal layer and the second metal layer and therefore form a metal silicide layer or a metal silicon-germanide layer on the epitaxial layer.” The Applicant further argues that HUNG (relabeled in this office action, [hereinafter OA] as HUNG1) in paragraph [0031], the formation of TiSi layer, 32 includes silicon atoms, and cannot be interpreted as the claimed first metal layer. The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of HUNG2 teaches in Figure 9, a method of forming a semiconductor device, comprising: after forming the second metal layer, 54, performing a rapid thermal annealing (or RTA) on the first and second metal layer (50 and 54 respectively), so as to form a metal silicidize layer on the epitaxial layer. Both the first and second metal layers free of silicon, because the first metal layer is preferably composed of Ni or Ti, and the second metal layer is composed of elements such as Ta, Mo etc. and remain as metal before the silicidation using RTA process as mentioned above.
Regarding Claim 31. The Applicant argues (see Remarks, pages 11-12) that HUNG (relabeled in this OA as HUNG1) fails to disclose or suggest features at least, “the upper metal silicon- germanide including the second metal, and the upper metal silicon-germanide is disposed on and interface with the lower metal silicon-germanide.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection with an embodiment of TSAI (prior art used in the previous OA, filed on 05/08/2026, and relabeled in this OA as TSAIY) is made as mentioned in the above paragraph. For instance, the prior-art of TSAIY teaches in Figure 2, wherein the flowchart, step 28 demonstrates the annealing the metal containing layer (530) as equated to the first metal layer, the second metal layer (532) deposited as depicted in Figure 5C, forms a metal silicide layer (550), including the first semiconductor material (e.g. Si) [0030], and the second semiconductor material (e.g. Ge) [0030], the first metal material, and the second metal material (Figure 2, step 28).
Regarding Claims 9-17, 25-30, and 32-33: The dependent claims 9-17, 25-30, and 32-33 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Specification Objection
The disclosure is objected to because of the following informalities: Claim 8 with amended feature recites, “the first metal layer is free of silicon” and the support is well represented in the Specification. Similarly, Claim 24 with amended feature recites, “the first and the second metal layers free of silicon simultaneously” have no supportive evidence found in the Specification. The Examiner interpreted that the first and second metal remains as metals until the siliciding process begins. The Examiner respectfully seek clarification, “after forming the metal-silicide” no free silicon is possible to coexist with the metal-silicide, since silicide is a compound and silicon is an element and they both are not the same.
Appropriate correction and/or explanation is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8-12, and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching-Wen Hung et al, (hereinafter HUNG1), US 20150243663 A1, in view of Ching-Wen Hung et al, (hereinafter HUNG2), US 9230816 B1.
Regarding Claim 8, HUNG1 teaches a method of forming a semiconductor device in (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) comprising:
providing a substrate (Fig. 1A, 10) having a gate stack (Fig. 1A, 12/22, first metal gate/second metal gate) thereon, an epitaxial layer (Fig. 1A, SiP/SiGe) therein, and a dielectric layer (Fig. 1A, 18/28, ILD) aside the gate stack (Fig. 1A, 12/22, first metal gate/second metal gate) and over the epitaxial layer (Fig. 1A, SiP/SiGe);
forming an opening (Fig. 1C, 191, first opening) through the dielectric layer (Fig. 1A, 18/28, ILD), the opening (Fig. 1C, 191, first opening) exposing the epitaxial layer (Fig. 1A, SiP/SiGe);
forming a first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) on a sidewall and a bottom of the opening (Fig. 1C, 191, first opening), wherein a first melting point of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is about 1700 0C or higher [Note: (According to Wikipedia, the melting point of Titanium nitride is 5,336 oF or 2,947 oC; [https://en.wikipedia.org/wiki/Titanium_nitride]); According to Wikipedia, the melting point of Titanium is 3, 034 oF or 1,668 oC or about 1,700 oC; [https://en.wikipedia.org/wiki/Titanium])];
removing the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) from an upper portion of the sidewall of the opening (Figs. 1E and 1F combined; Ti remains with Si to form TiSi, 32 at the bottom of the opening as in Fig. 1E; the unreacted Ti containing portion of the Ti layer, 31 is removed as in Fig. 1F, [0031]; annotated Figures 1E/1F);
forming a second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]), and a first atomic size (see below the table and the calculations therein) of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is greater (see below the table and the calculations therein) than a second atomic size (see below the table and the calculations therein) of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]).
First Metal layer from the prior art: Ti/TiN
Second Metal layer from the prior art: NiPt/TiN
Considering only Ti atomic size/radius for calculation
Considering only NiPt (Ni-50% and Pt-50%) atonic size/radius for calculation
Reference 1 (Ref 1): https://pubchem.ncbi.nhm.nih.gov/ptable/atomic-radius/
Reference 2 (Ref 2); https://sizes.com/natural/atoms.htm#:~:text=sources&text=32%20(5)%20pages%20751–767%2C%20(1976)
According to Ref 1, atomic radius (pm)
Ti = 187
According to Ref 1, atomic radius (pm)
Ni = 163; or 50%Ni = 81
Pt = 209; or 50%Pt = 104
NiPt = 186
According to Ref 1: Atomic radius of Ti (187 pm) > Atomic radius of NiPt (186 pm)
According to Ref 2, atomic radius (nm)
Ti = 0.146
According to Ref 2, atomic radius (nm)
Ni = 0.124; or 50%Ni = 0.62
Pt = 0.138; or 50%Pt = 0.69
NiPt = 0.131
According to Ref 2: Atomic radius of Ti (0.146 nm) > Atomic radius of NiPt (0.131 nm)
performing a first annealing process (first thermal treatment as in Fig. 1E, [0031]), so as to silicidize (Fig. 1E, 32, first silicide, TiSi, [0031]) the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) and the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) on the epitaxial layer (Fig. 1A, SiP/SiGe) and therefore form a metal silicide layer (Fig. 1I, 34, second silicide, NiSi, [0033]) or a metal silicon-germanide layer (Fig. 1G, 33/SiGe, [0032]) on the epitaxial layer (Fig. 1A, SiP/SiGe);
removing the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) from the sidewall of the opening (Figs. 1I and 1J combined; Ni remains with Si to form NiSi, 34 at the bottom of the opening as in Fig. 1I; the unreacted Ni containing portion of Ni containing layer, 33 is removed as in Fig. 1J, [0031]); and
forming a connector (Fig. 1L, 38, conductor) over the metal silicide layer (Fig. 1E, 32, first silicide, TiSi, [0031]; Fig. 1I, 34, second silicide, NiSi, [0033]) or the metal silicon- germanide layer (Fig. 1G, 33/SiGe, [0032]) in the opening (Fig. 1K, 191/192).
PNG
media_image1.png
952
618
media_image1.png
Greyscale
HUNG1 does not explicitly disclose a method of forming a semiconductor device comprising: forming a second metal layer on the first metal layer and the sidewall of the opening, wherein the second metal layer is in contact with the first metal layer, the first metal layer is free of silicon.
HUNG2 teaches a method of forming a semiconductor device (Figs. 9-10, a method of fabricating semiconductor device, [Col. 1, Lines55-60]) comprising: forming a second metal layer (Fig. 9, 54) on the first metal layer (Fig. 9, 50) and the sidewall (annotated Figure 9, [Col. 4, Lines60-65]) of the opening (Fig. 9, 48), wherein the second metal layer (Fig. 9, 54) is in contact (annotated Figure 9, [Col. 4, Lines 40-42]) with the first metal layer (Fig. 9, 50), the first metal layer (Fig. 9, 50) is free of silicon (Fig. 9, [Col. 4, Lines 48-50]; the first metal layer, 50 is preferably composed of Ni or Ti, [Col. 3, Linwa59-60]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUNG1 to incorporate the teachings of HUNG2 such that a method of forming a semiconductor device comprising: forming a second metal layer on the first metal layer and the sidewall of the opening, wherein the second metal layer is in contact with the first metal layer, the first metal layer is free of silicon, so that the fabrication with the aforementioned steps would mitigate the loss of epitaxial layer loss, thereby enhancing the performance of the FinFET device (HUNG2, [Col. 1, Lines 25-30]).
PNG
media_image2.png
874
1003
media_image2.png
Greyscale
Regarding Claim 9, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) comprises Mo, V, Cr, Zr, Nb, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Zr, a combination including two of these metals, or a combination including three of these metals (See Wikipedia [https://en.wikipedia.org/wiki/Group_4_element]: Titanium (Ti) in prior art is the same Group 4 elements like Zirconium (Zr), or Hafnium (Hf) as claimed in Claim 9). It should be noted that substituting (group 4 titanium group elements, Zr, Hf) for (Ti) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 10, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the second melting point of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) is less than 1700 oC (See Stanford Advanced Materials datasheet [https://www.samaterials.com/st6572-nickel-platinum-target.html] for melting point of Nickel Platinum (NiPt) which is in the range of 1400-1650 oC).
Regarding Claim 11, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the second metal layer comprises Ni, Pt, Pd, Ti, Co, Sc, a combination (Fig. 1H, NiPt/TiN, [0033]) including two of these metals, or a combination including three of these metals.
Regarding Claim 12, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first annealing process is performed at a temperature ranging from about 180 °C to 280 °C (the second thermal treatment, 280 oC, second temperature for forming NiSi (first step), [0034]).
Regarding Claim 16, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), further comprising forming an etching stop layer (Figs. 1A/4A, 16/26, CESL) between the gate stack (Figs. 1A/4A, 12/22, firs/second metal gate) and the dielectric layer (Figs. 1A/4A, 18/28, ILD layer) and between the dielectric layer (Figs. 1A/4A, 18/28, ILD layer) and the epitaxial layer (Figs. 1A/4A, SiP/SiGe), wherein the opening (Figs. 1C/4C, 191, first openings) further penetrates through the etching stop layer (Figs. 1A/1C/4A/4C, 16/26, CESL).
Regarding Claim 17, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), further comprising performing a second annealing process to the epitaxial layer at a temperature ranging from about 400 °C to 480 "C (the substrate, 10 with the first silicide, 32 in the first openings, 191 and the second silicide, 34 in the second openings, 192, are subjected to the third thermal treatment, 450 oC, [0034]) after removing the second metal layer (Fig. 1J, Ni containing layer, 33 is removed, [0034]) and before forming the connector (Fig. 1L, 38, conductors, [0035]).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG1, in view of HUNG2 as applied to claims 8-12, and 16-17 above, and further in view of Yan-Ming Tsai et al, (hereinafter TSAIY), US 20200083100 A1.
Regarding Claim 13, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 as modified by HUNG2 does not disclose the method, wherein forming the epitaxial layer comprises performing a heavily doping process during an epitaxial growth process.
TSAIY teaches in Figure 1, the method (Figs. 1-3, method for manufacturing a semiconductor structure, [0006-0008]), wherein forming the epitaxial layer (Fig. 5C, 510, epitaxial structure) comprises performing a heavily doping process during an epitaxial growth process (in some embodiments, that boron is over-doped in the epitaxial structure, [0045]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUNG1 as modified by HUNG2 to incorporate the teachings of TSAIY such that the method, wherein forming the epitaxial layer comprises performing a heavily doping process during an epitaxial growth process, so that the over-doping of boron in the epitaxial structure for improving contact resistance in the epitaxial structure, interstitials or vacancies that have been created (TSAIY, [0045]).
Regarding Claim 14, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 as modified by HUNG2 does not disclose the method, further comprising, after forming the opening and before forming the first metal layer, performing a heavily doping process to the epitaxial layer.
TSAIY teaches in Figure 1, the method (Figs. 1-3, method for manufacturing a semiconductor structure, [0006-0008]), further comprising, after forming the opening (Fig. 4A, 426, source/drain, [0023]) and before forming the first metal layer (Fig. 3, 34; Fig. 4B, 430), performing a heavily doping process to the epitaxial layer (Fig. 3, 32; Fig. 4A, 410, [0023-0024]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUNG1 as modified by HUNG2 to incorporate the teachings of TSAIY such that the method, further comprising, after forming the opening and before forming the first metal layer, performing a heavily doping process to the epitaxial layer, so that the over-doping of boron in the epitaxial structure for improving contact resistance in the epitaxial structure, interstitials or vacancies that have been created (TSAIY, [0045]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG1, in view of HUNG2 as applied to claims 8-12, and 16-17 above, and further in view of Chung-Hwan Shin et al, (hereinafter SHIN), US 20130316535 A1.
Regarding Claim 15, HUNG1 as modified by HUNG2 teaches the method of claim 8.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), further comprising: forming the opening (Fig. 1C, 191, first opening) and forming the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]).
HUNG1 as modified by HUNG2 does not disclose the method, further comprising, after forming the opening and before forming the first metal layer, performing a pre-amorphous implant process to the epitaxial layer.
SHIN teaches the method (Figs. 11-16, methods of fabricating the semiconductor device, 2, [0078]) of claim 8 further comprising: after forming the opening (Fig. 12, 161a, contact hole/opening, [0079]) and before forming the first metal layer (Figs. 16A/16B, a metal layer can be formed on the amorphized elevated source/drain. 102, [0085]), performing a pre-amorphous implant process (Fig. 14A/14B, 199, PAI/pre-amorphization implant, [0081]) to the epitaxial layer (Fig. 14A, 142, [0054]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUNG1 as modified by HUNG2 to incorporate the teachings of SHIN such that a method, further comprising: after forming the opening and before forming the first metal layer, performing a pre-amorphous implant process to the epitaxial layer, so that the pre-amorphization implant can promote the formation of the amorphous portion (152a) to have a lower profile that is curved which in turn can promote the formation of the metal silicide also to have a curved-sectional profile, particularly at a central potion thereof (SHIN, [0081], [0086]).
Claim(s) 24, and 26-30, is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG1 as applied to claims 8-12, and 16-17 above, in view of Pushkar Ranade, (hereinafter RANADE), US 20090001588 A1, and further in view of HUNG2 as applied to claims 8-12, and 16-17 above.
Regarding Claim 24, HUNG1 teaches a method of forming a semiconductor device in (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) comprising:
providing a substrate (Fig. 1A, 10) having a gate stack (Fig. 1A, 12/22, first metal gate/second metal gate) thereon, an epitaxial layer (Fig. 1A, SiP/SiGe) therein, and a dielectric layer (Fig. 1A, 18/28, ILD) aside the gate stack (Fig. 1A, 12/22, first metal gate/second metal gate) and over the epitaxial layer (Fig. 1A, SiP/SiGe);
forming an opening (Fig. 1C, 191, first opening) through the dielectric layer (Fig. 1A, 18/28, ILD), the opening (Fig. 1C, 191, first opening) exposing the epitaxial layer (Fig. 1A, SiP/SiGe);
forming a first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) on a sidewall and a bottom of the opening (Fig. 1C, 191, first opening), wherein a first melting point of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is about 1700 0C or higher [Note: (According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium_nitride]; the melting point of Titanium nitride is 5,336 oF or 2,947 oC); According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium ]; the melting point of Titanium is 3, 034 oF or 1,668 oC or about 1,700 oC)];
removing the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) from an upper portion of the sidewall of the opening (Figs. 1E and 1F combined; Ti remains with Si to form TiSi, 32 at the bottom of the opening as in Fig. 1E; the unreacted Ti containing portion of the Ti layer, 31 is removed as in Fig. 1F, [0031]; annotated Figures 1E/1F) by an etching process (Fig. 1F, 31, Ti-containing layer removal process, [0031]);
forming a second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) on the sidewall and the bottom of the opening (Fig. 1C, 191, first opening), wherein the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) is in contact (annotated Figure 1H, 33 in contact with 31) with the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]), and a first atomic size (see below the table and the calculations therein) of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is greater (see below the table and the calculations therein) than a second atomic size (see below the table and the calculations therein) of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]).
First Metal layer from the prior art: Ti/TiN
Second Metal layer from the prior art: NiPt/TiN
Considering only Ti atomic size/radius for calculation
Considering only NiPt (Ni-50% and Pt-50%) atonic size/radius for calculation
Reference 1 (Ref 1): https://pubchem.ncbi.nhm.nih.gov/ptable/atomic-radius/
Reference 2 (Ref 2); https://sizes.com/natural/atoms.htm#:~:text=sources&text=32%20(5)%20pages%20751–767%2C%20(1976)
According to Ref 1, atomic radius (pm)
Ti = 187
According to Ref 1, atomic radius (pm)
Ni = 163; or 50%Ni = 81
Pt = 209; or 50%Pt = 104
NiPt = 186
According to Ref 1: Atomic radius of Ti (187 pm) > Atomic radius of NiPt (186 pm)
According to Ref 2, atomic radius (nm)
Ti = 0.146
According to Ref 2, atomic radius (nm)
Ni = 0.124; or 50%Ni = 0.62
Pt = 0.138; or 50%Pt = 0.69
NiPt = 0.131
According to Ref 2: Atomic radius of Ti (0.146 nm) > Atomic radius of NiPt (0.131 nm)
after forming the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]), performing a first annealing process (first thermal treatment as in Fig. 1E, [0031]), so as to silicidize (Fig. 1E, 32, first silicide, TiSi, [0031]) the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) and the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) on the epitaxial layer (Fig. 1A, SiP/SiGe) and therefore form a metal silicide layer (Fig. 1I, 34, second silicide, NiSi, [0033]) or a metal silicon-germanide layer (Fig. 1G, 33/SiGe, [0032]) on the epitaxial layer (Fig. 1A, SiP/SiGe);
HUNG1 does not explicitly disclose a method of forming a semiconductor device comprising: removing the first metal layer from the sidewall of the opening by an etching process.
RANADE teaches a method of forming a semiconductor device (Fig. 2, 200, a method to provide silicides on a single semiconductor wafer, [0010]) comprising: removing the first metal layer from the sidewall of the opening by an etching process (Fig. 2, 204, etch out a portion of second metal layer, [0012]; see also from Fig. 1A to Fig. 1B, the 204 operation of etching to removing the metal layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUNG1 to incorporate the teachings of RANADE such that a method of forming a semiconductor device comprising: removing the first metal layer from the sidewall of the opening by an etching process, so that a monolayer or first metal silicide can be accomplished simultaneously with the bi-metal or bi-layer silicide on the single silicon wafer (RANADE, Figs. 1A-1D, [0010-0012]).
Thought HUNG1 teaches the method that involves two annealing processes for siliciding the first and metal layers separately, HUNG1 as modified by RANADE does not explicitly disclose a method of formatting a semiconductor device, comprising: after forming the second metal layer, performing a first annealing process on the first and second metal layers free of silicon simultaneously, so as to silicidize the first metal layer and the second metal layer and therefore form a metal silicide layer or a metal silicon-germanide layer on the epitaxial layer.
HUNG2 teaches a method of forming a semiconductor device (Figs. 9-10, a method of fabricating semiconductor device, [Col. 1, Lines 55-60]), comprising: after forming the second metal layer (Fig. 9, 54), performing a first annealing process (Fig. 9, RTA (Rapid Thermal Annealing), [Col. 4, Lines 43-49]), on the first (Fig. 9, 50) and second metal layers (Fig. 9, 54) free of silicon (Fig. 9, [Col. 4, Lines 48-50]; the first metal layer, 50 is preferably composed of Ni or Ti, [Col. 3, Lines 59-60]) simultaneously, so as to silicidize ([Col. 4, Lines 43-49]) the first metal layer (Fig. 9, 50) and the second metal layer (Fig. 9, 54) on the epitaxial layer (Fig. 9, 28) and therefore form a metal silicide layer (Fig. 9, 52) or a metal silicon-germanide layer on the epitaxial layer (Fig. 9, 28).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUNG1 to incorporate the teachings of RANADE such that a method of forming a semiconductor device comprising: after forming the second metal layer, performing a first annealing process on the first and second metal layers free of silicon simultaneously, so as to silicidize the first metal layer and the second metal layer and therefore form a metal silicide layer or a metal silicon-germanide layer on the epitaxial layer. The said fabrication with the aforementioned steps would mitigate the loss of epitaxial layer loss, thereby enhancing the performance of the FinFET device (HUNG2, [Col. 1, Lines 25-30]).
PNG
media_image2.png
874
1003
media_image2.png
Greyscale
Regarding Claim 26, HUNG1 as modified by RANADE and HUNG2 teaches the method of claim 24.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein a first melting point of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is different from a second melting point of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]). [Note: (According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium_nitride]; the melting point of Titanium nitride is 5,336 oF or 2,947 oC;); According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium]; the melting point of Titanium is 3, 034 oF or 1,668 oC or about 1,700 oC); (See Stanford Advanced Materials datasheet, [https://www.samaterials.com/st6572-nickel-platinum-target.html]; for melting point of Nickel Platinum (NiPt) which is in the range of 1400-1650 oC)].
Regarding Claim 27, HUNG1 as modified by RANADE and HUNG2 teaches the method of claim 26.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first melting point of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is 1700 °C or higher [Note: (According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium_nitride]; the melting point of Titanium nitride is 5,336 oF or 2,947 oC)Error! Bookmark not defined.; According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium]; the melting point of Titanium is 3, 034 oF or 1,668 oC or about 1,700 oC)], and the second melting point of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033])is less than 1700 °C [Note: See Stanford Advanced Materials datasheet, [https://www.samaterials.com/st6572-nickel-platinum-target.html]; for melting point of Nickel Platinum (NiPt) which is in the range of 1400-1650 oC;].
Regarding Claim 28, HUNG1 as modified by RANADE and HUNG2 teaches the method of claim 24.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) comprises Mo, V, Cr, Zr, Nb, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Zr, a combination including two of these metals, or a combination including three of these metals (See Wikipedia [https://en.wikipedia.org/wiki/Group_4_element]: Titanium (Ti) in prior art is the same Group 4 elements like Zirconium (Zr), or Hafnium (Hf) as claimed in Claim 28). It should be noted that substituting (group 4 titanium group elements, Zr, Hf) for (Ti) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 29, HUNG1 as modified by RANADE and HUNG2 teaches the method of claim 24.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first atomic size of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) greater than 0.25 nm (see table below), and the second atomic size of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) is less than 0.25 nm (see table below).
First Metal layer from the prior art: Ti/TiN
Second Metal layer from the prior art: NiPt/TiN
Considering only Ti atomic size/radius for calculation
Considering only Ni or Pt (Ni-50% and Pt-50%) atonic size/radius for calculation
Reference 1 (Ref 1): https://pubchem.ncbi.nhm.nih.gov/ptable/atomic-radius/
According to Ref 1, atomic radius
Ti = 187 pm or 0.187 nm
According to Ref 1, atomic radius
Ni = 163; or 50%Ni = 81 pm
Pt = 209; or 50%Pt = 104 pm
NiPt = 186 pm or 0.186 nm < 0.25 nm
According to Ref 1: Atomic radius of the second metal layer, NiPt (0.186 nm) which is less than 0.25 nm as claimed in claim 29.
According to Ref 1: Atomic radius of the first metal layer, Ti (0.187 nm) which is not greater than 0.25 nm as claim 29; (Titanium (Ti) in prior art is the same Group 4 elements like Zirconium (Zr), or Hafnium (Hf) or their combinations; therefore, the element with atomic size greater than 0.25 nm can be easily substituted for Ti as a first metal layer; Moreover Titanium nitride as a metal layer increase the atomic size of titanium). It should be noted that substituting (Zr [22nm], Hf [21nm], Yb [0.24nm], Sr [0.25nm]) for (Ti) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 30, HUNG1 as modified by RANADE and HUNG2 teaches the method of claim 24.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first annealing process is performed at a temperature ranging from about 180 "C to 280 "C (the second thermal treatment, 280 oC, second temperature for forming NiSi (first step), [0034]).
Claim(s) 25, is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG1 in view of RANADE, and HUNG2 as applied to claims 24, and 26-30, above, and further in view of TSAIY as applied to claims 13-14 above.
Regarding Claim 25, HUNG1 as modified by RANADE and HUNG2 teaches the method of claim 24.
HUNG1 as modified by RANADE and HUNG2 does not disclose the method, further comprising, after the first annealing process: removing the second metal layer from the sidewall of the opening; and forming a connector over the metal silicide layer or the metal silicon- germanide layer in the opening.
TSAIY teaches in Figure 1, a method (Figs. 1-3, method for manufacturing a semiconductor structure, [0006-0008]) of claim 24, further comprising, after the first annealing process:
removing the second metal layer from the sidewall of the opening (Fig. 5E, un-reacted portion of the implanted metal-containing layer, 532 is removed, [0034]); and
forming a connector (Fig. 5E, 560, conductive plug lands, [0034]) over the metal silicide layer or the metal silicon- germanide layer (Fig. 5E, 510, metal silicide layer, [0034]) in the opening (Fig. 5A, 526, Si/Ge source/drain region, [0030]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUNG1 as modified by RANADE and HUNG2 to incorporate the teachings of TSAIY such that the method, further comprising, after the first annealing process: removing the second metal layer from the sidewall of the opening; and forming a connector over the metal silicide layer or the metal silicon- germanide layer in the opening, so that the source/drain (526) includes the epitaxial structure (510 serving as a source/drain stressor (TSAIY, [0030]).
Claim(s) 31-33, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chia Ching Tsai et al, (hereinafter TSAIC), US 20180315652 A1, in view of HUNG1 as applied to claims 8-12, and 16-17 above, TSAIY as applied to claims 13-14.
Regarding Claim 31, TSAIC teaches in Figure 12, a method of forming a semiconductor device (Fig. 20, 200, flow chart of a process forming a FinFET), comprising:
providing a substrate (20) having a gate stack (64, replacement gate stack) thereon, an epitaxial layer (42, epitaxy regions) therein, and a dielectric layer (67) aside the gate stack (64, replacement gate stack) and over the epitaxial layer (42, epitaxy regions);
forming an opening (68, contact openings) through the dielectric layer (67), the opening (68, contact openings) exposing the epitaxial layer (42, epitaxy regions);
forming a first layer including a first metal layer (Fig. 11, 72, metal layer) on a sidewall and a bottom (annotated Figure 11) of the opening (68, contact openings).
PNG
media_image3.png
771
930
media_image3.png
Greyscale
TSAIC does not teach a semiconductor device comprising: removing the first layer from the sidewall of the opening; forming a second layer including a second metal on the sidewall and the bottom of the opening; after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal; removing the second layer from the sidewall of the; and forming a connector over the bi-layer structure in the opening.
HUNG1 teaches a method of forming a semiconductor device in (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) comprising:
removing the first layer from the sidewall of the opening (Figs. 1E and 1F combined; Ti remains with Si to form TiSi, 32 at the bottom of the opening as in Fig. 1E; the unreacted Ti containing portion of the Ti layer, 31 is removed as in Fig. 1F, [0031]);
forming a second layer including a second metal on the sidewall and the bottom of the opening Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]);
after forming the second layer, performing a first annealing process (first thermal treatment as in Fig. 1E, [0031]), so as to silicidize the first layer (Fig. 1E, 32, first silicide, TiSi, [0031]) and the second layer on the epitaxial layer (Fig. 1I, 34, second silicide, NiSi, [0033]) and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal (Fig. 1G, 31/SiP, [0032], [0065]), and an upper metal silicon- germanide including the second metal (Fig. 1G, 33/SiGe, [0032], [0065]);
removing the second layer from the sidewall of the opening (Figs. 1I and 1J combined; Ni remains with Si to form NiSi, 34 at the bottom of the opening as in Fig. 1I; the unreacted Ni containing portion of Ni containing layer, 33 is removed as in Fig. 1J, [0031]); and
forming a connector (Fig. 1L, 38, conductor) over the bi-layer structure (Fig. 1G, 33/SiGe, [0032], [0065]) in the opening. (Fig. 1K, 191).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified TSAIC to incorporate the teachings of HUNG1 such that a method of forming a semiconductor device comprising: removing the first layer from the sidewall of the opening; forming a second layer including a second metal on the sidewall and the bottom of the opening; after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal; removing the second layer from the sidewall of the; and forming a connector over the bi-layer structure in the opening. The aforementioned arrangements enable the reduction of feature size, improvements of the rate, the efficiency, the density and the cost per integrated circuit unit with low resistance that satisfy the electrical requirements (HUNG, [0004]).
Though TSAIC as modified by HUNG1 teaches the forming, removing of first and second metal layers and performing an annealing process to form the first silicide and second silicide layers, TSAIC as modified by HUNG1 does not explicitly disclose the performing of a first annealing process after forming of first and second metal layers in a specific sequence as listed in the Claim 31. TSAIC as modified by HUNG does not explicitly disclose a method of forming a semiconductor device comprising: forming a first layer including a first metal on a sidewall and a bottom of the opening; removing the first layer from the sidewall of the opening; forming a second layer including a second metal on the sidewall and the bottom of the opening; after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal, and the upper metal silicon-germanide is disposed on and interface with the lower metal silicon-germanide; removing the second layer from the sidewall of the opening.
TSAIY teaches in Figure 1, a method of forming a semiconductor device (Figs. 1-3, method for manufacturing a semiconductor structure, [0006-0008]) comprising:
forming a first metal layer including a first metal on a sidewall of the opening (Fig. 1, Step 14, depositing a metal layer including a first metal material);
removing the first layer from the sidewall of the opening (Figs. 4D/5E, absence of 430/530);
forming a second layer including a second metal on the sidewall and the bottom of the opening (Fig. 1, Step 14, depositing a metal layer including a second metal material);
after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal (Fig. 1, Step 16, annealing the metal layer and epitaxial structure to form a metal silicide layer on the epitaxial structure), and the upper metal silicon-germanide is disposed on and interface with the lower metal silicon-germanide (Fig. 2, step 28, [0033]);
removing the second layer from the sidewall of the opening (Fig. 5E, un-reacted portion of the implanted metal-containing layer, 532 is removed, [0034]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have TSAIC as modified by HUNG1 to incorporate the teachings of TSAIYsuch that a method of forming a semiconductor device comprising: forming a first layer including a first metal on a sidewall and a bottom of the opening; removing the first layer from the sidewall of the opening; forming a second layer including a second metal on the sidewall and the bottom of the opening; after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal, and the upper metal silicon-germanide is disposed on and interface with the lower metal silicon-germanide; removing the second layer from the sidewall of the opening. The aforementioned sequence of method of manufacturing a semiconductor structure are mere implementation of different features and ease up the process flow, such as annealing with wider temperature ranges (e.g. 400 oC-900 oC) and quaternary metal-silicide or metal-silicon germanide, TiXSiGe formation etc. (TSAIY, [0013], [0033]).
Regarding Claim 32, TSAIC as modified by HUNG1, and TSAIY teaches the method of claim 31.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first annealing process is performed at a temperature ranging from about 180 "C to 280 "C (the second thermal treatment, 280 oC, second temperature for forming NiSi (first step), [0034]).
Regarding Claim 33, TSAIC as modified by HUNG1, and TSAIY teaches the method of claim 31.
HUNG1 further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), further comprising performing a second annealing process to the epitaxial layer at a temperature ranging from about 400 °C to 480 °C the substrate, 10 with the first silicide, 32 in the first openings, 191 and the second silicide, 34 in the second openings, 192, are subjected to the third thermal treatment, 450 oC, [0034]) after removing the second metal layer (Fig. 1J, Ni containing layer, 33 is removed, [0034]) and before forming the connector (Fig. 1L, 38, conductors, [0035]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20180012975 A1 – Figure 11
STATEMENT OF RELEVANCE – A schematically illustrate a method of forming a semiconductor device, wherein the barrier layer (501, include Ti/TiN layer, [0042]) equated as a second metal layer, is formed and in contact with the underlying protection layer (354) equated as a first metal layer, both are free of Silicon.
US 20190097012 A1 – Figure 14
STATEMENT OF RELEVANCE – A cross-sectional views of various intermediate stages showing a method of forming the semiconductor device structure, wherein the metal-silicide or germanide layer, (142a) is formed over t he bottom of each of the contact openings (132).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
Prosecution Insights