DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/24/2025 has been entered.
Specification
The amendment to the specification for the paragraphs [0044] and [0072] filed on 12/24/2025 has been accepted and entered.
Response to Amendment
The amendments with respect to claims 8, 24, 28, and 29 filed on 12/24/2025 have been fully considered for examination based on their merits. The previously presented claims 9-17, 25-27, and 30-33 have been considered. Claims 1–7, and 18–23 are canceled.
Response to Arguments
Applicant's arguments (see Remarks, pages 9-12) filed 12/24/2025 have been fully considered but they are not persuasive.
Regarding Independent Claims 8, and 24. Applicant argues that the prior art does not disclose or suggest the amended features, now recites, “a method of forming a semiconductor device comprising a first atomic size of the first metal layer is greater than a second atomic size of the second metal layer.” Applicant further argues with an evidence of paragraph [0044] of the instant application that the criticality of the aforementioned amended feature of the selection of atomic size is crucial and yield unexpected effect over the cited references. The Examiner agrees with the criticality features of the atomic size, which overcomes the art of the previous rejection. However, upon further review of the prior art HUNG, the atomic size of the first metal layer (Ti-containing layer, 31, such as Ti/TiN) is greater than the atomic size of the second metal layer (Ni- containing layer, 33, such as NiPt/TiN). Therefore, the Examiner maintains the rejection using the prior art HUNG in this Office Action.
The dependent Claims 9-17, and 25-30 are treated in the same manner as mentioned above.
Regarding Independent Claim 31. The Applicant argues that “the bi-layer structure comprises a lower metal silicon-germanide including the first metal, and an upper metal silicon-germanide including the second metal, which are considered novel and overcome the art of rejection. However, upon further review of the prior art, HUNG teaches the first metal layer or the Ti-containing layer, 31 (such as Ti/TiN) is thermally treated with the portion of the first silicide, 32 as shown in Figure 1E and discussed in paragraph [0031], unambiguously defines the SiP or SiGe layer with Ti containing metal for the bi-layer formation as claimed in Claim 31. Similarly, HUNG teaches the second metal layer or the Ni-containing layer, 33 (such as NiPt/TiN) is thermally treated with the portion of the second silicide, 34 as shown in Figure 1J and discussed in paragraph [0034], unambiguously defines the SiP or SiGe layer with Ni containing metal for the bi-layer formation as claimed in Claim 31. The prior art previously used to reject claim 31 is indeed disclose or suggest the metal layer that contributes to the formation of the bi-layer structure, SiP/SiGe as claimed by the instant application. The Examiner, therefore, maintains the art of rejection with respect to the bi-layer structure of claim 31.
The dependent Claims 32, and 33 are treated in the same manner as mentioned above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8-12, and 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching-Wen Hung et al, (hereinafter HUNG), US 20150243663 A1 (Cited in the Previous Office Action).
Regarding Claim 8, HUNG teaches a method of forming a semiconductor device in (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) comprising:
providing a substrate (Fig. 1A, 10) having a gate stack (Fig. 1A, 12/22, first metal gate/second metal gate) thereon, an epitaxial layer (Fig. 1A, SiP/SiGe) therein, and a dielectric layer (Fig. 1A, 18/28, ILD) aside the gate stack (Fig. 1A, 12/22, first metal gate/second metal gate) and over the epitaxial layer (Fig. 1A, SiP/SiGe);
forming an opening (Fig. 1C, 191, first opening) through the dielectric layer (Fig. 1A, 18/28, ILD), the opening (Fig. 1C, 191, first opening) exposing the epitaxial layer (Fig. 1A, SiP/SiGe);
forming a first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) on a sidewall and a bottom of the opening (Fig. 1C, 191, first opening), wherein a first melting point of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is about 1700 0C or higher [Note: (According to Wikipedia, the melting point of Titanium nitride is 5,336 oF or 2,947 oC; [https://en.wikipedia.org/wiki/Titanium_nitride]); According to Wikipedia, the melting point of Titanium is 3, 034 oF or 1,668 oC or about 1,700 oC; [https://en.wikipedia.org/wiki/Titanium])];
removing the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) from an upper portion of the sidewall of the opening (Figs. 1E and 1F combined; Ti remains with Si to form TiSi, 32 at the bottom of the opening as in Fig. 1E; the unreacted Ti containing portion of the Ti layer, 31 is removed as in Fig. 1F, [0031]; annotated Figures 1E/1F);
forming a second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) on the sidewall and the bottom of the opening (Fig. 1C, 191, first opening), wherein the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) is in contact (annotated Figure 1H, 33 in contact with 31) with the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]), and a first atomic size (see below the table and the calculations therein) of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is greater (see below the table and the calculations therein) than a second atomic size (see below the table and the calculations therein) of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]).
First Metal layer from the prior art: Ti/TiN
Second Metal layer from the prior art: NiPt/TiN
Considering only Ti atomic size/radius for calculation
Considering only NiPt (Ni-50% and Pt-50%) atonic size/radius for calculation
Reference 1 (Ref 1): https://pubchem.ncbi.nhm.nih.gov/ptable/atomic-radius/
Reference 2 (Ref 2); https://sizes.com/natural/atoms.htm#:~:text=sources&text=32%20(5)%20pages%20751–767%2C%20(1976)
According to Ref 1, atomic radius (pm)
Ti = 187
According to Ref 1, atomic radius (pm)
Ni = 163; or 50%Ni = 81
Pt = 209; or 50%Pt = 104
NiPt = 186
According to Ref 1: Atomic radius of Ti (187 pm) > Atomic radius of NiPt (186 pm)
According to Ref 2, atomic radius (nm)
Ti = 0.146
According to Ref 2, atomic radius (nm)
Ni = 0.124; or 50%Ni = 0.62
Pt = 0.138; or 50%Pt = 0.69
NiPt = 0.131
According to Ref 2: Atomic radius of Ti (0.146 nm) > Atomic radius of NiPt (0.131 nm)
performing a first annealing process (first thermal treatment as in Fig. 1E, [0031]), so as to silicidize (Fig. 1E, 32, first silicide, TiSi, [0031]) the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) and the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) on the epitaxial layer (Fig. 1A, SiP/SiGe) and therefore form a metal silicide layer (Fig. 1I, 34, second silicide, NiSi, [0033]) or a metal silicon-germanide layer (Fig. 1G, 33/SiGe, [0032]) on the epitaxial layer (Fig. 1A, SiP/SiGe);
removing the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) from the sidewall of the opening (Figs. 1I and 1J combined; Ni remains with Si to form NiSi, 34 at the bottom of the opening as in Fig. 1I; the unreacted Ni containing portion of Ni containing layer, 33 is removed as in Fig. 1J, [0031]); and
forming a connector (Fig. 1L, 38, conductor) over the metal silicide layer (Fig. 1E, 32, first silicide, TiSi, [0031]; Fig. 1I, 34, second silicide, NiSi, [0033]) or the metal silicon- germanide layer (Fig. 1G, 33/SiGe, [0032]) in the opening (Fig. 1K, 191/192).
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Regarding Claim 9, HUNG teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) of claim 8, wherein the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) comprises Mo, V, Cr, Zr, Nb, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Zr, a combination including two of these metals, or a combination including three of these metals (See Wikipedia [https://en.wikipedia.org/wiki/Group_4_element]: Titanium (Ti) in prior art is the same Group 4 elements like Zirconium (Zr), or Hafnium (Hf) as claimed in Claim 9). It should be noted that substituting (group 4 titanium group elements, Zr, Hf) for (Ti) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 10, HUNG teaches, the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) of claim 8, wherein the second melting point of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) is less than 1700 oC (See Stanford Advanced Materials datasheet [https://www.samaterials.com/st6572-nickel-platinum-target.html] for melting point of Nickel Platinum (NiPt) which is in the range of 1400-1650 oC).
Regarding Claim 11, HUNG teaches, the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) of claim 8, wherein the second metal layer comprises Ni, Pt, Pd, Ti, Co, Sc, a combination (Fig. 1H, NiPt/TiN, [0033]) including two of these metals, or a combination including three of these metals.
Regarding Claim 12, HUNG teaches, the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) of claim 8, wherein the first annealing process is performed at a temperature ranging from about 180 °C to 280 °C (the second thermal treatment, 280 oC, second temperature for forming NiSi (first step), [0034]).
Regarding Claim 16, HUNG teaches, the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) of claim 8, further comprising forming an etching stop layer (Figs. 1A/4A, 16/26, CESL) between the gate stack (Figs. 1A/4A, 12/22, firs/second metal gate) and the dielectric layer (Figs. 1A/4A, 18/28, ILD layer) and between the dielectric layer (Figs. 1A/4A, 18/28, ILD layer) and the epitaxial layer (Figs. 1A/4A, SiP/SiGe), wherein the opening (Figs. 1C/4C, 191, first openings) further penetrates through the etching stop layer (Figs. 1A/1C/4A/4C, 16/26, CESL).
Regarding Claim 17, HUNG teaches, the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) of claim 8, further comprising performing a second annealing process to the epitaxial layer at a temperature ranging from about 400 °C to 480 "C (the substrate, 10 with the first silicide, 32 in the first openings, 191 and the second silicide, 34 in the second openings, 192, are subjected to the third thermal treatment, 450 oC, [0034]) after removing the second metal layer (Fig. 1J, Ni containing layer, 33 is removed, [0034]) and before forming the connector (Fig. 1L, 38, conductors, [0035]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG, in view of Yan-Ming Tsai et al, (hereinafter TSAI-2), US 20200083100 A1 (Cited in the Previous Office Action).
Regarding Claim 13, HUNG teaches the method of claim 8.
HUNG does not disclose the method, wherein forming the epitaxial layer comprises performing a heavily doping process during an epitaxial growth process.
TSAI-2 teaches in Figure 1, the method (Figs. 1-3, method for manufacturing a semiconductor structure, [0006-0008]), wherein forming the epitaxial layer (Fig. 5C, 510, epitaxial structure) comprises performing a heavily doping process during an epitaxial growth process (in some embodiments, that boron is over-doped in the epitaxial structure, [0045]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUNG to incorporate the teachings of TSAI-2 such that the method, wherein forming the epitaxial layer comprises performing a heavily doping process during an epitaxial growth process, so that the over-doping of boron in the epitaxial structure for improving contact resistance in the epitaxial structure, interstitials or vacancies that have been created (TSAI-2, [0045]).
Regarding Claim 14, HUNG teaches the method of claim 8.
HUNG does not disclose the method, further comprising, after forming the opening and before forming the first metal layer, performing a heavily doping process to the epitaxial layer.
TSAI-2 teaches in Figure 1, the method (Figs. 1-3, method for manufacturing a semiconductor structure, [0006-0008]), further comprising, after forming the opening (Fig. 4A, 426, source/drain, [0023]) and before forming the first metal layer (Fig. 3, 34; Fig. 4B, 430), performing a heavily doping process to the epitaxial layer (Fig. 3, 32; Fig. 4A, 410, [0023-0024]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUNG to incorporate the teachings of TSAI-2 such that the method, further comprising, after forming the opening and before forming the first metal layer, performing a heavily doping process to the epitaxial layer, so that the over-doping of boron in the epitaxial structure for improving contact resistance in the epitaxial structure, interstitials or vacancies that have been created (TSAI-2, [0045]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG in view of Chung-Hwan Shin et al, (hereinafter SHIN), US 20130316535 A1 (Cited in the Previous Office Action).
Regarding Claim 15, HUNG teaches the method of claim 8, further comprising: forming the opening (Fig. 1C, 191, first opening) and forming the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]).
HUNG does not disclose the method, further comprising, after forming the opening and before forming the first metal layer, performing a pre-amorphous implant process to the epitaxial layer.
SHIN teaches the method (Figs. 11-16, methods of fabricating the semiconductor device, 2, [0078]) of claim 8 further comprising: after forming the opening (Fig. 12, 161a, contact hole/opening, [0079]) and before forming the first metal layer (Figs. 16A/16B, a metal layer can be formed on the amorphized elevated source/drain. 102, [0085]), performing a pre-amorphous implant process (Fig. 14A/14B, 199, PAI/pre-amorphization implant, [0081]) to the epitaxial layer (Fig. 14A, 142, [0054]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified to incorporate the teachings of SHIN such that a method, further comprising: after forming the opening and before forming the first metal layer, performing a pre-amorphous implant process to the epitaxial layer, so that the pre-amorphization implant can promote the formation of the amorphous portion (152a) to have a lower profile that is curved which in turn can promote the formation of the metal silicide also to have a curved-sectional profile, particularly at a central potion thereof (SHIN, [0081], [0086]).
Claim(s) 24, 26-30, is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG in view of Pushkar Ranade, (hereinafter RANADE), US 20090001588 A1 (Cited in the Previous Office Action).
Regarding Claim 24, HUNG teaches a method of forming a semiconductor device in (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) comprising:
providing a substrate (Fig. 1A, 10) having a gate stack (Fig. 1A, 12/22, first metal gate/second metal gate) thereon, an epitaxial layer (Fig. 1A, SiP/SiGe) therein, and a dielectric layer (Fig. 1A, 18/28, ILD) aside the gate stack (Fig. 1A, 12/22, first metal gate/second metal gate) and over the epitaxial layer (Fig. 1A, SiP/SiGe);
forming an opening (Fig. 1C, 191, first opening) through the dielectric layer (Fig. 1A, 18/28, ILD), the opening (Fig. 1C, 191, first opening) exposing the epitaxial layer (Fig. 1A, SiP/SiGe);
forming a first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) on a sidewall and a bottom of the opening (Fig. 1C, 191, first opening), wherein a first melting point of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is about 1700 0C or higher [Note: (According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium_nitride]; the melting point of Titanium nitride is 5,336 oF or 2,947 oC); According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium ]; the melting point of Titanium is 3, 034 oF or 1,668 oC or about 1,700 oC)];
removing the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) from an upper portion of the sidewall of the opening (Figs. 1E and 1F combined; Ti remains with Si to form TiSi, 32 at the bottom of the opening as in Fig. 1E; the unreacted Ti containing portion of the Ti layer, 31 is removed as in Fig. 1F, [0031]; annotated Figures 1E/1F) by an etching process (Fig. 1F, 31, Ti-containing layer removal process, [0031]);
forming a second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) on the sidewall and the bottom of the opening (Fig. 1C, 191, first opening), wherein the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) is in contact (annotated Figure 1H, 33 in contact with 31) with the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]), and a first atomic size (see below the table and the calculations therein) of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is greater (see below the table and the calculations therein) than a second atomic size (see below the table and the calculations therein) of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]).
First Metal layer from the prior art: Ti/TiN
Second Metal layer from the prior art: NiPt/TiN
Considering only Ti atomic size/radius for calculation
Considering only NiPt (Ni-50% and Pt-50%) atonic size/radius for calculation
Reference 1 (Ref 1): https://pubchem.ncbi.nhm.nih.gov/ptable/atomic-radius/
Reference 2 (Ref 2); https://sizes.com/natural/atoms.htm#:~:text=sources&text=32%20(5)%20pages%20751–767%2C%20(1976)
According to Ref 1, atomic radius (pm)
Ti = 187
According to Ref 1, atomic radius (pm)
Ni = 163; or 50%Ni = 81
Pt = 209; or 50%Pt = 104
NiPt = 186
According to Ref 1: Atomic radius of Ti (187 pm) > Atomic radius of NiPt (186 pm)
According to Ref 2, atomic radius (nm)
Ti = 0.146
According to Ref 2, atomic radius (nm)
Ni = 0.124; or 50%Ni = 0.62
Pt = 0.138; or 50%Pt = 0.69
NiPt = 0.131
According to Ref 2: Atomic radius of Ti (0.146 nm) > Atomic radius of NiPt (0.131 nm)
after forming the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]), performing a first annealing process (first thermal treatment as in Fig. 1E, [0031]), so as to silicidize (Fig. 1E, 32, first silicide, TiSi, [0031]) the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) and the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) on the epitaxial layer (Fig. 1A, SiP/SiGe) and therefore form a metal silicide layer (Fig. 1I, 34, second silicide, NiSi, [0033]) or a metal silicon-germanide layer (Fig. 1G, 33/SiGe, [0032]) on the epitaxial layer (Fig. 1A, SiP/SiGe);
HUNG does not explicitly disclose a method of forming a semiconductor device comprising: removing the first metal layer from the sidewall of the opening by an etching process.
RANADE teaches a method of forming a semiconductor device (Fig. 2, 200, a method to provide silicides on a single semiconductor wafer, [0010]) comprising: removing the first metal layer from the sidewall of the opening by an etching process (Fig. 2, 204, etch out a portion of second metal layer, [0012]; see also from Fig. 1A to Fig. 1B, the 204 operation of etching to removing the metal layer).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified HUNG to incorporate the teachings of RANADE such that a method of forming a semiconductor device comprising: removing the first metal layer from the sidewall of the opening by an etching process, so that a monolayer or first metal silicide can be accomplished simultaneously with the bi-metal or bi-layer silicide on the single silicon wafer (RANADE, Figs. 1A-1D, [0010-0012]).
Regarding Claim 26, HUNG as modified by RANADE teaches the method of claim 24.
HUNG further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein a first melting point of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is different from a second melting point of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]). [Note: (According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium_nitride]; the melting point of Titanium nitride is 5,336 oF or 2,947 oC;); According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium]; the melting point of Titanium is 3, 034 oF or 1,668 oC or about 1,700 oC); (See Stanford Advanced Materials datasheet, [https://www.samaterials.com/st6572-nickel-platinum-target.html]; for melting point of Nickel Platinum (NiPt) which is in the range of 1400-1650 oC)].
Regarding Claim 27, HUNG as modified by RANADE teaches the method of claim 26.
HUNG further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first melting point of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) is 1700 °C or higher [Note: (According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium_nitride]; the melting point of Titanium nitride is 5,336 oF or 2,947 oC)Error! Bookmark not defined.; According to Wikipedia, [https://en.wikipedia.org/wiki/Titanium]; the melting point of Titanium is 3, 034 oF or 1,668 oC or about 1,700 oC)], and the second melting point of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033])is less than 1700 °C [Note: See Stanford Advanced Materials datasheet, [https://www.samaterials.com/st6572-nickel-platinum-target.html]; for melting point of Nickel Platinum (NiPt) which is in the range of 1400-1650 oC;].
Regarding Claim 28, HUNG as modified by RANADE teaches the method of claim 24.
HUNG further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) comprises Mo, V, Cr, Zr, Nb, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Zr, a combination including two of these metals, or a combination including three of these metals (See Wikipedia [https://en.wikipedia.org/wiki/Group_4_element]: Titanium (Ti) in prior art is the same Group 4 elements like Zirconium (Zr), or Hafnium (Hf) as claimed in Claim 28). It should be noted that substituting (group 4 titanium group elements, Zr, Hf) for (Ti) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 29, HUNG as modified by RANADE teaches the method of claim 24.
HUNG further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first atomic size of the first metal layer (Fig. 1D, 31, Ti containing layer, Ti/TiN, [0031]) greater than 0.25 nm (see table below), and the second atomic size of the second metal layer (Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]) is less than 0.25 nm (see table below).
First Metal layer from the prior art: Ti/TiN
Second Metal layer from the prior art: NiPt/TiN
Considering only Ti atomic size/radius for calculation
Considering only Ni or Pt (Ni-50% and Pt-50%) atonic size/radius for calculation
Reference 1 (Ref 1): https://pubchem.ncbi.nhm.nih.gov/ptable/atomic-radius/
According to Ref 1, atomic radius
Ti = 187 pm or 0.187 nm
According to Ref 1, atomic radius
Ni = 163; or 50%Ni = 81 pm
Pt = 209; or 50%Pt = 104 pm
NiPt = 186 pm or 0.186 nm < 0.25 nm
According to Ref 1: Atomic radius of the second metal layer, NiPt (0.186 nm) which is less than 0.25 nm as claimed in claim 29.
According to Ref 1: Atomic radius of the first metal layer, Ti (0.187 nm) which is not greater than 0.25 nm as claim 29; (Titanium (Ti) in prior art is the same Group 4 elements like Zirconium (Zr), or Hafnium (Hf) or their combinations; therefore, the element with atomic size greater than 0.25 nm can be easily substituted for Ti as a first metal layer; Moreover Titanium nitride as a metal layer increase the atomic size of titanium). It should be noted that substituting (Zr [22nm], Hf [21nm], Yb [0.24nm], Sr [0.25nm]) for (Ti) is a simple substitution of one known element for another to obtain predictable results (See MPEP2143).
Regarding Claim 30, HUNG as modified by RANADE teaches the method of claim 24.
HUNG further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first annealing process is performed at a temperature ranging from about 180 "C to 280 "C (the second thermal treatment, 280 oC, second temperature for forming NiSi (first step), [0034]).
Claim(s) 25, is/are rejected under 35 U.S.C. 103 as being unpatentable over HUNG in view of RANADE, further in view of TSAI-2.
Regarding Claim 25, HUNG, as modified by RANADE teaches the method of claim 24.
HUNG as modified by RANADE does not disclose the method, further comprising, after the first annealing process: removing the second metal layer from the sidewall of the opening; and forming a connector over the metal silicide layer or the metal silicon- germanide layer in the opening.
TSAI-2 teaches in Figure 1, a method (Figs. 1-3, method for manufacturing a semiconductor structure, [0006-0008]) of claim 24, further comprising, after the first annealing process:
removing the second metal layer from the sidewall of the opening (Fig. 5E, un-reacted portion of the implanted metal-containing layer, 532 is removed, [0034]); and
forming a connector (Fig. 5E, 560, conductive plug lands, [0034]) over the metal silicide layer or the metal silicon- germanide layer (Fig. 5E, 510, metal silicide layer, [0034]) in the opening (Fig. 5A, 526, Si/Ge source/drain region, [0030]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have HUNG as modified by RANADE to incorporate the teachings of TSAI-2 such that the method, further comprising, after the first annealing process: removing the second metal layer from the sidewall of the opening; and forming a connector over the metal silicide layer or the metal silicon- germanide layer in the opening, so that the source/drain (526) includes the epitaxial structure (510 serving as a source/drain stressor (TSAI-2, [0030]).
Claim(s) 31-33, is/are rejected under 35 U.S.C. 103 as being unpatentable over Chia Ching Tsai et al, (hereinafter TSAI-1), US 20180315652 A1 (Cited in the Previous Office Action), further in view of HUNG, and further in view of TSAI-2.
Regarding Claim 31, TSAI-1 teaches in Figure 12, a method of forming a semiconductor device (Fig. 20, 200, flow chart of a process forming a FinFET), comprising:
providing a substrate (20) having a gate stack (64, replacement gate stack) thereon, an epitaxial layer (42, epitaxy regions) therein, and a dielectric layer (67) aside the gate stack (64, replacement gate stack) and over the epitaxial layer (42, epitaxy regions);
forming an opening (68, contact openings) through the dielectric layer (67), the opening (68, contact openings) exposing the epitaxial layer (42, epitaxy regions);
forming a first metal layer (Fig. 11, 72, metal layer) on a sidewall and a bottom (annotated Figure 11) of the opening (68, contact openings).
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TSAI-1 does not teach a semiconductor device comprising: removing the first layer from the sidewall of the opening; forming a second layer including a second metal on the sidewall and the bottom of the opening; after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal; removing the second layer from the sidewall of the; and forming a connector over the bi-layer structure in the opening.
HUNG teaches a method of forming a semiconductor device in (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]) comprising:
removing the first layer from the sidewall of the opening (Figs. 1E and 1F combined; Ti remains with Si to form TiSi, 32 at the bottom of the opening as in Fig. 1E; the unreacted Ti containing portion of the Ti layer, 31 is removed as in Fig. 1F, [0031]);
forming a second layer including a second metal on the sidewall and the bottom of the opening Fig. 1H, 33, Ni containing layer, Ni/Pt/TiN, [0033]);
after forming the second layer, performing a first annealing process (first thermal treatment as in Fig. 1E, [0031]), so as to silicidize the first layer (Fig. 1E, 32, first silicide, TiSi, [0031]) and the second layer on the epitaxial layer (Fig. 1I, 34, second silicide, NiSi, [0033]) and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal (Fig. 1G, 31/SiP, [0032], [0065]), and an upper metal silicon- germanide including the second metal (Fig. 1G, 33/SiGe, [0032], [0065]);
removing the second layer from the sidewall of the opening (Figs. 1I and 1J combined; Ni remains with Si to form NiSi, 34 at the bottom of the opening as in Fig. 1I; the unreacted Ni containing portion of Ni containing layer, 33 is removed as in Fig. 1J, [0031]); and
forming a connector (Fig. 1L, 38, conductor) over the bi-layer structure (Fig. 1G, 33/SiGe, [0032], [0065]) in the opening. (Fig. 1K, 191).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified TSAI-1 to incorporate the teachings of HUNG such that a method of forming a semiconductor device comprising: removing the first layer from the sidewall of the opening; forming a second layer including a second metal on the sidewall and the bottom of the opening; after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal; removing the second layer from the sidewall of the; and forming a connector over the bi-layer structure in the opening. The aforementioned arrangements enable the reduction of feature size, improvements of the rate, the efficiency, the density and the cost per integrated circuit unit with low resistance that satisfy the electrical requirements (HUNG, [0004]).
Though TSAI-1 as modified by HUNG teaches the forming, removing of first and second metal layers and performing an annealing process to form the first silicide and second silicide layers, TSAI-1 as modified by HUNG does not explicitly disclose the performing of a first annealing process after forming of first and second metal layers in a specific sequence as listed in the Claim 31. TSAI-1 as modified by HUNG does not explicitly disclose a method of forming a semiconductor device comprising: forming a first layer including a first metal on a sidewall of the opening; removing the first layer from the sidewall of the opening; forming a second layer including a second metal on the sidewall and the bottom of the opening; after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal; removing the second layer from the sidewall of the opening.
TSAI-2 teaches in Figure 1, a method of forming a semiconductor device (Figs. 1-3, method for manufacturing a semiconductor structure, [0006-0008]) comprising:
forming a first metal layer including a first metal on a sidewall of the opening (Fig. 1, Step 14, depositing a metal layer including a first metal material);
removing the first layer from the sidewall of the opening (Figs. 4D/5E, absence of 430/530);
forming a second layer including a second metal on the sidewall and the bottom of the opening (Fig. 1, Step 14, depositing a metal layer including a second metal material);
after forming the second layer, performing a first annealing process and the second layer on the epitaxial layer and therefore form a bi-layer structure on the epitaxial layer, wherein the bi-layer structure comprises a lower metal silicon-gerrmanide including the first metal, and an upper metal silicon- germanide including the second metal (Fig. 1, Step 16, annealing the metal layer and epitaxial structure to form a metal silicide layer on the epitaxial structure);
removing the second layer from the sidewall of the opening (Fig. 5E, un-reacted portion of the implanted metal-containing layer, 532 is removed, [0034]).
Therefore, it would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have TSAI-1 as modified by HUNG to incorporate the teachings of TSAI-2 such that a method of forming a semiconductor device comprising: forming a first metal layer; forming a second metal layer, wherein the second metal layer is in contact with the first metal layer; performing a first annealing process, so as to silicidize the first metal layer and the second metal layer on the epitaxial layer and therefore form a metal silicide layer or a metal silicon-germanide layer on the epitaxial layer; removing the second metal layer. The aforementioned sequence of method of manufacturing a semiconductor structure are mere implementation of different features and ease up the process flow, such as annealing with wider temperature ranges (e.g. 400 oC-900 oC) and quaternary metal-silicide or metal-silicon germanide, TiXSiGe formation etc. (TSAI-2, [0013], [0033]).
Regarding Claim 32, TSAI-1 as modified by HUNG, and TSAI-2 teaches the method of claim 31.
HUNG further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), wherein the first annealing process is performed at a temperature ranging from about 180 "C to 280 "C (the second thermal treatment, 280 oC, second temperature for forming NiSi (first step), [0034]).
Regarding Claim 33, TSAI-1 as modified by HUNG, and TSAI-2 teaches the method of claim 31.
HUNG further teaches the method (Figs. 1A-1L, method for manufacturing a semiconductor device, [0024]), further comprising performing a second annealing process to the epitaxial layer at a temperature ranging from about 400 °C to 480 °C the substrate, 10 with the first silicide, 32 in the first openings, 191 and the second silicide, 34 in the second openings, 192, are subjected to the third thermal treatment, 450 oC, [0034]) after removing the second metal layer (Fig. 1J, Ni containing layer, 33 is removed, [0034]) and before forming the connector (Fig. 1L, 38, conductors, [0035])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210184037 A1 – Figure 11
STATEMENT OF RELEVANCE – The silicide metal profile of the MOS transistor at various regions of the device, for example at the horizontal plane is at a level immediately above the interface between capping layer, 44, and the respective underlying epitaxy layer, 42, and in silicide regions, 52.
US 20180337188 A1 – Figure 9, [0030]
STATEMENT OF RELEVANCE – Cross-sectional views in the formation of Fin-Field Transistors (FinFETs) – metal containing conductive layers (162, 262) are formed through deposition and may include a TiN layer, a TaN layer, and another TiN layer respectively, may also include two layers or more than three layers.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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