DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I was elected.
Amendment filed May 05, 2026 is acknowledged. Claims 1-2 have been amended. Non-elected Invention, claims 15-20 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of the Elected Invention, claims 1-14 follows.
Claim Objections
Claims 15 and 17 are objected to because of the following informalities:
Non-elected claims 15 and 17 are marked as “(withdrawn)”. However, claims 15 and 17 had been previously amended. See Amendment filed March 18, 2025.
Therefore, the correct status of claims 15 and 17 is “(withdrawn, previously presented)”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over LIN et al. (US. Pub. No. 2019/0172753) of record, in view of LIM et al. (US. Pub. No. 2021/0036121).
With respect to claim 1, LIN teaches a fin field effect transistor (FinFET) substantially as claimed including:
a semiconductor substrate (12);
a semiconductor fin (14), protruding from the semiconductor substrate;
a gate structure (50) disposed across a first segment of the semiconductor fin (14), wherein the gate structure (50) comprises a gate electrode (46); and
an isolation structure (72) interrupting a continuity of a second segment of the semiconductor fin (14), wherein the isolation structure (72) has a first portion (76) and a second portion (78) stacked on the first portion (76), sidewalls of the first portion are inclined, sidewalls of the second portion (78) are straight such that the second portion (78) has a constant width from top to bottom, and a top surface of the first portion (76) is coplanar with a top surface of the gate electrode (46) of the gate structure (50). (See FIG. 10).
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing sidewalls of the first portion are continuously inclined.
However, LIM teaches a fin field effect transistor including:
an isolation structure interrupting a continuity of a second segment of the semiconductor fin (105), wherein the isolation structure has a first portion (200) and a second portion (195) stacked on the first portion (200), sidewalls of the first portion are continuously inclined, sidewalls of the second portion are straight, and a top surface of the first portion (200) is coplanar with a top surface of the gate structure (160). (See FIG. 6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the sidewalls of the first portion of the isolation structure of LIN being continuously inclined as taught by LIM for the same intended purpose of interrupting the continuity of the semiconductor fin.
Regarding the shape of the first portion of the isolation structure, vertical or incline or straight, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
With respect to claim 2, the width of the second portion (78) of the isolation structure (72) of LIN is greater than a maximum width of the first portion (76) of the isolation structure.
With respect to claim 3, the FinFET of LIN further comprises a first spacer (30) and a second spacer (36), the first spacer (30) is sandwiched between the first portion (76) of the isolation structure (72) and the second spacer (36).
With respect to claim 4, in view of LIM, the first spacer (164) exhibits a triangular shape from a cross-sectional view, and the second spacer (36) of LIN exhibits a rectangular shape from the cross-sectional view.
With respect to claim 5, the second portion (78) of the isolation structure (72) of LIN covers a top surface of the second spacer (36).
With respect to claim 6, the isolation structure (72) of LIN extends below a top surface of the semiconductor substrate (12).
With respect to claim 7, the isolation structure (72) of LIN is parallel to the gate structure (50) from a top view. (FIG. 1).
With respect to claim 8, LIN teaches a fin field effect transistor (FinFET) having a first region and a second region adjacent to the first region, as claimed including:
a semiconductor substrate (12);
semiconductor fins (14) protruding from the semiconductor substrate, wherein the semiconductor fins (14) in the first region are continuous and the semiconductor fins in the second region are fragmented;
gate structures (48, 50) located in the first region, wherein the gate structures are disposed across the semiconductor fins (14), and each of the gate structure comprises a gate electrode (46); and
isolation structures (72) located in the second region, wherein the isolation structures (72) are sandwiched between fragments of the semiconductor fins (14) in the second region, each of the isolation structures has a first portion (76) and a second portion (78) stacked on the first portion, each of the first portions (76) exhibits a trapezoidal shape, lower, from a cross-sectional view, each of the second portions (78) exhibits a rectangular shape from the cross-sectional view, and top surfaces of the first portions (76) are coplanar with top surfaces of the gate electrode (46) of the gate structures (48, 50). (See FIG. 10).
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing the first portions exhibits a trapezoidal shape.
However, LIM teaches a fin field effect transistor including:
isolation structures located in second region, wherein the isolation structures are sandwiched between fragments of semiconductor fins (105) in the second region, each of the isolation structures has a first portion (200) and a second portion (195) stacked on the first portion, each of the first portions (200) exhibits a trapezoidal shape from a cross-sectional view, and top surfaces of the first portions (200) are coplanar with top surfaces of the gate electrode the gate structures (160). See FIG. 6).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first portion of the isolation structure of LIN exhibiting the trapezoidal shape as taught by LIM for the same intended purpose of interrupting the continuity of the semiconductor fin.
Regarding the shape of the isolation structure, trapezoidal, rectangular, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
With respect to claim 9, the FinFET of LIN further comprises a hard mask layer (58) disposed on the gate structures, and a bottom surface of the second portion (78) is coplanar with a bottom surface of the hard mask layer (58).
With respect to claim 10, sidewalls of the second portion (78) of each of the isolation structures (72) of LIN are aligned with sidewalls of the corresponding gate structure from a top view. (FIG. 1).
With respect to claim 11, the FinFET of LIN further comprises first spacers (30) and second spacers (36), each of the first spacers (30) is sandwiched between the first portion (76) of the corresponding isolation structure (72) and the corresponding second spacer (36).
With respect to claim 12, in view of LIM, each of the first spacers (164) exhibits a triangular shape from the cross-sectional view, and each of the second spacer (36) of LIN exhibits a rectangular shape from the cross-sectional view.
With respect to claim 13, the FinFET of LIN further comprises an insulating structure (38) sandwiched between the isolation structures (72) and the gate structures (50).
With respect to claim 14, the insulating structure (38) of LIN extends along a first direction (X), the gate structures (50) and the isolation structures (72) extend along a second direction (Y), and the first direction is perpendicular to the second direction.
Response to Arguments
Applicant's arguments filed January 21, 2026 have been fully considered but they are not persuasive.
Regarding the claim objection
Applicant asserts that claims 15 and 17 has amended to adapt identifier “withdrawn, previously presented”.
However, Applicant should carefully review the amendment filed May 05, 2026. Claims 15 and 17 are identified as “withdrawn”.
The objection is maintained.
Rejection under 35 U.S.C. 103
Regarding independent claim 1, Applicant argues:
Moreover, on page 4 of the Office Action, the Examiner interpreted upper insulating layer 195 of Lim as the second portion of the present application. However, as shown in FIG. 6 of Lim, the upper insulating layer 195 does not have a constant width from top to bottom.
However, contrary to the Applicant’s assertion, as clearly indicated in the rejection, the second portion of the isolation structure is indicated as second portion 78. FIG. 10, LIN clearly shows that the sidewalls of the second portion (78) are straight such that the second portion (78) has a constant width from top to bottom.
PNG
media_image1.png
414
469
media_image1.png
Greyscale
The limitations are met.
Regarding independent claim 8, Applicant argues:
Currently, claim 8 recites the feature of "each of the second portions exhibits a rectangular shape from the cross-sectional view." Applicant respectfully submits that the cited arts Lin and Lim at least fail to disclose the foregoing feature.
Again, as clearly discussed in the rejection, the second portion 78 of the isolation structure 72, as shown in FIG. 10 of LIN, each of the second portions (78) exhibits a rectangular shape from the cross-sectional view.
The limitations are met.
The rejection of all claims are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANH D MAI/Primary Examiner, Art Unit 2893
Prosecution Insights