Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the Amendment and Request for Reconsideration filed February 16, 2026. Claims 1 and 3 have been amended. Claim 14 has been canceled.
Claims 1-13 and 15 are currently pending.
Response to Amendment
The amendments to the claims filed February 16, 2026 have been entered. Applicant’s amendments to the claims have failed to overcome each and every rejection set forth in the Office Action filed December 16, 2025.
Response to Arguments
Applicant's arguments filed February 16, 2026 have been fully considered but they are not persuasive.
Applicant’s arguments against the references individually are not persuasive, as one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Although Applicant is correct that APA is silent regarding forming a first dielectric layer on the metal gates and the zeroth interlayer film, as argued on page 6, this argument is not persuasive because this limitation is taught by Xie, as explained in the previous Office Action, and again in the rejection of claim 1 below. Similarly, although Applicant is correct that APA only disclosed one annealing, as argued on pages 7-8, and that Xie describes a lower first annealing temperature (220C-300C) and a higher second annealing temperature (400C-500C) and Xie does not explicitly disclose “the first annealing is performed before the second annealing and the first temperature is higher than the second temperature, so that the threshold voltage of the metal gate MOS transistor is completely determined by the first annealing”, as explained in the previous Office Action, and again in the rejection of claims below, the Xie reference is applied to show that the technique of applying a first anneal process and a second anneal process, each at different temperatures, was known in the art.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the preferred annealing temperatures as taught by APA with the technique of using first and second anneal processes at different temperatures taught by Xie, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. Although Xie does not disclose that the higher temperature annealing occurs before the lower temperature second annealing, Xie teaches the advantages of two annealing processes each at different temperatures, and combined with the preferred annealing temperatures as taught by APA in FIGs. 2A, 2B, 3A, 3B, and accompanying text, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to pursue the limited number of predictable solutions, i.e., multiple anneal processes within a limited range of temperatures, with a reasonable expectation of success.
Applicant argues on pages 7-10 that “APA does not disclose two annealings.” Although Applicant is correct in stating that APA does not disclose two annealings, the rejections set forth in the previous Office Action do not rely solely on the teachings of APA, but rather the combination of APA and Xie. APA clearly sets forth that there had been a recognized problem known to a person having ordinary skill in the art, “it is impossible to obtain appropriate on-resistance and threshold voltage at the same time.” (APA, Background section of Applicant’s specification, [0025]). APA teaches that for various annealing temperatures, using “an existing technique,” the on-resistance can be predictably controlled (APA, Background section of Applicant’s specification, FIG. 2A, [0026]). Similarly, APA teaches that for various annealing temperatures, using “an existing technique,” the threshold voltages can be predictably controlled (APA, Background section of Applicant’s specification, FIG. 2B, [0027]). Xie teaches that applying a first anneal process and a second anneal process, each at different temperatures, was known in the art. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to pursue the limited number of predictable solutions, i.e., multiple anneal processes, as taught by Xie, within the limited range of temperatures taught by APA, with a reasonable expectation of success.
In response to applicant's argument that on pages 10-11 that Xie's annealing is performed on silicide materials to reduce their resistance, not for controlling threshold voltage of the metal gate in an MOS transistor”, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The Xie reference is applied to show that the technique of applying a first anneal process and a second anneal process, each at different temperatures, was known in the art. Although Applicant’s purpose for annealing differs from the teachings of Xie, the combined teachings of Xie and APA would have suggested Applicant’s claimed method to those of ordinary skill in the art for the reasons discussed in the rejections of the claims below.
Applicant argues on page 10 that Xie's contact (154) is neither disposed over the epitaxial layer of the source and drain nor has a stack of Ti and TiN in between. This argument is not persuasive because Xie discloses that the contact structures 150R and contacts 154, are disposed over the epitaxially grown fins 106 [the epitaxial layer of the source and drain] and, in an embodiment, a Ti, TiN liner [a stack of Ti and TiN] is deposited prior to deposition of the conductive material 150 (Xie, see FIG. 3K, [0049]).
In response to Applicant’s argument on page 11 that the dependent claims are patentably distinct over the prior art, and are also allowable based at least on their dependency from independent claim 1, as amended, see the rejections of the claims below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 and all claims dependent therefrom are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, as amended, recites, inter alia, “the threshold voltage of the metal gate MOS transistor is usually determined by a highest annealing temperature”. The term “usually” in claim 1 is a relative term which leaves room for ambiguity and therefore renders the claim indefinite. The term “usually” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For examination purposes, the term “usually” is understood to refer to that which was known in the art before the effective filing date of the claimed invention. Support for this interpretation may be found, for example, in the Background section of Applicant’s specification, where the term “usually” occurs over a dozen times with reference to existing prior art structures and/or methods (See Applicant’s specification, [0003-0029]). This rejection may be overcome by amending claim 1 to recite clear and precise boundaries defining the invention.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s Admitted Prior Art (hereinafter APA) in view of Xie et al., US 2015/0340452 A1 (hereinafter Xie).
The Background section of Applicant’s specification discusses prior art methods for manufacturing a metal gate transistor at paragraphs [0003 – 0029] and FIGs. 1, 2A, 2B, 3A, and 3B. This portion of Applicant’s specification is relied upon in the following rejection and will be referred to as Applicant’s Admitted Prior Art (hereinafter APA). See MPEP 2129 regarding admissions by Applicant as prior art.
Regarding claim 1, as amended, APA teaches: A method for manufacturing a metal gate MOS transistor (APA, FIG. 1, “FIG. 1 is a flowchart of an existing method for manufacturing a metal gate MOS transistor,” [0016]), comprising: step 1, forming metal gates on a semiconductor substrate (APA, FIG. 1, step S101, “a metal gate is formed in a region where the dummy polysilicon gate is removed,” [0017]), (APA, “an interlayer film which fills a spacing region between the dummy polysilicon gates is formed,” [0006]); step 2,(APA, FIG. 1, step S104, “M0 Etch represents etching a region for forming the zeroth metal layer to form an opening,” [0020]), wherein the opening is aligned to a top surface of the embedded epitaxial layer of the source region and the drain region (APA, opening is to be filled with conductive material to provide electrical contact with bottom contact region of semiconductor material, i.e., the opening is aligned to a top surface of the embedded epitaxial layer of the source region and the drain region, [0019-0022], and performing a first annealing at a first temperature, for adjusting a threshold voltage of the metal gate MOS transistor to a target value (APA, “in the existing method, the annealing in step S105 is not only used to reduce the contact resistance, but also to adjust the threshold voltage (Vt),” [0024]); step 4, forming a Ti layer and a TiN layer on the Ti layer on an inner side surface of the opening (APA, bottom barrier layer, [0010]; “a Ti layer and a TiN layer are formed in the opening,” [0021]), and performing (APA, FIG. 1, step S105, “Ti layer and a TiN layer are formed in the opening and then annealing is performed,” [0021]) (APA, FIGs. 2A and 3A, “The annealing process alloys the Ti layer with a bottom contact region such as the semiconductor material, thereby reducing contact resistance and thereby reducing on-resistance,” [0021]), (APA, FIGs. 2B and 3B, “chart comparing the threshold voltages on two wafers containing metal gate MOS transistors which are annealed at different temperatures for the zeroth metal layer, applying an existing process,” [0027; 0029]), (APA, FIG. 1, step S106, “ the opening is filled with tungsten,” [0022]).
APA is silent regarding: forming a source region and a drain region on two sides of each one of the metal gates, wherein the source region and the drain region comprise an embedded epitaxial layer.
However, Xie, in the same field of endeavor, teaches: forming a source region and a drain region on two sides of each one of the metal gates, wherein the source region and the drain region comprise an embedded epitaxial layer (Xie, FIG. 3K, fins 106 [the source/drain regions] including epi semiconductor material 109 [the embedded epitaxial layer] shown on two sides of each of replacement gate structure 133 [each one of the metal gates], [0045-0050]). Xie teaches that this structural arrangement allows for the distance between the source/drain contact structure and the gate contact structure to be increased, thereby reducing the chances of the gate contact structure shorting with the source/drain contact structure (Xie, [0050]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of APA with the teachings of Xie, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Xie, to allow for etching processes to reduce the chances of the gate contact structure shorting with the source/drain contact structure, thereby improving device performance and reliability.
APA is silent regarding: forming a first dielectric layer on the metal gates and the zeroth interlayer film.
However, Xie, in the same field of endeavor, teaches: forming a first dielectric layer on the metal gates and the zeroth interlayer film (Xie, FIG. 3J, “a layer of insulating material 152 [the first dielectric layer] (e.g., silicon dioxide) was formed above the device 100,” [0048]). Xie teaches that the layer of insulating material 152 helps to encapsulated the buried fin-contact structure prior to etching through the insulating material 152 during formation of the source/drain contact structures and gate contact structure, (Xie, [0048-0049]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of APA with the teachings of Xie, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by Xie, to allow for etching processes to define contact openings, thereby improving manufacturing yield.
Additionally, although APA teaches one annealing, APA is silent regarding: performing a first annealing at a first temperature, for adjusting a threshold voltage of the metal gate MOS transistor to a target value; … and performing a second annealing at a second temperature, for reducing an on-resistance, wherein the first annealing is performed before the second annealing and the first temperature is higher than the second temperature, so that the threshold voltage of the metal gate MOS transistor is completely determined by the first annealing.
However, APA teaches that annealing temperature has a predictable effect on-resistance and threshold voltage, and that a preferred annealing temperature for adjusting threshold voltage is 650°C, while a preferred annealing temperature for adjusting the on-resistance is 600°C, as shown in FIGs. 2A, 2B, 3A, 3B, and accompanying text. APA also teaches that it was a recognized problem in the art before the effective filing date of the claimed invention that “Appropriate threshold voltage and on-resistance cannot be achieved at the same time by adjusting the temperature of the annealing process,” (emphasis added), [0024; see also 0025-0029].
Xie teaches a process for forming a high-k/metal gate transistor using the replacement gate process, including a first anneal process and a second anneal process, each at different temperatures, (Xie, see [0045]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to combine the preferred annealing temperatures as taught by APA with the technique of using first and second anneal processes at different temperatures taught by Xie, arriving at Applicant’s claimed invention with predictable results and without undue experimentation. The motivation for doing so would be, as expressly recognized by APA, to solve the problem of achieving appropriate threshold voltage and on-resistance. It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to pursue the limited number of predictable solutions, i.e., multiple anneal processes within a limited range of temperatures, with a reasonable expectation of success.
Regarding claim 2, APA in view of Xie teaches: The method according to claim 1, wherein in step 1, the metal gates are formed by means of a gate-last process (APA, “The process of forming the metal gate usually adopts a gate-last process,” [0005]).
Regarding claim 3, APA in view of Xie teaches: The method according to claim 2, wherein the gate-last process comprises: removing dummy polysilicon gates; and forming the metal gates where the dummy polysilicon gates are removed (APA, FIG. 1, step S101, “a dummy polysilicon gate is removed, and then a metal gate is formed in a region where the dummy polysilicon gate is removed,” [0017]).
Regarding claim 4, APA in view of Xie teaches: The method according to claim 2, wherein each one of the metal gates comprises a metal work function layer and a metal conductive material layer stacked in sequence (APA, “The metal gate includes a metal work function layer and a metal conductive material layer,” [0004]; “The metal work function layer is formed between the bottom barrier layer and the metal conductive material layer,” i.e., stacked in sequence, [0011]; Xie, FIG. 4F [0044]).
Regarding claim 5, APA in view of Xie teaches: The method according to claim 4, wherein a material of the metal conductive material layer comprises tungsten (APA, “A metal conductive material layer of the metal gate usually adopts tungsten,” [0018]; Xie, [0044]).
Regarding claim 6, APA in view of Xie teaches: The method according to claim 5, wherein a material of the zeroth metal layer comprises tungsten (APA, FIG. 1, step S106, “the opening is filled with tungsten,” [0022]).
Regarding claim 7, APA in view of Xie teaches: The method according to claim 6, wherein the first temperature is in a range of 650°C-700°C (APA, FIGs. 2B, 3B, a preferred annealing temperature for adjusting threshold voltage [the first temperature] is 650°C, [0025-0029]).
Regarding claim 8, APA in view of Xie teaches: The method according to claim 7, wherein the second temperature is in a range of 550°C- 600°C (APA, FIGs. 2A, 3A, a preferred annealing temperature for adjusting the on-resistance [the second temperature] is 600°C, [0025-0029]).
Regarding claim 9, APA in view of Xie teaches: The method according to claim 5, after forming the metal gates in step 1, further comprising a step of etching back the metal conductive material layer (APA, FIG. 1, step S102, “A tungsten etching-back (WEB) process is performed. A metal conductive material layer of the metal gate usually adopts tungsten, and the WEB is one kind of metal conductive material layer etching-back.” [0018]).
Regarding claim 10, APA in view of Xie teaches: The method according to claim 9, before forming the first dielectric layer in step 2 (Xie, FIG. 3J, “a layer of insulating material 152 [the first dielectric layer] (e.g., silicon dioxide) was formed above the device 100,” [0048]), further comprising: a step of forming a second dielectric layer to fill an etching-back region of the metal conductive material layer (APA, region formed during FIG. 1, step S102, [0018]); wherein a material of the first dielectric layer (Xie, FIG. 3J, insulating material 152, silicon dioxide, [0048]) is a same material as a material of the zeroth interlayer film (Xie, FIG. 3F shows insulating material 111, analogous to the interlayer film of APA [the zeroth interlayer film], silicon dioxide, [0042 - 0044]), and a material of the second dielectric layer comprises silicon nitride; and wherein the second dielectric layer is formed by means of a deposition process, and wherein the method further comprises performing planarization by means of a chemical mechanical polishing process after the deposition process (APA, FIG. 1, step S103, “A self-aligned contact (SAC) silicon nitride (SiN) deposition (Dep.)/chemical mechanical polishing (CMP) process, i.e., SAC SiN Dep./CMP, is performed, including two sub-steps: first depositing SiN to define a self-aligned contact and then performing CMP,” [0019]).
Regarding claim 11, APA in view of Xie teaches: The method according to claim 4, wherein in step 1, a gate dielectric layer is disposed between the metal gates and the semiconductor substrate (APA, “an HKMG [high dielectric constant layer (HK) and a metal gate (MG) (HKMG) stacked, see APA, [0003]] is formed in the gate trench,” i.e., HK [the gate dielectric layer] is disposed between the MG [metal gate] and the semiconductor substrate, [0006]).
Regarding claim 12, APA in view of Xie teaches: The method according to claim 11, wherein the gate dielectric layer comprises a high dielectric constant layer (APA, “gate dielectric layer including a high dielectric constant layer,” [0005]).
Regarding claim 13, APA in view of Xie teaches: The method according to claim 12, wherein the metal gate MOS transistor is a fin transistor (APA, “when the process node is reduced to below 25 nm, the existing planar MOS transistor may have a problem of a large electric leakage, and thus a fin transistor (FinFET) is usually adopted,” [0015]), wherein fins are formed on the semiconductor substrate by patterning the semiconductor substrate (APA, “In the FinFET, a fin is formed on a semiconductor substrate by patterning the semiconductor substrate,” [0015]); and wherein the metal gates are disposed on a top surface and side surfaces of one of the fins (APA, “a gate structure covers the top surface and the side surface of the fin,” [0015]).
Regarding claim 15, APA in view of Xie teaches: The method according to claim 4, wherein the metal gate MOS transistor comprises an NMOS and a PMOS (APA, CMOS, [0004]; Xie, CMOS, i.e., an NMOS and a PMOS, [0033]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.L.N./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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