DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous rejection: 1, 4 through 6, 35 through 42 rejected
Present rejection: 1, 4 through 6, 35 through 42 rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5, and 6 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Obuchi (US 2017/0278805).
Regarding claim 1.
Obuchi teaches:
an electronic chip (fig 5:1; [para 0013]), comprising: an outermost seal ring (fig 1-3:14; [para 0013]) that defines an edge of the electronic chip (fig 5:1; [para 0013]) and whose shape is contained within a rectangle (fig 5 annotated) having a width equal to a maximum width of said electronic chip (fig 5:1; [para 0013]) and a length equal to a maximum length of said electronic chip (fig 5:1; [para 0013]);
and at least one test pad (fig 1-3:4,6; [para 0022]) arranged, at least partially, at a location in said rectangle (fig 1);
wherein said test pad (fig 1-3:4,6; [para 0022]) is arranged outside of said outermost seal ring (fig 1-3:14; [para 0013]);
wherein said test pad (fig 5:4,6; [para 0022,0069]) is shared with at least one other electronic chip (fig 5);
and wherein said outermost seal ring (fig 1-3:14; [para 0013]) has a recess (fig 1-3:14a; [para 0071]) of substantially rectangular shape at the location of said at least one test pad (fig 1-3:4,6; [para 0022]),
said at least one test pad (fig 1-3:4,6; [para 0022]) being embedded in said recess (fig 1-3:14a; [para 0071]).
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Regarding claim 5.
Obuchi teaches the electronic chip (fig 5:1; [para 0013]) according to claim 1, wherein
said recess (fig 1,3:14a; [para 0071]) is arranged on a cutting line (fig 1-3:D; [para 0071]) that makes it possible to individualize said electronic chip (fig 3:1; [para 0071]) at the end of its manufacturing method.
Regarding claim 6.
Obuchi teaches the electronic chip (fig 5:1; [para 0013]) according to claim 1, wherein
said test pad (fig 5:4,6; [para 0070]) is positioned next to a cutting line (fig 1-3:D; [para 0071]) that makes it possible to individualize said electronic chip (fig 3:1; [para 0071]) at the end of its manufacturing method.
Claim(s) 39 and 40 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Obuchi (US 2017/0278805).
Regarding claim 39.
Obuchi teaches:
an apparatus, comprising: a group of electronic chips (fig 5:9; [para 0066]) including a first electronic chip (fig 5:1; [para 0066]) and a second electronic chip (fig 5:1; [para 0066]) adjacent the first electronic chip (fig 5:1; [para 0066]) and,
the first and second electronic chips (fig 5:1; [para 0066]) separated by a cutting line (fig 1,5:8,D; [para 0066]);
wherein the first electronic chip (fig 1:1; [para 0066]) includes a first outermost seal ring (fig 1:14; [para 0071]) that defines an edge of the first electronic chip and whose shape is contained within a rectangular or square shape with a first recess of substantially rectangular shape (fig 5 annotated);
wherein the second electronic chip (fig 5:1; [para 0066]) includes a second outermost seal ring (fig 1:14; [para 0071]) that defines an edge of the second electronic chip (fig 5:1; [para 0066]) and whose shape is contained within a rectangular or square shape with a second recess (fig 1:14a; [para 0071]) of substantially rectangular shape (fig 1,5);
and a plurality of test pads (fig 1,5:4,6; [para 0071]) arranged outside the first and second outermost seal rings (fig 5:14; [para 0013]) and embedded in said first and second recesses (fig 1:14a; [para 0071]).
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Regarding claim 40.
Obuchi teaches the apparatus of claim 39, wherein:
the first (fig 1:14a; [para 0071]) and second recesses (fig 1:14a; [para 0071]) face and are aligned with each other (fig 5).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obuchi (US 2017/0278805) as applied to claim 1 and further in view of West (US 2010/0078769).
Regarding claim 4
Obuchi teaches the electronic chip according to claim 1 above.
Obuchi does not teach the arrangement of circuitry in the die area.
West teaches:
at least one circuit arranged in an area (fig 2:150; [para 0021]) of same size as the recess (fig 2:140; [para 0020]) and arranged against a first side of the electronic chip (fig 2:110; [para 0020]), opposite a second side of the chip (fig 2:110; [para 0020]) where said recess (fig 2:140; [para 0020]) is formed, said at least one circuit being a circuit whose position in said electronic chip can be modified.
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It would have been obvious to one of ordinary skill in the for the chip to comprise an area the same size as the recess area for circuitry in order to provide a location for test circuitry and like structures (paragraph 20).
Given the teaching of the references, it would have been obvious to determine the optimum area sizes. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 35, 37, and 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obuchi (US 2017/0278805) in view of Chen (US 2011/0284843).
Regarding claim 35.
Obuchi teaches:
an apparatus, comprising: a group of electronic chips (fig 1,5:9; [para 0013,0066]) including a first electronic chip (fig 1,5:1; [para 0013,0066]) and a second electronic chip (fig 1,5:1; [para 0013,0066])adjacent the first electronic chip (fig 1,5:1; [para 0013,0066]), the first and second electronic chips (fig 1,5:1; [para 0013,0066]) separated by a cutting line (fig 1,5:D,8; [para 0070,0071]);
wherein each of the first and second electronic chips (fig 1,5:1; [para 0013,0066]) includes an outermost seal ring (fig 1-3:14; [para 0013])that defines an edge of the electronic chip (fig 1,5:1; [para 0013,0066]) and whose shape is contained within a rectangular or square shape (fig 5 annotated);
wherein the outermost seal ring (fig 1-3:14; [para 0013]) for at least the first electronic chip (fig 1,5:1; [para 0013,0066]) includes a recess (fig 1-3:14a; [para 0071]) of substantially rectangular shape;
and a test pad(fig 1,5:4,6; [para 0071]) arranged outside the outermost seal ring (fig 1-3:14; [para 0013]) and embedded in said recess (fig 1-3:14a; [para 0071]).
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Obuchi does not teach a plurality of pads embedded in the recess.
Chen teaches:
a plurality of test pads (fig 2:1141-3; [para 0018]) arranged outside the seal ring (fig 2:110; [para 0016]) and embedded in said recess (fig 2:108; [para 0018]).
It would have been obvious to one of ordinary skill in the art to provide a plurality of pads in order to conduct multiple tests from the same region thereby more efficiently using available area.
Regarding claim 37.
Obuchi in view of Chen teaches the apparatus of claim 35, further:
Obuchi teaches
at least part (fig 1:4; [para 0024]) of the test pad (fig 1:4; [para 0024]) is located in the cutting line (fig 1,5:8,D; [para 0071]) separating the first and second electronic chips (fig 1,5:1; [para 0024]).
Chen teaches:
a plurality of test pads (fig 2:1141-3; [para 0018]) arranged outside the seal ring (fig 2:110; [para 0016]) and embedded in said recess (fig 2:108; [para 0018]).
Regarding claim 38,
Obuchi in view of Chen teaches the apparatus of claim 35:
the recess (fig 1:14a; [para 0071]) of the outermost seal ring (fig 1:14; [para 0071]) for the first electronic chip (fig 5:1; [para 0013]) faces a side of the outermost seal ring (fig 1:14; [para 0071]) for the second electronic chip (fig 5:1; [para 0066]).
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Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obuchi (US 2017/0278805) in view of Chen (US 2011/0284843) as applied to claim 35 and further in view Kim (US 2018/0174933).
Regarding claim 36.
Obuchi in view of Chen teaches the apparatus of claim 35 above
Obuchi teaches the recess (fig 1:14a; [para 0071]) of the outermost seal ring (fig 1:14; [para 0071]) for the first electronic chip (fig 1,4:1; [para 0013]) [and] the second electronic chip (fig 1,4:1; [para 0013]).
Obuchi does not teach a bus connecting pads.
Kim teaches:
a bus (fig 2:213,215; [para 0022])connected to at least one of the plurality of test pads (fig 2:116,212; [para 0022]),
said bus (fig 2:213,215; [para 0022]) passing through the cutting line (fig 2:220; [para 0022]) to electrically connect said at least one of the plurality of test pads (fig 2:116,212; [para 0022]) for the first electronic chip (fig 2:110; [para 0021]) to the second electronic chip (fig 2:130; [para 0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a bus connecting pads in order that more chips can be tested simultaneously and enable a reduction in particles generated during singulation (paragraph 28).
Claim(s) 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obuchi (US 2017/0278805) as applied to claim 39 and further in view of Fujii (US 6462401).
Regarding claim 41.
Obuchi teaches the apparatus of claim 39 above
Obuchi teaches:
the first recess (fig 1:14a; [para 0071]) faces (fig 5) a side of the second outermost seal ring (fig 1:14; [para 0071]) and the second recess (fig 1:14a; [para 0071]) faces a side of the first outermost seal ring (fig 1:14; [para 0071]),
and wherein the first and second recesses (fig 1:14a; [para 0071]) ,
and wherein the plurality of test pads (fig 1,5:4,6; [para 0013]) includes first test pads (fig 1,5:4,6; [para 0013]) embedded in the first recess and second test pads (fig 1,5:4,6; [para 0013]) embedded in the second recess (fig 1,5:14a; [para 0071]).
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Obuchi does not teach that the pads and recesses are not aligned.
Fujii teaches:
the first recess faces a side of the second [chip] (fig 5:11[column 1 lines 25-30]) and the second recess faces a side of the first [chip] (fig 5:11[column 1 lines 25-30]),
and wherein the first and second recesses are not aligned with each other, and wherein the plurality of test pads (fig 4:15[column 1 lines 30-35]) includes first test pads embedded in the first recess and second test pads embedded in the second recess.
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the recesses to not align in order to accommodate asymmetric chip layouts.
Claim(s) 42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Obuchi (US 2017/0278805) in view of Fujii (US 6462401) as applied to claim 41 and further in view of Kim (US 2018/0174933).
Regarding claim 42.
Obuchi in view of Fujii the apparatus of claim 41, further:
Obuchi teaches
at least one of the first test pads (fig 1:4,6; [para 0013]),
said at least one of the first test pads (fig 1:4,6; [para 0071]) in the first recess (fig 1:14a; [para 0071]) of the first outermost seal ring (fig 1:14; [para 0071]) for the first electronic chip (fig 5:1; [para 0013]) ;
and at least one of the second test pads (fig 1:4,6; [para 0013]),
said at least one of the second test pads (fig 1:4,6; [para 0013]) in the second recess (fig 1:14a; [para 0071]) of the second outermost seal ring (fig 1:14; [para 0071]) for the second electronic chip (fig 5:1; [para 0013])
Obuchi in view of Fujii does not teach a bus.
Kim teaches:
a first bus (fig 2:213,215; [para 0022]) connected to at least one of the first test pads (fig 2:116,212; [para 0022]),
said first bus (fig 2:213,215; [para 0022]) passing through the cutting line (fig 2:220; [para 0022]) to electrically connect said at least one of the first test pads (fig 2:116,212; [para 0022]) for the first electronic chip (fig 2:110; [para 0021]) to the second electronic chip (fig 2:130; [para 0021]);
and a second bus (fig 2:213,215; [para 0022]) connected to at least one of the second test pads (fig 2:116,212; [para 0022]),
said second bus (fig 2:213,215; [para 0022]) passing through the cutting line to electrically connect said at least one of the second test pads (fig 2:116,212; [para 0022]) for the second electronic chip (fig 2:130; [para 0021]) to the first electronic chip (fig 2:110; [para 0021]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a bus connecting pads in order that more chips can be tested simultaneously and enable a reduction in particles generated during singulation (paragraph 28).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied reference Obuchi (US 2017/0278805) anticipates the claims
Previously applied rejection under USC 112 paragraph 2 is withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/ Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 11, 2026