DETAILED ACTION
Claim Objections/correction
Claims 10 and 21 are objected to because of minor issues. The Examiner suggests the following amendments:
Replace ‘The method of claim 10’ in claim 13, line 1, by ‘The method of claim 9’,
Replace ‘area’ in claim 21, line 6, by ‘region’,
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9, 12-13 and 21-22, and 24-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 20160020267 A1, hereinafter Lin‘267) of record.
Regarding independent claim 9, Lin‘267 teaches, “A method for forming a layout structure of an integrated circuit (fig. 1-25; ¶ [0022] - ¶ [0066]), comprising:
defining, on a substrate (300, fig. 3), a first rectangular region (fig. 1C, fig. 12B etc) corresponding to a first capacitor (fig. 11, see annotation) comprising a first dielectric layer (800);
defining, on the substrate (300), a second rectangular region (fig. 1C, fig. 12B etc) corresponding to a second capacitor (fig. 11, see annotation) comprising a second dielectric layer (800);
defining, on the substrate (300), a third rectangular region (accommodating metal line 1102, 1100, fig. 11) overlapping the first and second rectangular regions, the third rectangular region corresponding to a metal line (1104); and
defining a fourth rectangular region (containing contact 1102h, fig. 11) within the third rectangular region and corresponding to a at a via interface and configured to provide a shared electrical path to the first and second capacitors,
wherein the via interface (bottom surface of 1102h) is disposed beneath a top surface of the first dielectric layer (800) and a top surface of the second dielectric layer (800).
Regarding claim 12, Lin‘267 further teaches, “The method of claim 9, wherein defining the third rectangular region comprises defining a region less than or equal to the area of each of the first and second rectangular regions (fig. 11, 12A)”.
Regarding claim 13, Lin‘267 further teaches, “The method of claim 9, wherein defining the first and second rectangular regions comprises spacing the first and second capacitors apart (fig. 11)”.
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Regarding independent claim 21, Lin‘267 teaches, “A method (fig. 1-25; ¶ [0022] - ¶ [0066]), comprising:
forming, on a substrate (300, fig. 3), a first region (fig. 1C, fig. 12B etc) corresponding to a first capacitor (fig. 11, see annotation) comprising a first dielectric layer (800);
forming, on the substrate (300), a second region (fig. 1C, fig. 12B etc) corresponding to a second capacitor (fig. 11, see annotation) comprising a second dielectric layer (800);
forming, on the substrate (300), a third region (accommodating metal line 1102, 1100, fig. 11) on the first and second regions, the third region corresponding to a metal line (1104); and
forming a fourth region (containing contact 1102h, fig. 11) within the third region and corresponding to a at a via interface and configured to provide a shared electrical path to the first and second capacitors,
wherein the via interface (bottom surface of 1102h) is disposed beneath a top surface of the first dielectric layer (800) and a top surface of the second dielectric layer (800).
Regarding claim 22, Lin‘267 further teaches, “The method of claim 21, wherein forming the first and second regions comprises arranging the first and second capacitors side-by-side (mapping two adjacent capacitors as first and second capacitors in fig. 11)”.
Regarding claim 24, Lin‘267 further teaches, “The method of claim 21, wherein forming the third region comprises forming a region less than or equal to each of the first and second regions (fig. 11, 12A)”.
Regarding claim 25, Lin‘267 further teaches, “The method of claim 21, wherein forming the first and second regions comprises spacing the first and second capacitors apart (fig. 11, 12A)”.
Regarding claim 26, Lin‘267 further teaches, “The method of claim 21, further comprising forming a passivation layer (1000, fig. 11) over the first and second capacitors”.
Regarding claim 27, Lin‘267 further teaches, “The method of claim 21, further comprising depositing a first inter-layer dielectric (ILD) layer (1632, fig. 16A) over the metal line (1622)”.
Regarding claim 28, Lin‘267 further teaches, “The method of claim 21, wherein the first and second capacitors comprise a high-k dielectric layer (¶ [0033]) with zirconium and aluminum oxide sub-layers’.
Claim 14 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Won et al. (US 20070102746 A1, hereinafter Won‘746).
Regarding independent claim 14, Won‘746 teaches, “A method, comprising:
forming first and second metal lines (124, fig. 6) on a substrate (100);
depositing a first inter-layer dielectric (ILD) layer (140, fig. 7) over the first and second metal lines (124, 124);
forming a first trench (142, fig. 7) and a second trench (142) in the first ILD layer (140) and over each of the first and second metal lines (124, 124);
forming a first capacitor and a second capacitor (fig. 11) that extend into the first trench and the second trench, respectively, so that bottom electrodes (212) of the first and second capacitors are in physical contact with the first and second metal lines (124, 124), respectively, a portion of a top surface of dielectric layers (220) of the first and second capacitors is disposed above a top surface of the first ILD layer (140);
depositing a second ILD layer (150, fig. 12) over the first and second capacitors; and
forming, in the second ILD layer (150), a shared contact (152) (electrically) coupled to top electrodes of the first and second capacitors and between the first and second capacitors,
wherein the via interface (152) is disposed beneath a top surface of the first dielectric layer (220) and a top surface of the second dielectric layer (220)”.
Claims 9, 11-13, 21-26 and 31 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 20220416014 A1, hereinafter Lin‘014).
Regarding independent claim 9, Lin‘014 teaches, “A method for forming a layout structure of an integrated circuit (fig. 1-4; ¶ [0016] - ¶ [0035]), comprising:
defining, on a substrate (404, fig. 4G), a first rectangular region corresponding to a first capacitor (any of the five capacitors shown in fig. 4G) comprising a first dielectric layer (418);
defining, on the substrate (404, fig. 4G), a second rectangular region corresponding to a second capacitor (any other of the five capacitors shown in fig. 4G) comprising a second dielectric layer (418);
defining, on the substrate (404), a third rectangular region (containing element 426) overlapping the first and second rectangular regions, the third rectangular region corresponding to a metal line (426); and
defining a fourth rectangular area within the third rectangular region and corresponding to a via (424) in direct contact with the first and second capacitors at a via interface and configured to provide a shared electrical path to the first and second capacitors,
wherein the via interface (424) is disposed beneath a top surface of the first dielectric layer (418) and a top surface of the second dielectric layer (418)”.
Regarding claim 11, Lin‘014 further teaches, “The method of claim 9, wherein defining the fourth rectangular region comprises placing the via (424) between the first and second capacitors”.
Regarding claim 12, Lin‘014 further teaches, “The method of claim 9, wherein defining the third rectangular region comprises defining a region less than or equal to the area of each of the first and second rectangular regions (boundary of first/second/third regions can be drawn accordingly)”.
Regarding claim 13, Lin‘014 further teaches, “The method of claim 10, wherein defining the first and second rectangular regions comprises spacing the first and second capacitors apart by a minimum separation distance (Out of 5 capacitors, first and second capacitors can be picked up accordingly)”.
Regarding independent claim 21, Lin‘014 teaches, “A method (fig. 1-4; ¶ [0016] - ¶ [0035]) comprising:
forming, on a substrate (404, fig. 4G), a first region corresponding to a first capacitor comprising a first dielectric layer (418);
forming, on the substrate (404, fig. 4G), a second region corresponding to a second capacitor comprising a second dielectric layer (418);
forming, on the substrate (404, fig. 4G), a third region on the first and second area, the third region corresponding to a metal line (426); and
forming a fourth region within the third region and corresponding to a via (424) extending from the metal line (426) and in direct contact with the first and second capacitors at a via interface and providing a shared electrical connection to the first and second capacitors,
wherein the via interface (424) is disposed beneath a top surface of the first dielectric layer (418) and a top surface of the second dielectric layer (418)”.
Regarding claim 22, Lin‘014 further teaches, “The method of claim 21, wherein forming the first and second regions comprises arranging the first and second capacitors side-by-side (Out of 5 capacitors, first and second capacitors can be picked up side-by-side)”.
Regarding claim 23, Lin‘014 further teaches, “The method of claim 21, wherein forming the fourth region comprises placing the via (424) between the first and second capacitors”.
Regarding claim 24, Lin‘014 further teaches, “The method of claim 21, wherein forming the third region comprises forming a region less than or equal to each of the first and second regions (boundary of first, second, third regions can be drawn accordingly)”.
Regarding claim 25, Lin‘014 further teaches, “The method of claim 21, wherein forming the first and second regions comprises spacing the first and second capacitors apart (Out of 5 capacitors, first and second capacitors can be picked up accordingly)”.
Regarding claim 26, Lin‘014 further teaches, “The method of claim 21, further comprising forming a passivation layer (422) over the first and second capacitors”.
Regarding claim 31, Lin‘014 further teaches, “The method of claim 9, wherein defining the third rectangular region comprises overlapping the third rectangular region with a region of the first and second dielectric layers (418), and wherein the via is a single via (418) and the region consists of a single via opening filled by the single via (boundary of third rectangular region can be drawn accordingly)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15, 20 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Won‘746 as applied to claim 14 as above, and further in view of SHIN; SEUNGHUN et al. (US 20210118618 A1, hereinafter Shin‘618) of record.
Regarding claim 15, Won‘746 teaches all the limitations described in claim 14.
But Won‘746 is silent upon the provision of wherein the method of claim 14, further comprising: depositing a third ILD layer over the second ILD layer; and forming, in the third ILD layer, an upper metal line coupled to the first and second capacitors through the shared contact.
However, Shin‘618 teaches, a similar method comprising: depositing a third ILD layer (150A, fig. 13A-13B, Shin‘618) over the second ILD layer (140); and forming, in the third ILD layer (150A), an upper metal line (154) coupled to the first and second capacitors through the shared contact (144).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Won‘746 and Shin‘618 to include ILD layers and metal lines according to the teachings of Shin‘618 as these are conventional and essential elements of this capacitor device.
Regarding claim 20, Won‘746 modified with Shin‘618 further teaches, “The method of claim 14, further comprising forming a passivation layer (150A, fig. 14, Shin‘618) over the first and second capacitors”.
Regarding claim 30, Won‘746 modified with Shin‘618 further teaches, “The method of claim 14, wherein the first trench (122H, fig. 9B, Shin‘618) has a width at a top surface of the first ILD layer (122) greater than a width at a bottom surface of the first ILD layer (122)”.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Won‘746 modified with Shin‘618 as applied to claim 15 above, and further in view of Hsu Hsu et al. (US 20180102368 A1, hereinafter Hsu‘368) of record.
Regarding claim 16, Won‘746 modified with Shin‘618 teaches all the limitations described in claim 14.
But Won‘746 modified with Shin‘618 is silent upon the provision of wherein forming the first ILD layer comprises forming an etch stop layer that includes one or more of silicon carbide (SiC) and silicon nitride (SiN).
However, Hsu‘368 teaches a similar method of manufacturing capacitor devices, wherein forming the first ILD layer (140c, fig. 6; ¶ [0028]) comprises forming an etch stop layer (144) that includes one or more of silicon carbide (SiC) and silicon nitride (SiN).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Won‘746 modified with Shin‘618 and Hsu‘368 to include etch stop layers according to the teachings of Hsu‘368 with a general motivation of protecting underlying layers from etching chemicals, allowing for precise and deeper pattern transfer into a specific material while maintaining the integrity of other layers.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Won‘746 as applied to claim 14 above, and further in view of Clevenger et al. (US 20070278619 A1) of record.
Regarding claim 19, Won‘746 teaches all the limitations described in claim 14.
But Won‘746 is silent upon the provision of wherein forming the first and second capacitors comprises depositing metal layers into the first and second trenches using a metal plating process.
However, Clevenger et al. teaches a similar MIM capacitor (¶ 0040), wherein forming the first and second capacitors comprises depositing metal layers into the first and second trenches using a metal plating process.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Won‘746 and Clevenger et al. to form the capacitor plates using metal plating according to the teachings of Clevenger et al. as metal plating has advantages e.g., enhanced corrosion resistance, increased strength and durability, improved electrical conductivity, and enhanced aesthetics.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Won‘746 as applied to claim 14 above, and further in view of Han (US 20100213573 A1, hereinafter Han‘573).
Regarding claim 29, Won‘746 teaches all the limitations described in claim 14.
But Won‘746 is silent upon the provision of wherein the first trench has a width less than a width of the first metal line.
However, Han‘573 teaches a similar capacitor (fig. 1), wherein the first trench (accommodating capacitor 14A) has a width less than a width of the first metal line (BL).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Won‘746 and Han‘573 to form the metal line wider than the trench width according to the teachings of Han‘573 with a general motivation of ensuring good ohmic contact between the capacitor and the metal line.
Response to Arguments
Applicant’s arguments with respect to the newly amended claims have been considered but are moot because the arguments do not apply to any of the references being as used in the current rejection.
Examiner’s Note
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817