Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 01/06/2022 is acknowledged.
Claims 10-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/06/2022.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-9 and 17-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 of U.S. Patent No. 11367695 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because
Regarding claim 1, Claim 1 of 11367695 teaches an interposer, comprising: a first conductive layer comprising a first signal line and a second signal line; a second conductive layer comprising a third signal line and a fourth signal line; a plurality of capacitors positioned between the first conductive layer and the second conductive layer, each of the plurality of capacitors comprising a first conductive plate and a second conductive plate; a plurality of first connectors, a respective first connector of the plurality of first connectors connecting the first conductive plate of a respective capacitor of the plurality of capacitors to the first signal line in the first conductive layer; a plurality of second connectors, a respective second connector of the plurality of second connectors connecting the second conductive plate of the respective capacitor of the plurality capacitors to the second signal line in the first conductive layer wherein: the plurality of first connectors are arranged to overlap and alternate with the plurality of second connectors along a first dimension of the interposer, wherein the first dimension extends perpendicular to a thickness direction of the interposer; each of the plurality of first connectors extend out from the first signal line along a second dimension of the interposer towards the second signal line, wherein the second dimension extends perpendicular to the first dimension and the thickness direction; and each of the plurality of second connectors extend out from the second signal line along the second dimension of the interposer towards the first signal line.
Regarding claim 2, Claim 1 of 11367695 teaches one or more third connectors spaced apart from the first and the second conductive plates, a respective third connector of the one or more third connectors connecting the first signal line in the first conductive layer to the third signal line in the second conductive layer; and one or more fourth connectors spaced apart from the first and the second conductive plates, a respective fourth connector of the one or more fourth connectors connecting the second signal line in the first conductive layer to the fourth signal line in the second conductive layer.
Regarding claim 3, Claim 2 of 11367695 teaches a portion of a third dimension of each first connector overlaps a portion of the third dimension of an adjacent second connector.
Regarding claim 4, Claim 3 of 11367695 teaches the second dimension of the interposer is less than the first dimension
Regarding claim 5, Claims 4 and 5 of 11367695 teaches he first conductive plate comprises a capacitor top metal plate, and wherein the second conductive plate comprises a capacitor bottom metal plate
Regarding claim 6, Claim 6 of 11367695 teaches in a first area of the interposer, each of the plurality of first connectors extends out from the first signal line along the second dimension of the interposer towards the second signal line and each of the plurality of second connectors extends out from the second signal line along the second dimension of the interposer towards the first signal line; in a second area of the interposer, each of the plurality of first connectors extends out from the first signal line along a third dimension of the interposer towards another second signal line and each of the plurality of second connectors extends out from the another second signal line along the third dimension of the interposer; and a portion of a fourth dimension of each of the plurality of first connectors overlaps a portion of the fourth dimension of an adjacent second connector.
Regarding claim 7, Claim 7 of 11367695 teaches each of the plurality of first connectors the plurality of second connectors comprise a set of one or more connectors.
Regarding claim 8, Claim 21 of 11367695 teaches a via formed in the first conductive plate, wherein the respective second connector is positioned in the via to connect the second conductive plate of the respective capacitor to the second signal line in the first conductive layer.
Regarding claim 9, Claim 22 of 11367695 teaches a through-silicon via formed in the interposer for routing a signal line.
Regarding claim 17, Claim 30 of 11367695 teaches an interposer, comprising: a first conductive layer comprising a first signal line and a second signal line; a second conductive layer comprising a third signal line and a fourth signal line; a plurality of capacitors positioned between the first conductive layer and the second conductive layer, each of the plurality of capacitors comprising a first conductive plate and a second conductive plate parallel to the first conductive plate; a plurality of first connectors, a respective first connector of the plurality of first connectors connecting the first conductive plate of a respective capacitor of the plurality of capacitors to the first signal line in the first conductive layer; a plurality of second connectors, a respective second connector of the plurality of second connectors connecting the second conductive plate of the respective capacitor of the plurality of capacitors to the second signal line in the first conductive layer, and wherein: the plurality of first connectors are arranged to overlap and alternate with the plurality of second connectors along a first dimension of the interposer, wherein the first dimension extends perpendicular to a thickness direction of the interposer, each of the plurality of first connectors extend out from the first signal line along a second dimension of the interposer towards the second signal line, wherein the second dimension extends perpendicular to the first dimension and the thickness direction, and each of the plurality of second connectors extends out from the second signal line along the second dimension of the interposer towards the first signal line
Regarding claim 18, Claim 31 of 11367695 teaches each of the plurality of capacitors comprises a metal-insulator-metal capacitor.
Regarding claim 19, Claim 32 of 11367695 teaches a through-silicon via formed in the interposer for routing a signal line.
Regarding claim 20, Claim 33 of 11367695 teaches a via formed in the first conductive plate, wherein the respective second connector is positioned in the via to connect the second conductive plate of the respective capacitor to the second signal line in the first conductive layer.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the interposer wherein “each of the plurality of second connectors extend out from the second signal line along the second dimension of the interposer towards the first signal line” and “each of the plurality of second connectors extends out from the another second signal line along the third dimension of the interposer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 6, the claim recites “each of the plurality of first connectors extends out from the first signal line along a third dimension of the interposer towards another second signal line and each of the plurality of second connectors extends out from the another second signal line along the third dimension of the interposer” in lines 6-9 however this is unclear as no embodiment is described in which both the above statement is true and “each of the plurality of second connectors extend out from the second signal line along the second dimension of the interposer towards the first signal line” as required by claim 1 on which claim 6 depends so that it is unclear if this limitation is meant to require such a structure or if applicant meant --each of another plurality of first connectors extends out from the first signal line along a third dimension of the interposer towards another second signal line and each of another plurality of second connectors extends out from the another second signal line along the third dimension of the interposer--, for the purpose of examination the latter interpretation will be taken.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 7, 17-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Yen et. Al. (US 20140264742 A1 hereinafter Yen).
Regarding claims 1 and 17, Yen teaches in Figs. 6-9 with associated text an interposer, comprising:
a first conductive layer 60 comprising a first signal line 600 and a second signal line 610 Fig. 6, [0034[);
a second conductive layer (layer comprising 652 and 642 for example) comprising a third signal line 652 and a fourth signal line 642 (Figs. 8-9, [0039]);
a plurality of capacitors (capacitors made up of 702-704 and 711-713) positioned between the first conductive layer and the second conductive layer, each of the plurality of capacitors comprising a first conductive plate (711-713) and a second conductive plate (702-704 or 622 along with similar interconnected electrodes in the same plane) (Fig; 7, [0038]) regarding claim 17 parallel to the first conductive plate (Fig; 7, [0038]),
a plurality of first connectors (601-604), a respective first connector of the plurality of first connectors connecting the first conductive plate of a respective capacitor of the plurality of capacitors to the first signal line in the first conductive layer (Figs. 6 and 8, [0038]);
a plurality of second connectors (611-614), a respective second connector of the plurality of second connectors connecting the second conductive plate of the respective capacitor of the plurality capacitors to the second signal line in the first conductive layer (Figs. 7 and 9, [0038])
wherein:
the plurality of first connectors are arranged to overlap and alternate with the plurality of second connectors along a first dimension (x direction) of the interposer, wherein the first dimension extends perpendicular to a thickness direction of the interposer (Fig. 6);
each of the plurality of first connectors extend out from the first signal line along a second dimension (y direction) of the interposer towards the second signal line, wherein the second dimension extends perpendicular to the first dimension and the thickness direction (Fig. 6); and
each of the plurality of second connectors extend out from the second signal line along the second dimension of the interposer towards the first signal line (Fig. 6).
Regarding claim 3, Yen teaches a portion of a third dimension of each first connector overlaps a portion of the third dimension of an adjacent second connector (Fig. 6 and 8-9).
Regarding claim 4, Yen teaches the second dimension of the interposer is less than the first dimension (here the first dimension is interpreted to be the length of 600 and 610 in the x direction and the second dimension is interpreted to be the length of 600 and 610 in the y direction Fig. 6).
Regarding claim 5, Yen teaches the first conductive plate comprises a capacitor top metal plate, and wherein the second conductive plate comprises a capacitor bottom metal plate (here 622 along with similar interconnected electrodes in the same plane are interpreted to be the second conductive plates Fig. 7 metal is used .[0047]).
Regarding claim 7, Yen teaches each of the plurality of first connectors the plurality of second connectors comprise a set of one or more connectors (vias each connector include a plurality of vias Figs. 8-9).
Regarding claim 18, Yen teaches each of the plurality of capacitors comprises a metal-insulator-metal capacitor (Fig. 7, insulator [0036] and metal [0047[ materials are used for the capacitor).
Regarding claim 20, Yen teaches a via formed in the first conductive plate, wherein the respective second connector is positioned in the via to connect the second conductive plate of the respective capacitor to the second signal line in the first conductive layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yen as applied to claim 1.
Regarding claim 6, Yen teaches The interposer of claim 1, wherein: in a first area of the interposer, each of the plurality of first connectors extends out from the first signal line along the second dimension of the interposer towards the second signal line and each of the plurality of second connectors extends out from the second signal line along the second dimension of the interposer towards the first signal line Fig. 6.
Yen does not specify in a second area of the interposer, each of another plurality of first connectors extends out from the first signal line along a third dimension of the interposer towards another second signal line and each of another plurality of second connectors extends out from the another second signal line along the third dimension of the interposer; and a portion of a fourth dimension of each of the plurality of first connectors overlaps a portion of the fourth dimension of an adjacent second connector.
Yen discloses in the embodiment of Figs. 1 with associated text however a first area (area between 131 and 101) similar to that of the embodiment of Figs 6-9 and a second area (area between 101 and 121) in a second area of an interposer, each of the plurality of first connectors (102-103) extends out from the first signal line 101 along a third dimension (length of second area in the y direction Fig. 1) of the interposer towards another second signal line 121 and each of the plurality of second connectors (124-125) extends out from the another second signal line along the third dimension of the interposer (Fig. 1); and a portion of a fourth dimension of each of the plurality of first connectors overlaps a portion of the fourth dimension of an adjacent second connector
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use and arrangement similar to that of Yen Fig. 1 to include further connectors in the embodiment of Yen shown in Figs. 6-9 because doing so would improve at least parasitic performance (e.g., parasitic resistance and inductance) of the integrated capacitor while maintaining high capacitor density (capacitance/area) [0013].
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yen as applied to claim 1 and further in view of Inagaki et. Al. (US 20050157478 A1 hereinafter Inagaki).
Regarding claim 8, Yen teaches the interposer of claim 1.
Yen does not specify a via formed in the first conductive plate, wherein the respective second connector is positioned in the via to connect the second conductive plate of the respective capacitor to the second signal line in the first conductive layer.
Inagaki discloses in Figs. 18(D) and 69 with associated text a via (opening in 24 for 22 Figs. 18(D) and 69) formed in the first conductive plate, wherein a respective second connector is positioned in the via to connect the second conductive plate of the respective capacitor to the second signal line in the first conductive layer (Fig. 69).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a capacitor plate with via structure similar to that of Inagaki for the capacitor plates of Yen because according to Yen by doing so a capacitor having a large capacity can be formed [0598].
Claims 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yen as applied to claim 1 above and further in view of Kuo et. Al. (US 20160071805 A1 hereinafter Kuo).
Regarding claims 9 and 19, Yen teaches the interposer of claim 1 and 17.
Yen does not specify a through-silicon via formed in the interposer for routing a signal line.
Kuo discloses in Figs. 3A with associated text a through-silicon via 44 formed in an interposer similar to that of Yen for routing a signal line 38 (paragraph [0022], Fig. 3A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a through-silicon via in the interposer of Yen for routing a signal line as taught by Kuo because according to Kuo such a through-silicon via is useful for coupling to further components (Kuo paragraph [0022]) furthermore using such a through-silicon via in an interposer was very well known in the art before the effective filing date of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached on Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897