Detailed Action
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et. Al. (US 9659943 B1 hereinafter Tran) and further in view of Tseng et. Al. (US 9589970 B1 hereinafter Tseng).
Regarding claim 10,Tran teaches in Fig. 1 with associated text a semiconductor device, comprising: a substrate 16 having an one time programmable (OTP) device region (Fig. 1, col. 5, lines 24-26); a shallow trench isolation (STI) 18 in the substrate (Fig. 1, col. 5, lines 34-36); a first doped region 26 adjacent to the STI (Fig. 1, col. 5, lines 24-26); and a first gate structure 40 on the substrate and the STI (Fig. 1, col. 4, lines 49-50), wherein the first gate structure comprises: a high-k dielectric layer 50 on the substrate (Fig. 1, col. 4, lines 63-65), wherein the high-k dielectric layer comprises a first L-shape (Fig. 1, see annotated Fig. below); and a gate electrode 42 on the high-k dielectric layer (Fig. 1, col. 4, lines 4-5); and a first spacer (structure not labeled on right side of gate structure) adjacent to one side of the first gate structure (Fig. 1); and a second spacer (structure not labeled on left side of gate structure) adjacent to another side of the first gate structure, wherein a second sidewall of the first gate structure directly contacting the second spacer is directly on the first doped region (Fig. 1).
Tran does not specify a first sidewall of the first gate structure directly contacting the first spacer is directly on the STI.
Tseng discloses in Fig. 4 with associated text an embodiment of a semiconductor device similar to that of Tran wherein a first gate structure 650 extends all the way over a STI 121 and in Fig. 2 an embodiment of a semiconductor device wherein a sidewall of a first gate structure (340 and 350) directly contacting a first spacer (360 on right side of 340) is directly on the STI (Fig. 2, col. 5, lines 1-11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to the embodiment of Fig. 2 of Tseng in the device of Tran t because according to Tseng such a structure is suitable for forming a vertical program gate transistor PGT.sub.1 comprises a program gate 340 that is electrically coupled to a source line, for example, SL.sub.1, and another vertical program gate transistor PGT.sub.2 comprises a program gate 440 that is electrically coupled to another source line, for example, SL.sub.2 (column 4, lines 55-60) so that such a structure would be useful in the device of Tran when two independent programing gates are required.
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Regarding claim 15, Tran teaches the first doped region contacts the high-k dielectric layer directly (Fig. 1).
Regarding claim 16, Tran teaches the first L-shape contacts a top surface and a sidewall of the substrate (Fig. 1).
Regarding claim 17, Tran teaches the high-k dielectric layer comprises a second L-shape (see annotated Fig. 1).
Regarding claim 18, Tran teaches the second L-shape contacts a sidewall of the substrate and a top surface of the STI (Fig. 1, see annotated Fig. above).
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Tseng as applied to claim 10 and further in view of Bracchitta et. Al. (US 6130469 A hereinafter Bracchitta).
Regarding claim 11,Tran un view of Tseng teaches the semiconductor device of claim 10, further comprising: a second gate structure (60 and 62 thereunder on left side) adjacent to the first gate structure (Fig. 1, col. 6, lines 42-44); and an interlayer dielectric (ILD) layer (270 of Tran or 500 of Tseng) around the first gate structure and the second gate structure (Fig. 5H, col. 8, lines 33-36).
Tran does not specify in the embodiment shown in Fig. 1 an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure however Tran teaches in the embodiment shown in Figs. 4A-5H an interlayer dielectric (ILD) layer 270 around the first gate structure and the second gate structure (Figs. 5D and 5H, col. 8, lines 33-36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to an interlayer dielectric (ILD) layer as shown if Fig. 5H around the first gate structure and the second gate structure of the embodiment of Fig. 1 of Tran because according to Tran the structure acts as an inter-layer dielectric (ILD) (col. 8, lines 33-36) such structures were very well known to one of ordinary skill in the art before the effective filing date of the claimed invention to protect underlying devices and electrically isolate adjacent conducting structures furthermore It would have been obvious to one of ordinary skill in the art, in view of the teachings of Tran, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007)..
Tran does not specify a second doped region between the first gate structure and the second gate structure
Bracchitta discloses in Fig. 4 with associated text a semiconductor device similar to that of Tran comprising a second doped region (n+ diffusion) (Fig. 4) between a first gate structure (40 and 42) (Fig. 4, col. 2, line 67- col. 3, line 4) and a second gate structure (gate of 12) (Fig. 4, col. 3, line 8) similar to those of Tran so that by including a first doped region 34 and second doped region (n+ diffusion) of Bracchitta in the device of Tran the device would comprise a second doped region between the first gate structure and the second gate structure
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a first doped region and second doped region similar to those of Bracchitta in the device of Tran because according to Bracchitta diffusions 34 that function as the FET device junctions extend below the recessed gate 40 is achieved by using sufficient ion implant energy, angled implants, or combinations of both, When a voltage is applied to gate element 40 it produces a high field point at the corners 38 of which catastrophically breaks down the oxide 42 at the corners and causes a short circuit between the gate element 40 and the implanted diffusions 34, thus providing a fuse function (col. 2, line 62- col. 3, line 7) the second doped region is well known to act as a source/drain region for transistor 12 so that such a structure would be useful in forming a fuse structure for an OTP in the device of Tran.
Regarding claim 12,Tran in view of Bracchitta teaches the first doped region contacts the second doped region directly (Bracchitta Fig. 4).
Regarding claim 13,Tran in view of Bracchitta teaches the first doped region and the second doped region comprise same conductive type ( n-type Bracchitta Fig. 4).
Regarding claim 14,Tran in view of Bracchitta teaches a concentration of the first doped region is less than a concentration of the second doped region (the first doped region is an n diffusion and the second doped region is a n+ diffusion Bracchitta Fig. 4)).
Response to Arguments
Applicant's arguments filed 01/06/2026 have been fully considered but they are not persuasive. Regarding the arguments on pages 6-7 Tran is relied upon to teach second spacer (structure not labeled on left side of gate structure) adjacent to another side of the first gate structure, wherein a second sidewall of the first gate structure directly contacting the second spacer is directly on the first doped region (Fig. 1 also see annotated Fig. above). Tseng is only relied upon to teach modifying the structure if Tran so that two similar gate structures are formed on the STI and adjacent semiconductor regions on each side instead of one so that the device similarly comprises a sidewall of a first gate structure (340 and 350) is directly contacting a first spacer (360 on right side of 340) is directly on the STI (Fig. 2, col. 5, lines 1-11). The device as modified would therefore comprise both a first sidewall of the first gate structure directly contacting the first spacer is directly on the STI and a second sidewall of the first gate structure directly contacting the second spacer is directly on the first doped region.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AARON J GRAY/Examiner, Art Unit 2897