Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
RCE, received 12/4/2025, has been entered.
Claims 1-7, 9-17 and 19-20 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10-11 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jun et al. (US Pub. No. 2018/0130796 A1), hereafter referred to as Jun.
As to claim 1, Jun discloses a method for fabricating a semiconductor device (figs 2 and 14; [0090]), comprising:
providing a substrate having a resistor region (substrate 100 with resistor region R2);
forming a STI (ST3) around the substrate (100) on the resistor region (R2);
forming a first gate structure (DGP) directly on the STI (ST3; fig 14 does not show DGP directly on ST3, however, [0096] clearly teaches that AP2 can be omitted such that DGP is directly on ST3 as shown in fig 8B) on the resistor region (R2);
forming a first interlayer dielectric layer (110) around the first gate structure (DGP);
transforming the first gate structure into a first metal gate ([0048]), wherein the first metal gate comprises:
a gate electrode (DE) on the substrate (100); and
a hard mask (DC) on the gate electrode (DE);
forming a second ILD layer (120) on the first metal gate (DGP);
forming a resistor (RP) on the first metal gate (DGP) and the second ILD (120); and
forming a first contact plug (fig 2, CS to the left of DGP) and a second contact plug (CS to the right of DGP) adjacent to two sides of the gate structure (DGP), wherein the first contact plug (CS) penetrates the resistor (RP) and the second ILD layer (120), and a bottom surface of the first contact plug is lower than a top surface of the first gate structure (bottom surface of CS is lower than top surface of DGP).
As to claim 10, Jun discloses the method of claim 1 (paragraphs above),
wherein a width of the first gate structure (DGP) is less than a width of the resistor (RP).
As to claim 11, Jun discloses a semiconductor device (figs 2 and 14), comprising:
a substrate (100) having a resistor region (R2);
a STI (ST3) around the substrate (100) on the resistor region (R2);
a first gate structure (DGP) on the resistor region (R2), wherein the first gate structure comprises:
a gate electrode (DE) on the substrate (100); and
a hard mask (DC) on the gate electrode (DE);
a first interlayer dielectric layer (110) around the first gate structure (DGP);
a second ILD layer (120) on the first gate structure (DGP);
a resistor (RP) directly on the first gate structure (DGP) and the second ILD layer (120); and
a first contact plug (CS on left of DGP) and a second contact plug (CS on right of DGP) adjacent to two sides of the gate structure (DGP), wherein the first contact plug (CS) penetrates the resistor (RP) and the second ILD (120), and a bottom surface of the first contact plug is lower than a top surface of the first gate structure (bottom surface of CS is lower than top surface of DGP).
As to claim 20, Jun discloses the semiconductor device of claim 11 (paragraphs above),
wherein a width of the first gate structure (DGP) is less than a width of the resistor (RP).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2-7, 9, 12-17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun in view of Choi et al. (US Pub. No. 2018/0151376 A1), hereafter referred to as Choi.
As to claim 2, Jun discloses the method of claim 1 (paragraphs above).
Jun does not disclose wherein the substrate comprises a transistor region (TA), however, does not explicitly disclose a low-voltage (LV) region and high-voltage (HV) region, the method further comprising:
forming the first gate structure on the resistor region, a second gate structure on the LV region, and a third gate structure on the HV region;
forming the first ILD layer around the first gate structure, the second gate structure, and the third gate structure;
transforming the first gate structure, the second gate structure, and the third gate structure into the first metal gate, a second metal gate, and a third metal gate;
forming a second ILD layer on the first metal gate, the second metal gate, and the third metal gate.
Nonetheless, Choi discloses a substrate comprising a LV region (fig 11, region a) and a HV region (region b), the method comprising:
forming the first gate structure on the resistor region (gate structure 110D in RA), a second gate structure on the LV region (Choi, figs 1-12, gate GP1 in region a), and a third gate structure on the HV region (Choi, figs 1-12, gate GP2 in region b);
forming the first ILD layer around the first gate structure, the second gate structure, and the third gate structure (ILD 13);
transforming the first gate structure, the second gate structure, and the third gate structure into the first metal gate, a second metal gate, and a third metal gate (metal gates GP1-2);
forming an ILD layer on the metal gate (170b);
forming a first contact plug and a second contact plug adjacent to two sides of the resistor (contact plugs).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the transistors of Jun in high-voltage and low-voltage regions as taught by Choi since this will provide improved integration of the semiconductor device (Choi, [0003]).
As to claim 3, Jun in view of Choi disclose the method of claim 2 (paragraphs above).
Jun further discloses wherein top surfaces of the first gate structure and the second gate structure are coplanar (fig 14, gates DGP and CGP).
Additionally, Choi further teaches that the gates GP1 and GP2 of the high and low voltage region transistors are also coplanar (fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the transistor gates of Choi coplanar with the dummy gates taught by Jun since this will provide improved easy of manufacture and uniformity of the semiconductor structure.
As to claim 4, Jun in view of Choi disclose the method of claim 2 (paragraphs above).
Jun further discloses wherein top surfaces of the first gate structure and the third gate structure are coplanar (fig 14, gates CGP and DGP);
Additionally, Choi further teaches that the gates GP1 and GP2 of the high and low voltage region transistors are also coplanar (fig 12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the transistor gates of Choi coplanar with the dummy gates taught by Jun since this will provide improved easy of manufacture and uniformity of the semiconductor structure.
As to claim 5, Jun in view of Choi disclose the method of claim 2 (paragraphs above).
Jun further discloses wherein forming the resistor (RP) comprises:
forming a metal layer on the second ILD layer (RP on 120); and
forming a cap layer on the metal layer (HM on RP).
As to claim 6, Jun in view of Choi disclose the method of claim 5 (paragraphs above).
Jun further discloses wherein a sidewall of the metal layer is aligned with a sidewall of the cap layer (RP and HM have aligned sidewalls).
As to claim 7, Jun in view of Choi disclose the method of claim 5 (paragraphs above).
Jun further discloses wherein the metal layer comprises tungsten nitride ([0057]).
As to claim 9, Jun in view of Choi disclose the method of claim 1 (paragraphs above).
Jun further discloses wherein the first gate structure is between the first contact plug and the second contact plug (gate DGP between plugs CS).
As to claim 12, Jun discloses the semiconductor device of claim 11 (paragraphs above),
Jun does not disclose wherein the substrate comprises a transistor region (TA), however, does not explicitly disclose a low-voltage (LV) region and high-voltage (HV) region, the semiconductor device further comprising:
the first gate structure on the resistor region, a second gate structure on the LV region, and a third gate structure on the HV region;
the first ILD layer around the first gate structure, the second gate structure, and the third gate structure;
a second ILD layer on the first gate structure, the second gate structure, and the third gate structure.
Nonetheless, Choi discloses a substrate comprising a LV region (fig 11, region a) and a HV region (region b), the device comprising:
forming the first gate structure on the resistor region (gate structure n RA), a second gate structure on the LV region (Choi, figs 1-12, gate GP1 in region a), and a third gate structure on the HV region (Choi, figs 1-12, gate GP2 in region b);
forming the first ILD layer around the first gate structure, the second gate structure, and the third gate structure (ILD 13);
transforming the first gate structure, the second gate structure, and the third gate structure into the first metal gate, a second metal gate, and a third metal gate (metal gates GP1-2);
forming an ILD layer on the metal gate (120);
the resistor on the second ILD layer on the resistor region (resistor on the of second ILD layer, same as Applicant’s is directly on the gate structure and on the of the second ILD layer);
forming a first contact plug and a second contact plug adjacent to two sides of the resistor (contact plugs).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the transistors of Jun in high-voltage and low-voltage regions as taught by Choi since this will provide improved integration of the semiconductor device (Choi, [0003]).
As to claim 13, Jun in view of Choi disclose the semiconductor device of claim 12 (paragraphs above).
Jun further discloses wherein top surfaces of the first gate structure and the second gate structure are coplanar (DGP and CGP).
Additionally, Choi further teaches that the gates GP1 and GP2 of the high and low voltage region transistors are also coplanar (fig 12).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the transistor gates of Choi coplanar with the dummy gates taught by Jun since this will provide improved easy of manufacture and uniformity of the semiconductor structure.
As to claim 14, Jun in view of Choi disclose the semiconductor device of claim 12 (paragraphs above).
Jun further discloses wherein top surfaces of the first gate structure and the third gate structure are coplanar (DGP and CGP);
Additionally, Choi further teaches that the gates GP1 and GP2 of the high and low voltage region transistors are also coplanar (fig 12).
It would have been obvious to one of ordinary skill in the art at the time the application was effectively filed to form the transistor gates of Choi coplanar with the dummy gates taught by Jun since this will provide improved easy of manufacture and uniformity of the semiconductor structure.
As to claim 15, Jun in view of Choi disclose the semiconductor device of claim 12 (paragraphs above).
Jun further discloses wherein forming the resistor (RP) comprises:
forming a metal layer on the second ILD layer (RP on 120); and
forming a cap layer on the metal layer (HM on RP).
As to claim 16, Jun in view of Choi disclose the semiconductor device of claim 15 (paragraphs above).
Jun further discloses wherein a sidewall of the metal layer is aligned with a sidewall of the cap layer (RP and HM have aligned sidewalls).
As to claim 17, Jun in view of Choi disclose the semiconductor device of claim 15 (paragraphs above).
Jun further discloses wherein the metal layer comprises tungsten nitride ([0057]).
As to claim 19, Jun in view of Choi disclose the semiconductor device of claim 11 (paragraphs above).
Jun further discloses wherein the first gate structure is between the first contact plug and the second contact plug (gate DGP between plugs CS).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-7, 9-17 and 19-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2009/0039423 A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 1/22/2026