DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 03/18/2026 has been entered. Claims 1 and 10 have been amended, and Claims 7 and 16 have been cancelled. Applicant’s amendments to the claims are noted.
Claims 1-6, 8-15, and 17-18 remain pending in the application.
Response to Arguments
Applicant's arguments filed on 03/18/2026 have been fully considered but they are not persuasive. Regarding the arguments on pages 6-10, Emoto (US20030045029A1) teaches at least one support member disposed on the first side of the carrier structure (Para [0034], base member 17 is mounted on the substrate 11), wherein the support member is a metal bulk (Para [0035], base member 17 is a metal), and a coefficient of thermal expansion of the support member and a coefficient of thermal expansion of the first electronic element belong to a same level (Applicant defines ‘belong to the same level’ as a CTE that is ‘close to’ that of the first electronic element in para [0030]. Emoto teaches the base member 17 may preferably be formed from a material that has a small difference in the thermal expansion coefficient with respect to the first and second chips 12 in para [0035], which is consistent with and reads on Applicant’s own definition of ‘same level’).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 5-6 and 14-15 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Claims 1 and 10, as amended, already limits the support member to “a metal bulk.” Claims 5-6 and 14-15 improperly broaden this limitation by introducing “semiconductor material” and “dummy die” as an alternatives inconsistent with the metal bulk limitation of claim 1. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-14, and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Emoto (US20030045029A1), and further in view of Lee (US20060267609A1).
Regarding claim 1, Emoto teaches an electronic package (Fig. 1, semiconductor device), comprising:
a carrier structure having a first side and a second side opposing the first side (Fig. 4, substrate 11);
a first electronic element disposed on the first side of the carrier structure and electrically connected to the carrier structure (Para [0032] and Fig. 1, first chip 12 mounted on the substrate 11);
at least one support member disposed on the first side of the carrier structure (Para [0034], base member 17 is mounted on the substrate 11), wherein the support member is a metal bulk (Para [0035], base member 17 is a metal), and a coefficient of thermal expansion of the support member and a coefficient of thermal expansion of the first electronic element belong to a same level (Applicant defines ‘belong to the same level’ as a CTE that is ‘close to’ that of the first electronic element in para [0030]. Emoto teaches the base member 17 may preferably be formed from a material that has a small difference in the thermal expansion coefficient with respect to the first and second chips 12 in para [0035], which is consistent with and reads on Applicant’s own definition of ‘same level’),
wherein a height of the support member is equal to a height of a first electronic element (Fig. 1, second chip 13 is affixed on the first chip 12 and supported by base member 17; thereby the height of the first chip 12 and the base member 17 are same); and
a second electronic element disposed on the at least one support member (Para [0034], second chip 13 is supported by the base member 17), and electrically connected to the carrier structure (Para [0033], second chip 13 is wire-bonded to the interposer substrate 11 by wires 15), wherein the second electronic element has a planar dimension greater than a planar dimension of the first electronic element (Para [0033], second chip 13 has a larger measurement than the first chip 12).
But Emoto does not teach a spacer disposed on the first electronic element, wherein a height of the support member is equal to a sum of a height of the first electronic element and a height of the spacer, wherein the spacer is buffer die, a shield, a heat sink, or a functional chip; and
a second electronic element disposed on the spacer.
However, Lee teaches a spacer disposed on the first electronic element (Fig. 8 and Para [0041], spacer 86 is affixed to the bottom die 814), wherein a height of the support member is equal to a sum of a height of the first electronic element and a height of the spacer (Para [0041], dimension for the clearance 81 is determined as the sum of the thicknesses of the lower die 814 and the spacer 86, plus the thicknesses of the adhesives 83, 87), wherein the spacer is buffer die, a shield, a heat sink, or a functional chip (Para [0005], spacer such as a chip); and
a second electronic element disposed on the spacer (Fig. 8 and Para [0041], the second die or package 824 is affixed to the spacer 86).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Emoto (US20030045029A1) to further include a spacer disposed on the first electronic element as taught by Lee (US20060267609A1). Both Emoto and Lee address the same technical problem of supporting an overhanging upper chip in a stacked package structure. Incorporating Lee's spacer into Emoto's structure would provide additional clearance for accommodating wire bonds between the first electronic element and the carrier structure, while maintaining Emoto's metal bulk support member with CTE matching benefits. Such a combination involves only the combination of familiar elements using known methods to yield predictable results.
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Regarding claim 10, Emoto teaches a method of manufacturing an electronic package (Fig. 1, semiconductor device), comprising:
Providing a carrier structure having a first side and a second side opposing the first side (Fig. 4, substrate 11);
Disposing a first electronic element (Para [0032] and Fig. 1, first chip 12 mounted on the substrate 11) and at least one support member on the first side of the carrier structure (Para [0034], base member 17 is mounted on the substrate 11), wherein the support member is a metal bulk (Para [0035], base member 17 is a metal), and a coefficient of thermal expansion of the support member and a coefficient of thermal expansion of the first electronic element belong to a same level (Applicant defines ‘belong to the same level’ as a CTE that is ‘close to’ that of the first electronic element in para [0030]. Emoto teaches the base member 17 may preferably be formed from a material that has a small difference in the thermal expansion coefficient with respect to the first and second chips 12 in para [0035], which is consistent with and reads on Applicant’s own definition of ‘same level’),
wherein a height of the support member is equal to a height of a first electronic element (Fig. 1, second chip 13 is affixed on the first chip 12 and supported by base member 17; thereby the height of the first chip 12 and the base member 17 are same); and
disposing a second electronic element disposed on the at least one support member (Para [0034], second chip 13 is supported by the base member 17), and electrically connected to the carrier structure (Para [0033], second chip 13 is wire-bonded to the interposer substrate 11 by wires 15), wherein the second electronic element has a planar dimension greater than a planar dimension of the first electronic element (Para [0033], second chip 13 has a larger measurement than the first chip 12).
But Emoto does not teach disposing a spacer on the first electronic element, wherein a height of the support member is equal to a sum of a height of the first electronic element and a height of the spacer, wherein the spacer is buffer die, a shield, a heat sink, or a functional chip; and disposing a second electronic element on the spacer.
However, Lee teaches disposing a spacer on the first electronic element (Fig. 8 and Para [0041], spacer 86 is affixed to the bottom die 814), wherein a height of the support member is equal to a sum of a height of the first electronic element and a height of the spacer (Para [0041], dimension for the clearance 81 is determined as the sum of the thicknesses of the lower die 814 and the spacer 86, plus the thicknesses of the adhesives 83, 87), wherein the spacer is buffer die, a shield, a heat sink, or a functional chip (Para [0005], spacer such as a chip); and
disposing a second electronic element on the spacer (Fig. 8 and Para [0041], the second die or package 824 is affixed to the spacer 86).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Emoto (US20030045029A1) to further include a spacer disposed on the first electronic element as taught by Lee (US20060267609A1). Both Emoto and Lee address the same technical problem of supporting an overhanging upper chip in a stacked package structure. Incorporating Lee's spacer into Emoto's structure would provide additional clearance for accommodating wire bonds between the first electronic element and the carrier structure, while maintaining Emoto's metal bulk support member with CTE matching benefits. Such a combination involves only the combination of familiar elements using known methods to yield predictable results.
Regarding claims 2 and 11, Emoto in view of Lee teaches the electronic package of claim 1 and method of claim 10, wherein the first electronic element is electrically connected to the carrier structure via a plurality of first bonding wires (Fig. 8 of Lee, first die 814 is interconnected with the substrate 82 by wire bonds 817).
Regarding claims 3 and 12, Emoto in view of Lee teaches the electronic package of claim 1 and method of claim 10, wherein the second electronic element is electrically connected to the carrier structure via a plurality of second bonding wires (Fig. 8 of Lee, second die 8224 is interconnected with the substrate 82 by wire bonds 827).
Regarding claims 4 and 13, Emoto in view of Lee teaches the electronic package of claim 1 and method of claim 10, wherein the spacer has a planar dimension less than the planar dimension of the first electronic element (Fig. 8, smaller spacer 86 than the first die 814).
Regarding claims 5 and 14, Emoto in view of Lee teaches the electronic package of claim 1 and method of claim 10, wherein the at least one support member comprises a semiconductor material or a metal material (support member is a metal bulk (Para [0035] of Emoto, base member 17 is a metal).
Regarding claims 8 and 17, Emoto in view of Lee teaches the electronic package of claim 1, further comprising a packaging layer formed on the carrier structure and encapsulating the first electronic element, the second electronic element, the spacer and the at least one support member (Fig. 8 and Para [0037] of Emoto, first chip 12, the second chip 13 and the base member 17 are molded by a sealing resin 16).
Regarding claims 9 and 18, Emoto in view of Lee teaches the electronic package of claim 1 and method of claim 10, further comprising a plurality of conductive elements formed on the second side of the carrier structure and electrically connected to the carrier structure (Fig. 1 and Para [0037] of Emoto, on the opposite side of the chip-mounting side of the interposer substrate 11 are provided solder balls 18 that are connection members to be used for mounting on a printed wire board. The stacked package and the printed wiring board are electrically connected by the solder balls 18).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at (571) 271-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/JAHAE KIM/Examiner, Art Unit 2897
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