DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 7 are objected to because of the following informalities: each of claims 1 and 7 recite a typo in the language “a second current is measured to determines a second logic value” in the second amended limitation of the set of amended limitations. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-7, 11-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over US 2008/0233694 A1 to Li (hereinafter “Li” – previously cited reference) and further in view of US 2020/0227551 A1 to Ranmuthu (hereinafter “Ranmuthu” – newly cited reference).
Regarding claim 1, Li teaches a method of manufacturing a semiconductor device (method of manufacturing CMOS device 100; abstract; Figs. 1-9; paragraphs [0039], [0075]) comprising:
providing a substrate (workpiece 102 comprising SOI substrate; paragraph [0039]);
forming a plurality of gate electrodes simultaneously on the substrate (forming of first and second gate materials 122, 128 simultaneously upon workpiece 102 to form PMOS and NMOS transistors 136, 138; Figs. 7-8; paragraphs [0040], [0047]-[0048], [0055]-[0056], [0061]), and forming a plurality of doped regions formed in the substrate (doped first and second regions 104, 106 formed in substrate 102 which may be separated by an optional STI region 108 as shown in Fig. 9; paragraphs [0040]-[0041]);
providing a first reticle to expose a first gate electrode of the plurality of gate electrodes and to cover a second gate electrode of the plurality of gate electrodes (first mask is provided to expose first region 104 having second gate material 128 while second region 106 having first gate material 122 is masked; Fig. 8; paragraph [0065]);
after providing the first reticle, doping the first gate electrode of the plurality of gate electrodes through the first reticle with a first dopant of a first conductive type (first region 104 having second gate material 128 may be implanted with p-type dopants through first mask; Fig. 8; paragraph [0065]);
providing a second reticle to expose the second gate electrode of the plurality of gate electrodes and to cover the first gate electrode of the plurality of gate electrodes (second mask is provided to expose second region 106 having first gate material 122 while first region 104 having second gate material 122 is masked; Fig. 8; paragraph [0065]); and
after providing the second reticle, doping the second gate electrode of the plurality of gate electrodes through the second reticle with a second dopant of a second conductive type (second region 106 having first gate material 122 may be implanted with n-type dopants through second mask; Fig. 8; paragraph [0065]), and the first conductive type of the first dopant and the second conductive type of the second dopant respectively implanted in the first gate electrode and the second gate electrode of the plurality of gate electrodes are different (first and second regions 104, 106 doped with different n- an p-type dopants; Fig. 8; paragraph [0065]), wherein a first transistor comprising the first gate electrode has a first threshold voltage, and a second transistor comprising the second gate electrode has a second threshold voltage different from the first threshold voltage (PMOS transistor 136 having gate material 128 and NMOS transistor 138 having gate material 122 collectively comprising opposite threshold voltage values; Figs. 8 and 9; paragraphs [0063]-[0064], [0092]), wherein the first gate electrode and the second gate electrode are configured to store information or data (gate electrode material 122, 128 each having respective threshold voltage values capable of storing logic values; Figs. 8 and 9; paragraphs [0063]-[0064], [0092]).
Li fails to disclose wherein the plurality of doped regions includes only one shared source or only one shared drain which is disposed between two of the plurality of gate electrodes, wherein the only one shared source or the only shared drain is disposed between the first gate electrode and the second gate electrode of the plurality of gate electrodes; and wherein when the first transistor is turned on, a first current is measured to determine a first logic value and when the second transistor is turned on, a second current is measured to determines a second logic value different from the first logic value.
However, Ranmuthu discloses wherein the plurality of doped regions includes only one shared source or only one drain which is disposed between two of the plurality of gate electrodes, wherein the only one shared source or the only shared drain is disposed between the first portion and the second portion of the plurality of gate electrodes (first and second power FETs 204, 206 share a common drain disposed between respective gate electrodes; Fig. 2; paragraphs [0021]-[0022]); wherein when the first transistor is turned on, a first current is measured to determine a first logic value and when the second transistor is turned on, a second current is measured to determines a second logic value different from the first logic value (current sensing FETs 214, 216 share drain with FETs 204, 206 and sense current therethrough in order to output a corresponding value to controller 212 for adjusting gate-source voltage Vgs to FETs 204, 206; Fig. 2; paragraphs [0021]-[0022], [0033]).
Li and Ranmuthu are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Li to incorporate the teaching of Ranmuthu in order to potentially provide reduced area and increased density, lower parasitic capacitance, improved power efficiency, and simplified fabrication as well as the ability to assign logic values in memory for operating any type of electronic device.
Regarding claim 3, Li in view of Ranmuthu discloses the method of claim 1. Li further discloses forming a first photosensitive material on the substrate (photoresist 124 formed upon workpiece 102; Fig. 3; paragraph [0051]), wherein the first photosensitive material defines an opening exposing the first portion of the plurality of gate electrodes (photoresist 124 exposes a portion of first gate material 122 as shown in Fig. 3; paragraph [0051]).
Regarding claim 5, Li in view of Ranmuthu discloses the method of claim 1. Li further discloses a pattern of the first reticle is different from a pattern of the second reticle (masks 123, 129 are patterned distinctly as shown in Figs. 3-6; paragraphs [0051]-[0052], [0058]-[0059]).
Regarding claim 6, Li in view of Ranmuthu discloses the method of claim 1. Li further discloses the plurality of gate electrodes are arranged in an array (first and second gate materials 122, 128 form PMOS and NMOS transistors 136, 138 which are arranged in an array upon workpiece 102 as shown in Fig. 9; paragraph [0065]).
Regarding claim 7, Li teaches a method of manufacturing a semiconductor device (method of manufacturing CMOS device 100; abstract; Figs. 1-9; paragraphs [0039], [0075]), comprising:
providing a substrate (workpiece 102 comprising SOI substrate; paragraph [0039]);
forming a plurality of first gate electrodes and a plurality of second gate electrodes in an array simultaneously on the substrate (forming of first and second gate materials 122, 128 simultaneously upon workpiece 102 to form PMOS and NMOS transistors 136, 138 in a 2x1 or 1x2 array as shown in Fig. 9, where each of the first and second gate materials 122, 128 may comprise a plurality of stacked gate materials; Figs. 7-9; paragraphs [0040], [0047]-[0048], [0055]-[0056], [0061], [0065]), and forming a plurality of doped regions formed in the substrate (doped first and second regions 104, 106 formed in substrate 102 which may be separated by an optional STI region 108 as shown in Fig. 9; paragraphs [0040]-[0041]);
providing a first reticle to expose the plurality of first gate electrodes and to cover the plurality of second gate electrodes (first mask is provided to expose first region 104 having second gate material 128 while second region 106 having first gate material 122 is masked; Fig. 8; paragraph [0065]);
after providing the first reticle, implanting a first dopant of a first conductive type through the first reticle into the plurality of first gate electrodes (first region 104 having second gate material 128 may be implanted with p-type dopants through first mask; Fig. 8; paragraph [0065]); and
providing a second reticle to expose the plurality of second gate electrodes and to cover the plurality of first gate electrodes (second mask is provided to expose second region 106 having first gate material 122 while first region 104 having second gate material 122 is masked; Fig. 8; paragraph [0065]);
after providing the second reticle, implanting a second dopant of a second conductive type into the plurality of second gate electrodes through the second reticle (second region 106 having first gate material 122 may be implanted with n-type dopants through second mask; Fig. 8; paragraph [0065]), wherein the second conductive type of the second dopant implanted into the plurality of second gate electrodes is different from the first conductive type of the first dopant implanted into the plurality of first gate electrodes (first and second regions 104, 106 doped with different n- an p-type dopants; Fig. 8; paragraph [0065]), wherein a first transistor comprising the first gate electrode has a first threshold voltage, and a second transistor comprising the second gate electrode has a second threshold voltage different from the first threshold voltage (PMOS transistor 136 having gate material 128 and NMOS transistor 138 having gate material 122 collectively comprising opposite threshold voltage values; Figs. 8 and 9; paragraphs [0063]-[0064], [0092]), wherein the first gate electrode and the second gate electrode are configured to store information or data (gate electrode material 122, 128 each having respective threshold voltage values capable of storing logic values; Figs. 8 and 9; paragraphs [0063]-[0064], [0092]).
Li fails to disclose wherein the plurality of doped regions includes only one shared source or only one shared drain which is disposed between one of the plurality of first gate electrodes and one of the plurality of second gate electrodes, wherein the only one shared source or the only one shared drain is disposed between one of the plurality of first gate electrodes and one of the plurality of second gate electrodes; wherein when the first transistor is turned on, a first current is measured to determine a first logic value and when the second transistor is turned on, a second current is measured to determines a second logic value different from the first logic value.
However, Ranmuthu discloses wherein the plurality of doped regions includes only one shared source or only one shared drain which is disposed between one of the plurality of first gate electrodes and one of the plurality of second gate electrodes, wherein the only one shared source or the only one shared drain is disposed between one of the plurality of first gate electrodes and one of the plurality of second gate electrodes (first and second power FETs 204, 206 share a common drain disposed between respective gate electrodes; Fig. 2; paragraphs [0021]-[0022]); wherein when the first transistor is turned on, a first current is measured to determine a first logic value and when the second transistor is turned on, a second current is measured to determines a second logic value different from the first logic value (current sensing FETs 214, 216 share drain with FETs 204, 206 and sense current therethrough in order to output a corresponding value to controller 212 for adjusting gate-source voltage Vgs to FETs 204, 206; Fig. 2; paragraphs [0021]-[0022], [0033]).
Li and Ranmuthu are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Li to incorporate the teaching of Ranmuthu in order to potentially provide reduced area and increased density, lower parasitic capacitance, improved power efficiency, and simplified fabrication as well as the ability to assign logic values in memory for operating any type of electronic device.
Regarding claim 11, Li in view of Ranmuthu discloses the method of claim 7. Li further discloses at least one of the first gate electrodes comprises a charge trapping material (both PMOS and NMOS transistors 136, 138 comprise gate dielectric materials GD1, GD2; Fig. 9; paragraph [0068]).
Regarding claim 12, Li in view of Ranmuthu discloses the method of claim 11. Li further discloses at least one of the first gate electrodes comprises polysilicon (both gate materials 122, 128 may comprise polysilicon; paragraphs [0047], [0055]).
Regarding claim 14, Li in view of Ranmuthu discloses the method of claim 7. Li further discloses the first transistor has a first channel region in the substrate (PMOS 136 comprising first channel region C1; Fig. 9; paragraph [0068]), the second transistor has a second channel region in the substrate (PMOS 138 comprising second channel region C2; Fig. 9; paragraph [0068]), at least one of the first dopant and the second dopant is free from being doped in the first channel region and the second doped region (channel region C1 free from n-type dopant and channel region C2 free from p-type dopant as shown in Fig. 9; paragraph [0068]).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Li and Ranmuthu as applied to claim 7 above, and further in view of US 2019/0393240 A1 to Kim et al. (hereinafter “Kim” – previously cited reference).
Regarding claim 8, Li in view of Ranmuthu discloses the method of claim 7. Li further discloses the array comprises a first row and a second row (first and second gate materials 122, 128 form PMOS and NMOS transistors 136, 138 which are arranged in a 2x1 or 1x2 array upon workpiece 102 as shown in Fig. 9; paragraph [0065]).
Li fails to disclose an amount of the first gate electrodes in the first row is different from an amount of the first gate electrodes in the second row.
However, Kim teaches an amount of the first gate electrodes in the first row is different from an amount of the first gate electrodes in the second row (successive rows with different amount of gate electrode in each gate stack structure GS as shown in Fig. 4; paragraphs [0047]-[0050]).
Li and Kim are both considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Li to incorporate the teachings of Kim and provide the differing amount of gate electrodes between rows in order to assign unique logic values to specific rows.
Regarding claim 9, Li in view of Ranmuthu discloses the method of claim 7. Li further discloses the array comprises a first row and a second row (first and second gate materials 122, 128 form PMOS and NMOS transistors 136, 138 which are arranged in a 2x1 or 1x2 array upon workpiece 102 as shown in Fig. 9; paragraph [0065]).
Li fails to disclose an arrangement of the first gate electrodes and the second gate electrodes in the first row is different from an arrangement of the of the first gate electrodes and the second gate electrodes in the second row.
However, Kim teaches an arrangement of the first gate electrodes and the second gate electrodes in the first row is different from an arrangement of the of the first gate electrodes and the second gate electrodes in the second row (successive rows with different arrangement of gate electrodes in each gate stack structure GS as shown in Fig. 4; paragraphs [0047]-[0050]).
Li and Kim are both considered to be analogous to the claimed invention because they are in the same field of semiconductor memory devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Li to incorporate the teachings of Kim and provide the differing arrangement of gate electrodes between rows in order to assign unique logic values to specific rows.
Regarding claim 10, Li in view of Ranmuthu and Kim discloses the method of claim 9. Li further discloses an amount of the first gate electrodes in the first row is the same as an amount of the first gate electrodes in the second row (first and second gate materials 122, 128 form PMOS and NMOS transistors 136, 138 which are arranged in a 2x1 or 1x2 array upon workpiece 102 as shown in Fig. 9; paragraph [0065]).
Response to Arguments
Applicant's arguments filed August 21, 2025 have been fully considered but are moot in view of the new ground of rejection using Li in view of Ranmuthu that was necessitated by Applicant’s amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818