DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 31, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “the fifth metal oxide layer” in lines 4-5. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, the examiner will not consider this limitation. Clarification is requested.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 6 and 16, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara (2013/0337625) in view of Zurcher et al. (6,344,413) and Kang (2021/0359082).
Fujiwara shows in Figs. 9A-29A, 9B-29B and related text:
As for claims 1 and 16, a method for preparing a memory device, comprising:
(providing a semiconductor substrate 1 having an active region 1A (Figs. 9A-9B);)
forming a doped region 11 in a semiconductor substrate 1 (Figs. 12A-12B; [0072]);
(forming a first source/drain region 11/26 and a second source/drain region 11/37 in the active region (Figs. 12A-12B; 19A-19B; 24A-24B;)
forming a word line 23 (extending across the active region) across the doped region such that a first source/drain region 11/26 and a second source/drain region 11/37 are formed in the doped region and (deposited) at opposite sides of the word line (Figs. 14A-24A; 14B-24B);
forming a bit line 30 over and electrically connected to the first source/drain region (Figs. 21A-21B);
depositing a dielectric layer 44 over the second source/drain region and etching the dielectric layer to form an opening 44A over the second source/drain region (Figs. 27A-28A; 27B-28B);
forming a capacitor 48 in the opening of the dielectric layer and electrically connected to the second source/drain region (Figs. 28A-29A; 28B-29B), comprising:
forming a bottom electrode 45;
forming a capacitor dielectric structure 46 over the bottom electrode, comprising:
forming a first metal oxide layer (zirconium oxide) of 46 disposed over the bottom electrode;
forming a second metal oxide layer (aluminum oxide) of 46 over the first metal oxide layer ([0091]);
wherein a material the first metal oxide layer and a material of the second metal oxide layer are different from each other; and
forming a top electrode 47 over the capacitor dielectric structure,
wherein the capacitor dielectric structure separated from the dielectric layer via the bottom electrode.
Fujiwara does not disclose forming the capacitor dielectric structure comprising forming a third metal oxide layer over the second metal oxide layer, forming a fourth metal oxide layer over the third metal oxide layer, wherein the material of the first metal oxide layer, the material of the second metal oxide layer, and a material of the third metal oxide layer are different from each other, wherein the second metal oxide layer and the fourth metal oxide layer comprise Al2O3, the top electrode in direct contact with the fourth metal oxide layer; a top surface of the bottom electrode, a top surface of the top electrode and a top surface of the capacitor dielectric structure are coplanar (claims 1 and 16); the material of first metal oxide layer, a material of the fourth metal oxide layer, and a material of the fifth metal oxide layer are different from each other (claim 6).
As for claims 1 and 16, Zurcher et al. teach in Figs. 3-7 and related text a top surface of the bottom electrode, a top surface of the top electrode and a top surface of the capacitor dielectric structure are coplanar.
Kang teaches in Fig. 2 (5, 11 or 20) and related text:
As for claims 1 and 16, forming a capacitor dielectric structure ML12 (ML15, ML21 or ML28) over the bottom electrode BE, comprising:
forming a first metal oxide layer HK1 disposed over the bottom electrode;
forming a second metal oxide layer HBG over the first metal oxide layer; and
forming a third metal oxide layer LBL over the second metal oxide layer; and
forming a fourth metal oxide layer ICL over the third metal oxide layer, wherein a material of the first metal oxide layer ([0057]: zirconium oxide), a material of the second metal oxide layer ([0055]: aluminum oxide), and a material of the third metal oxide layer ([0076]: aluminum-doped zirconium oxide or beryllium-doped zirconium oxide) are different from each other, wherein the second metal oxide layer and the fourth metal oxide layer comprise Al2O3 ([0055]; [0081]).
As for claim 6, the material of the first metal oxide layer, a material of the fourth metal oxide layer, and a material of the fifth metal oxide layer are different from each other ([0057], [0081]).
Fujiwara, Zurcher et al. and Kang are analogous art because they are directed to a method of forming a capacitor structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fujiwara with the specified feature(s) of Zurcher et al. and Kang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form a top surface of the bottom electrode, a top surface of the top electrode and a top surface of the capacitor dielectric structure being coplanar, as taught by Zurcher et al., and to include the capacitor dielectric structure comprising four layered metal oxide layers, wherein the material of the first metal oxide layer, the material of the second metal oxide layer, and a material of the third metal oxide layer being different from each other, wherein the second metal oxide layer and the fourth metal oxide layer comprising Al2O3, the top electrode in direct contact with the fourth metal oxide layer, and the material of first metal oxide layer, a material of the fourth metal oxide layer, and a material of the fifth metal oxide layer being different from each other, as taught by Kang, in Fujiwara's device, in order to improve dielectric properties, reduce parasitic effects, increase capacitance, reduce leakage current and improve electrical liability of the device.
As for claim 2, the combined device shows the first metal oxide layer comprises ZrO2 (Fujiwara: [0091]; Kang: [0057]).
Claim(s) 3-5, 8, 17, 19 and 20, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara (2014/0291804), Zurcher et al. (6,344,413) and Kang (2021/0359082) in view of Wei et al. (2022/0278115) and Chen et al. (2022/0301785).
As for claims 3-5, 8 and 17-20, Fujiwara, Zurcher et al. and Kang disclosed substantially the entire claimed invention, as applied to claims 1 and 16, respectively, above, except the third metal oxide layer comprises ZrO2 doped with a first dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements (claim 3); a concentration of the first dopant in the third metal oxide layer is less than a concentration of Zr in the third metal oxide layer (claim 4); an atomic percentage of the first dopant in the third metal oxide layer is less than 20% (claim 5); and the third metal oxide layer comprise ZrO2 doped with a second dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements (claim 8); the first metal oxide layer is formed by depositing ZrO2, and the third metal oxide layer is formed by depositing ZrO2 with a dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements (claim 17); the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer are formed by atomic layer deposition (ALD) processes (claim 19); and a number of ALD cycles of the dopant occupies less than 20% of a number of total ALD cycles of the third metal oxide layer (claim 20).
Wei et al. teach in Fig. 2B and related text:
As for claim 3, the third metal oxide layer 120b comprises ZrO2 doped with a first dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements ([0023]).
As for claim 4, a concentration of the first dopant in the third metal oxide layer is less than a concentration of Zr in the third metal oxide layer ([0023], lines 46-48, when FSL 120a excludes a dopant and FSL 120b includes a dopant).
As for claim 5, an atomic percentage of the first dopant in the third metal oxide layer is less than 20% ([0023], lines 46-48).
As for claim 8, the third metal oxide layer comprise ZrO2 doped with a dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements ([0023]).
As for claim 17, the first metal oxide layer 120a is formed by depositing ZrO2, and the third metal oxide layer is formed by depositing ZrO2 with a dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements ([0023]; [0028]; [0048]).
As for claim 19, the first metal oxide layer 120a, the second metal oxide layer 122a, and the third metal oxide layer 120b are formed by atomic layer deposition (ALD) processes ([0048]).
Alternative, Chen et al. teach in Fig. 1 and related text:
As for claims 3, 8 and 17, the dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements ([0031]).
Fujiwara, Zurcher et al. Kang, Wei et al. and Chen et al. are analogous art because they are directed to a method of forming a capacitor structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fujiwara, Zurcher et al. and Kang with the specified feature(s) of Wei et al. and Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include ZrO2 doped with a dopant, as taught by Wei et al., wherein the dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements, as taught by Chen et al., in Fujiwara and Zurcher et al. and Kang's device, in order to increase dielectric constant, reduce crystallinity, minimize leakage current and improve the performance of the device.
As for claim 20, Fujiwara, Wei et al., Zurcher et al. and Chen et al. disclosed substantially the entire claimed invention, as applied to claims 19 above, except a number of ALD cycles of the dopant occupies less than about 20% of a number of total ALD cycles of the third metal oxide layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a number of ALD cycles of the dopant occupies less than about 20% of a number of total ALD cycles of the third metal oxide layer, in order to optimize the performance of the device. Furthermore, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Claim(s) 9-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara (2014/0291804) in view of Zurcher et al. (6,344,413), Kang (2021/0359082) Wei et al. (2022/0278115) and Chen et al. (2022/0301785).
As for claims 9 and 10, Fujiwara shows in Figs. 9A-29A, 9B-29B and related text a method for preparing a memory device, comprising:
providing a semiconductor substrate 1 having an active region 1A (Figs. 9A-9B);
forming a first source/drain region 11/26 and a second source/drain region 11/37 in the active region (Figs. 12A-12B; 19A-19B; 24A-24B;)
forming a word line 23 extending across the active region, wherein the first source/drain region and the second source/drain region are deposited at opposite sides of the word line (Figs. 14A-24A; 14B-24B);
forming a bit line 30 over and electrically connected to the first source/drain region (Figs. 21A-21B);
depositing a dielectric layer 44 over the second source/drain region and etching the dielectric layer to form an opening 44A over the second source/drain region (Figs. 27A-28A; 27B-28B);
forming a capacitor 48 in the opening of the dielectric layer and electrically connected to the second source/drain region (Figs. 28A-29A; 28B-29B), wherein the capacitor comprises a bottom electrode 45, a top electrode 47, and a capacitor dielectric structure 46 between the bottom electrode and the top electrode (Figs. 29A-29B), wherein the capacitor dielectric structure separated from the dielectric layer via the bottom electrode, and
wherein forming the capacitor dielectric structure comprises forming a first metal oxide layer (zirconium oxide) of 46 disposed over the bottom electrode, forming a second metal oxide layer (aluminum oxide) of 46 over the first metal oxide layer.
Fujiwara does not disclose a top surface of the bottom electrode, a top surface of the top electrode and a top surface of the capacitor dielectric structure are coplanar; forming the capacitor dielectric structure comprising forming a third metal oxide layer over the second metal oxide layer, and forming a fourth metal oxide layer over the third metal oxide layer and in direct contact with the top electrode, and wherein the third metal oxide layer comprises ZrO2 doped with a first dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements, wherein the second metal oxide layer and the fourth metal oxide layer comprise Al2O3 (claim 9); a crystallinity of the first metal oxide layer is higher than a crystallinity of the third metal oxide layer (claim 10).
As for claim 9, Zurcher et al. teach in Figs. 3-7 and related text a top surface of the bottom electrode, a top surface of the top electrode and a top surface of the capacitor dielectric structure are coplanar.
As for claim 9, Kang teaches in Fig. 2 (5, 11 or 20) and related text forming the capacitor dielectric structure ML12 (ML15, ML21 or ML28) comprises forming a first metal oxide layer HK1 disposed over the bottom electrode BE, forming a second metal oxide layer HBG over the first metal oxide layer, forming a third metal oxide layer LBL over the second metal oxide layer, and forming a fourth metal oxide layer ICL over the third metal oxide layer and in direct contact with the top electrode TE, wherein the third metal oxide layer comprises ZrO2 doped with a first dopant ([0076]: aluminum-doped zirconium oxide or beryllium-doped zirconium oxide) and wherein the second metal oxide and the fourth metal oxide comprise Al2O3 ([0055]; [0081])
Wei et al. teach in Fig. 2B and related text:
As for claim 9, the third metal oxide layer 120b comprises ZrO2 doped with a dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements ([0023]).
As for claim 10, a crystallinity of the first metal oxide layer 120a is higher than a crystallinity of the third metal oxide layer (Wei: [0023], lines 46-48; [0025], lines 27-28; note: crystallinity reduces as the impurity concentration is higher or as the thickness is lower).
Alternative, as for claim 9, Chen et al. teach in Figs. 1 and related text:
the first dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements; and the second dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements ([0031]).
Fujiwara, Kang, Zurcher et al., Wei et al. and Chen et al. are analogous art because they are directed to a method of forming a capacitor structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fujiwara with the specified feature(s) of Kang, Zurcher et al., Wei et al. and Chen et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a top surface of the bottom electrode, a top surface of the top electrode and a top surface of the capacitor dielectric structure being coplanar, as taught by Zurcher et al., to include the capacitor dielectric structure comprising four-layered metal oxide layers, wherein the second metal oxide layer and the fourth metal oxide layer comprising Al2O3, and the fourth metal oxide layer in direct contact with the top electrode, as taught by Kang, to include ZrO2 doped with a dopant, as taught by Wei et al., and to include the dopant selected from the group consisting of Hf, Ta, La, Gd, Y, Sc, Ga, and lanthanide elements, as taught by Chen et al., in Fujiwara's device, in order to increase dielectric constant, reduce crystallinity, minimize leakage current and improve electrical reliability and the performance of the device.
As for claim 11, the combined device shows the top electrode and the bottom electrode of the capacitor comprise TiN (Fujiwara: [0009]).
As for claim 12, the combined device shows the first metal oxide layer comprises ZrO2 (Fujiwara: [0091]; Kang: [0057]; Wei: [0023], [0024] and [0028])).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-6, 8-12, 16, 17, 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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