DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/06/2026 has been entered.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15 in the reply filed on 08/13/2025 is acknowledged. Claims 16-30 are withdrawn from consideration.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant argued the combination of references does not teach or render obvious the invention as claimed because Xin does not teach the second conductive layer disposed in a groove of the first planarization layer and Wang does not teach the second conductive layer overlaps a groove of an insulating layer.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Xin teaches the first planarization layer, 12 in Figure 26, comprising the fourth portion which overlaps the first groove 131 of the insulating layer 13, and the second conductive layer 212/21/DATA comprising the fourth conductive portion disposed on the fourth portion of the first planarization layer, overlapping the first groove of the insulating layer.
Xin differs from Applicant's invention in that Xin does not disclose the first planarization layer comprises the third portion defining a second groove, and thereby, does not disclose the fourth portion adjacent the third portion, or the second conductive layer comprises the third conductive pattern in the second groove and the fourth conductive pattern extends from the third conductive pattern.
However, Wang clearly teaches, in Figure 15A, second conductive layer 250/DATA comprising a third conductive pattern in the second groove 271 of the first planarization layer 270 and a fourth conductive pattern, on the surface of the first planarization layer 270 outside groove 271, which extends from the third conducive pattern, wherein the fourth conductive pattern is physically continuous with the third conductive pattern and extends across an edge of the second groove to reach the fourth portion, paragraph 160.
That is, Wang teaches a data line, in view of which it would have been obvious to modify the data line 212/21/DATA of Xin to place a portion of the data line in a second groove, thereby resulting in the invention as claimed.
Applicant argued neither Xin nor Wang provide a motivation to make such a modification.
However, one would have been motivated to do so in order to address considerations with respect to overlying conductive patterns, as is explicitly suggested by Wang. Wang teaches recessing the data line in regions in which a conductive pattern above the data line overlaps, paragraph 160, and further discloses this allows for the inclusion of components within a limited wiring space, paragraph 122, and improves the flatness of an overlying anode which improves visual qualities of the display, paragraph 162. Even though the data line of Xin is provided on a protruding portion of the planarization layer, the benefit of recessing the data line as taught by Wang is applicable.
For at least theses reasons, the combination of references is still proper and renders the invention as claimed obvious.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Xin et al. (CN 113345923 A) in view of Wang (US 2024/0155899).
In reference to claim 1, Xin et al. (CN 113345923), hereafter “Xin,” for which Xin et al. (US 2021/0384226) is used as an English language equivalent and cited herein, discloses a display apparatus comprising:
an insulating layer, 13 in Figure 26, comprising a first portion CA2 defining a first groove 131 and a second portion PA3 which is adjacent to the first portion, paragraphs 99-101; and
in order from the insulating layer:
a first conductive layer 22 comprising a first conductive pattern in the first groove of the insulating layer and a second conductive pattern which is on the second portion of the insulating layer, paragraph 102;
a first planarization layer 12, comprising a fourth portion which overlaps the first groove of the insulating layer, paragraph 52; and
a second conductive layer 21 on the first planarization layer, paragraph 43,
wherein the second conductive layer comprises a fourth conductive pattern 212 disposed on the fourth portion of the first planarization layer, thereby overlapping the first groove 131 of the insulating layer,
wherein the fourth conductive pattern extends to reach a position directly above the first groove of the insulating layer, paragraph 102.
Xin does not disclose the first planarization layer comprises a third portion defining a second groove and the fourth portion which is adjacent to the third portion,
the second conductive layer comprises a third conductive pattern in the second groove of the first planarization layer,
the fourth conductive pattern which extends from the third conducive pattern, or
the fourth conductive pattern is physically continuous with the third conductive pattern and extends across an edge of the second groove to reach a position directly above the first groove of the insulating layer.
Wang (US 2024/0155899), hereafter “Wang 2024,” discloses a display device including teaching
a first planarization layer, 270 in Figure15A, comprising a third portion defining a second groove 271 and a fourth portion which is adjacent to the third portion,
the second conductive layer 250/DATA comprising a third conductive pattern in the second groove 271 of the first planarization layer and a fourth conductive pattern which extends from the third conducive pattern,
wherein the fourth conductive pattern is physically continuous with the third conductive pattern and extends across an edge of the second groove to reach the fourth portion, paragraph 160.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the data line 212/DATA of Xin such that the first planarization layer comprises a third portion defining a second groove and a fourth portion which is adjacent to the third portion,
the second conductive layer comprises a third conductive pattern in the second groove of the first planarization layer, and
a fourth conductive pattern which extends from the third conducive pattern to be disposed on the fourth portion of the first planarization layer,
wherein the fourth conductive pattern is physically continuous with the third conductive pattern and extends across an edge of the second groove to reach a position directly above the first groove of the insulating layer.
One would have been motivated to do so in order to form a light emitting layer over a surface with improved flatness, paragraph 162.
In reference to claim 2, Xin discloses at the first groove of the insulating layer, the first conductive pattern of the first conductive layer, 22 at CA2, faces the fourth conductive pattern of the second conductive layer, 212 of 21, with the first planarization layer 12 therebetween, Figure 26.
In reference to claim 3, Xin discloses the first conductive pattern of the first conductive layer, 22 at CA2, and the second conductive pattern of the first conductive layer, 22 at PA3 are integral with each other, Figure 26 and paragraph 102.
In reference to claim 4, Wang 2024 discloses the third conductive pattern of the second conductive layer, 250/DATA in 271 in Figure 15A, and the fourth conductive pattern of the second conductive layer, 250/DATA outside 271. are integral with each other, Figure 15A.
In reference to claim 5, Xin discloses each of the first conductive pattern of the first conductive layer, the second conductive pattern of the first conductive layer and the first planarization layer has an upper surface, and a distance from the upper surface of the first conductive pattern of the first conductive layer to the upper surface of the first planarization layer, is greater than a distance from the upper surface of the second conductive pattern of the first conductive layer to the upper surface of the first planarization layer, Figure 26.
In reference to claim 6, Xin does not disclose, in order from the insulating layer: the second conductive layer; a second planarization layer; and a third conductive layer.
Wang (US 2024/0155899), hereafter “Wang 2024” discloses a display device including teaching, in order from the insulating layer: the second conductive layer 250; a second planarization layer 280 (unlabeled in Figure 15A); and a third conductive layer 310, Figure 15A.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the display device to comprise in order from the insulating layer: the second conductive layer; a second planarization layer; and a third conductive layer. One would have been motivated to do so in order to form a light emitting layer over a surface with improved flatness, paragraphs 162.
In reference to claim 7, Wang 2024 discloses at the second groove, 271 in Figure 15A, of the first planarization layer 270, the third conductive pattern of the second conductive layer, 250/DATA in 271, faces the third conductive layer 310 with the second planarization layer 280 therebetween.
In reference to claim 8, Wang 2024 discloses each of the third conductive pattern of the second conductive layer, the fourth conductive pattern of the second conductive layer and the second planarization layer has an upper surface, and a distance from the upper surface of the third conductive pattern of the second conductive layer to the upper surface of the second planarization layer, is greater than a distance from the upper surface of the fourth conductive pattern of the second conductive layer to the upper surface of the second planarization layer, paragraph 97, see also Figure 2B.
In reference to claim 9, Xin discloses the first groove located where the data line 212 and the power line 221 overlap, Figures 15 and 26, and Wang 2024 teaches the second groove located where the data line 250/DATA and the anode/pixel electrode 310/31 overlap, Figure 15A, and Wang 2024 further teaches a pixel layout where the location where the data line and power line overlap is spaced from the location where the data line and the anode/pixel electrode overlap, see annotated Figure 3 below.
It results naturally from the combination of the Xin and Wang 2024 that the first groove and the second groove are spaced apart from each other in a direction along the second conductive layer.
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[AltContent: textbox (Overlap of data line DATA and power line Vdd2 (first groove)
spaced from
overlap of data line and anode 31 (second groove)
in a direction M1 along the second conductive layer. )][AltContent: oval][AltContent: oval][AltContent: arrow][AltContent: arrow][AltContent: oval][AltContent: oval][AltContent: arrow][AltContent: arrow]
In reference to claim 15, Xin discloses the first conductive layer 22 extends in a first direction (horizontal direction in Figure 26), the second conductive layer 21 extends in a second direction (in and out of the page) crossing the first direction, and at the first groove CA2 of the insulating layer, the first conductive layer which extends in the first direction faces the second conductive layer which extends in the second direction, with the first planarization layer 12 therebetween.
Claims 10-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xin et al. (CN 113345923 A) in view of Wang (US 2024/0155899) as applied to claim 1 above and further in view of Wang et al. (US 2020/0083309).
In reference to claim 10, Xin does not disclose a first transistor comprising a first semiconductor layer and a first electrode which overlaps the first semiconductor layer; and a capacitor comprising the first electrode and a second electrode which overlaps the first electrode.
Wang et al. (US 2020/0083309), hereafter “Wang 2020,” discloses a display device including teaching a first transistor T1, comprising a first semiconductor layer, A1 in Figure 12, and a first electrode G1(Cst1) which overlaps the first semiconductor layer, paragraph 150; and a capacitor comprising the first electrode G1 (Cst1) and a second electrode Cst2 which overlaps the first electrode, paragraph 123.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the display to further comprise a first transistor comprising a first semiconductor layer and a first electrode which overlaps the first semiconductor layer; and a capacitor comprising the first electrode and a second electrode which overlaps the first electrode.
To do so would have merely been to apply a known technique to improve similar devices in the same way, KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. C. In this case, applying the wiring and wire spacing technique taught in the display of Xin to the display of Wang 2020.
In reference to claim 11, Xin teaches power line 21/211/PVDD, on the same layer as the data line 21/212/DATA, on the planarization layer 12, and power line 221/22 on the insulating layer 13, as addressed above, and Figure 26.
Wang 2020 includes the data line 171 (not pictured) on planarization layer 17, paragraph 172, and power line ELVDD 161 in Figures 7 and 12 on insulating layer 16.
Wang 2020 further teaches the second electrode of the capacitor, Cst2 in Figure 12, faces the first planarization layer 17 with the insulating layer 16 therebetween. It results naturally from the combination of Xin and Wang 2020 that the second electrode of the capacitor, Cst2 in Figure 12, faces the first planarization layer 17 with the insulating layer 16 therebetween.
In reference to claim 12, Wang 2020 discloses a second transistor T4 spaced apart from the first transistor in a direction along the insulating layer, and comprising: a second semiconductor layer, A4 in Figure 12, in a different layer than the first semiconductor layer A1 of the first transistor, and a third electrode G4 which overlaps the second semiconductor layer and is in a different layer than the second electrode of the capacitor Cst2, paragraphs 160 and 163.
In reference to claim 13, Xin teaches power line 21/211/PVDD, on the same layer as the data line 21/212/DATA, on the planarization layer 12, and power line 221/22 on the insulating layer 13, as addressed above, and Figure 26.
Wang 2020 includes the data line 171 (not pictured) on planarization layer 17, paragraph 172, and power line ELVDD 161 in Figures 7 and 12 on insulating layer 16.
Wang 2020 further teaches the third electrode G4 of the second transistor faces the first planarization layer 17 with the insulating layer 16 therebetween.
In reference to claim 14, Wang 2020 discloses the first semiconductor layer A1 (poly-silicon) of the first transistor and the second semiconductor layer A3 (oxide semiconductor) of the second transistor comprise different materials from each other, paragraphs 144, 150, and 162.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tanaka et al. (WO 2020/065962) and Adachi (WO 2009116177 A1) disclose related wiring structures.
All claims are identical to or patentably indistinct from, or have unity of invention with claims in the application prior to the entry of the submission under 37 CFR 1.114 (that is, restriction (including a lack of unity of invention) would not be proper) and all claims could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the application prior to entry under 37 CFR 1.114. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action after the filing of a request for continued examination and the submission under 37 CFR 1.114. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/Primary Examiner, Art Unit 2897
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