Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1-20 remain present in this application. Claims 1 and 13 have been amended.
Response to Arguments
Applicant's arguments filed 08/21/2025 have been fully considered but they are not persuasive. Applicant argues that Lin fails to teach “forming a plurality of conductive features within the passivation layer,” and has amended claims 1 and 13 to include the limitation. However, the examiner considers the passivation layer 120 of Lin to have a plurality of conductive features 140 (Lin Fig. 6). The conductive feature 140 is described as a contact feature made of material having good electrical conductivity such as tungsten (Lin Col. 4 Line 40). Furthermore, the contact structure is disclosed to be electrically connected a plurality of second transistors 110, which means that there are also a plurality of these conductive structures present within the passivation layer 120 (Lin Col. 2 Line 52, “104 peripheral region also includes a 110 plurality of second transistors”).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-6, and 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 10249357 B1), hereinafter referred to as Lin, and in further view of Jeong et al. (US 6465351 B1), hereinafter referred to as Jeong.
Regarding the independent claim 1:
A method for manufacturing a semiconductor device, comprising: providing a substrate comprising an array region and a peripheral region (Lin Fig. 1, with array region (102) and peripheral region (104)),
wherein an island structure is only formed on the array region and protrudes from the substrate (Lin Fig. 1, island structure comprising 105, protruding from substrate on the array region 102),
and the island structure comprises a plurality of pillar structures and each of the plurality of pillar structures includes a field effect vertical transistor and at least one capacitor (Lin Fig. 1 Island structure (105) with plurality of pillar structures including transistors (106) and capacitors (108), where the transistors are described to have gate structures that are features that are known to be part of field effect transistors (Lin Col. 1 Line 47 ))
wherein a top surface of the island structure disposed over the array region is higher than a top surface of the substrate in the peripheral region (Lin Fig. 1, depicts the top surface of Island structure 105 is higher than top surface of substrate in the peripheral region)
the top surface of the island structure disposed over the array region and the top surface of the substrate in the peripheral region define a stepped structure with a first height difference (H1) (Lin Fig. 1, Height difference between array region 102 and peripheral region 104 define a stepped structure.);
performing a deposition process to form a passivation layer over the peripheral region with a first thickness (T1) and over the array region with a second thickness (T2) (Lin Fig. 3, where it is apparent that the deposited passivation layer has a first thickness (T1 in the figure) in the peripheral region and a second thickness in the array region comprising of dielectric layer 120 and stop layer 130. The examiner notes that the usage of the claimed variable “T2” strictly refers to the thickness of the passivation layer over the array region and is not to be confused by the “T2” as used by Lin, which refers to the height of the island structure (105) + the thickness of the stop layer 130.);
performing a chemical mechanical polishing process to remove a portion of the passivation layer so that the passivation layer has a third thickness (T3) over the array region (Lin Fig. 4, planarization process P2, wherein planarization process is stopped upon exposure of stop layer 130, which gives the passivation layer a third thickness T3 over the array region equal to the thickness of stop layer 130.),
wherein the H1, the T1, the T2, and the T3 satisfy an inequality (1):(T1-H1- T3) x3<T2-T3<(T1-H1- T3) x7 (Lin Col 3 Line 38 “dielectric layer 120 usually has a great thickness (typically exceeding 1.5 micrometers) in order to make the dielectric layer completely cover the capacitor the thickness of the dielectric layer should be larger than the thickness of the capacitor… For example, the dielectric layer in this embodiment has a thickness of about 1.9 micrometers, but is not limited thereto”). In this case, it can be shown that if T1 = 1900 nm, and T2 = 2050 nm, T3 = 200 nm and where a reasonable estimate for H1 could be 1200 nm (height less than T1 according to Lin), would satisfy the inequality (T1-H1- T3) x3<T2-T3<(T1-H1- T3) x7. Furthermore, the examiner considers the limitations regarding the variation of dimensional parameters without specificity, to lack the inventive step required for patentability as the determination of dimensional parameters that will satisfy the claimed inequality can be done via routine optimization and experimentation. The examiner also notes that the dimensions for T2 in this case comes from the assumption that the passivation layer of Lin is reasonably conformal. With this assumption, T2 is then equivalent to the sum of T1 and the thickness of the stop layer 130 which is equal to T3 (Lin Fig. 3); and
forming a plurality of conductive features within the passivation layer (Lin Fig. 6, Col. 4 Line 40, conductive features 140 connected to a plurality of second transistors which is interpreted by the examiner that there must also be a plurality of these conductive features within the passivation layer 120.).
Even though Lin fails to disclose a specific value for the thickness for the stop layer, Jeong, in a similar field of endeavor, discloses a method of planarizing DRAM passivation layers wherein the stop layer is disclosed to be in the range of 1 to 200 nm (Jeong Col. 8 Line 41, “The CMP stopper 216 is preferably formed on the sacrificial oxide layer 214 to a thickness of about 10 Å to 2,000 Å.”). Taking 200 nm as an exemplary thickness for the stop layer yields T2 = 1900 nm + 200 nm = 2100 nm.
Therefore, it would have been obvious to a person having ordinary skill in the art would, prior to the effective filing date of the claimed invention, that a process for planarizing DRAM dielectric layers would have dimensional quantities for H1, T1, T2, and T3, that would satisfy the inequality (T1-H1- T3) x3<T2-T3<(T1-H1- T3) x7, since these are typical dimensions of passivation layers in DRAM devices that are known in the art as taught by the combined disclosure of Lin and Jeong.
Regarding Claim 2: The combined disclosure of Lin and Jeong teaches the method of claim 1.
Lin further teaches the method wherein the T1 ranges from 2000 nm to 2800 nm (Lin Col. 3 “It is noteworthy that the dielectric layer usually has a great thickness (typically exceeding 1.5 micrometers), in order to make the dielectric layer completely cover the capacitor, the thickness of the dielectric layer should be larger than the thickness of the capacitor”). Where the disclosure of Lin is interpreted by the examiner to include the range 2000 nm to 2800 nm as the thickness is disclosed to typically exceed 1500 nm and is dependent on the height of the capacitors in the array region. Therefore, the thickness of the dielectric layer T1 could be varied according to the height of the capacitors via known methods in the art.
For example, Jeong depicts in figure 3B capacitor electrodes 224c, that are the same height with sacrificial oxide layer 214. The sacrificial oxide layer 214 is disclosed to have a thickness of 500 nm to 2000 nm (Jeong Col. 8 Line 26 “the sacrificial oxide layer 214 is preferably formed to a thickness of about 5,000 Å to 20,000 Å”). The examiner interprets this as an indication that the capacitors is known in the art to vary between 500 nm and 2000 nm. Applying the disclosure of Lin that teaches that the dielectric layer must completely cover the capacitor, a person having ordinary skill in the art would have then understood that the dielectric layer could be at least more than 2000 nm in order to cover the capacitor completely in this particular case; which affirms the variability of the thickness of the passivation layer as known in the art.
Regarding Claim 3: The combined disclosure of Lin and Jeong teaches the method of claim 1.
Lin fails to teach the method wherein the T3 ranges from 200 nm to 300 nm.
Lin, however, teaches that the planarization process terminates upon exposure of the stop layer (Lin Fig. 4, Col. 4 Line 49, Stop layer 130, “As shown in FIG. 4 the mask layer 130 in the memory 102 region is used as a stop layer 130, a planarization process P2 is performed to remove the dielectric layer 120… until the top surface of mask layer within the memory region is exposed.”). Therefore, T3 is equal to the thickness of the stop layer. Lin fails to specify a thickness for the stop layer.
However, in a similar field of endeavor, Jeong discloses a method of planarizing DRAM passivation layers wherein a stop layer is disclosed to be in the range of 1 nm to 200 nm (Jeong Col. 8 Line 41, “The CMP stopper 216 is preferably formed on the sacrificial oxide layer 214 to a thickness of about 10 Å to 2,000 Å.”). Similar to Lin, Jeon also discloses that the stop layer serves as an endpoint for the CMP process (Jeong Col. 3 Line 1 “A CMP process is then carried out using the CMP stopping layer as an end point”)
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teaching of Jeong to the disclosure of Lin in order to set the thickness of a stop layer to 200 nm and have the CMP process stop upon the exposure of the stop layer and therefore leave a passivation layer that has a thickness T3 equal to 200 nm or greater. This is an obvious and expected result as the use of stop layers in a CMP process is known in the art as taught by Lin and Jeong and that the remaining dielectric layer could always be varied accordingly.
Regarding Claim 4: The combined disclosure of Lin and Jeong teaches the method of claim 1.
Lin teaches the method wherein the H1 ranges from 1200 nm to 2000 nm (Lin Col 3 Line 38 “dielectric layer 120 usually has a great thickness (typically exceeding 1.5 micrometers) in order to make the dielectric layer completely cover the capacitor the thickness of the dielectric layer should be larger than the thickness of the capacitor.). The examiner interprets the thickness of the capacitor to be H1 since the capacitor structure is what gives height to the island structure. According to the disclosure of Lin, since the dielectric layer 120 has to completely cover the capacitor thickness, it is reasonable to assume that H1 typically can be around the range of 1500 nm but can also exceed that depending on device characteristics. Lin for example deposits a dielectric layer of 1900 nm which means that H1 could also be around that thickness range (Lin Col 3 Line 43, “For example, the dielectric layer in this embodiment has a thickness of about 1.9 micrometers, but is not limited thereto”).
Furthermore, Jeong depicts in figure 3B capacitor electrodes 224c, that are the same height with sacrificial oxide layer 214. The sacrificial oxide layer 214 is disclosed to have a thickness of 500 nm to 2000 nm (Jeong Col. 8 Line 26 “the sacrificial oxide layer 214 is preferably formed to a thickness of about 5,000 Å to 20,000 Å”). The examiner interprets this as an indication that H1 is known in the art to vary between 500 nm and 2000 nm.
Regarding Claim 5: The combined disclosure of Lin and Jeong teaches the method of claim 1.
Lin further teaches the method wherein the T2 is greater than the T1 (Lin Fig. 3, where the examiner T1 as the height of the passivation layer over the peripheral area comprising a dielectric layer 102, and T2 is the height of the passivation layer comprising a dielectric layer 102 + the stopper layer 130. Note that “T2” refers to the applicant’s usage where T2 is a variable representing the total thickness of the passivation layer over the array region as opposed to the “T2” of Lin which refers to the top surface of the mask layer.). Assuming that the passivation layer is conformal, T2 must be greater than T1, since T2 includes an additional stopper layer deposited on top of the island structure.
Regarding Claim 6: The combined disclosure of Lin and Jeong teaches the method of claim 6.
Lin fails to teach the method wherein a difference between the T2 and the T1 ranges from 100 nm to 300 nm.
However, Lin teaches the method wherein a difference between the T2 and the T1 is equivalent to the thickness of the stopping layer 130 (Lin fig. 3). This is because the passivation layer at the peripheral region 104 comprises the dielectric layer 120, while the passivation layer over the array region 102, comprises the dielectric layer 120 and the stop layer 130.
Even though Lin fails to disclose a specific value for the thickness for the stop layer, Jeong, in a similar field of endeavor discloses a method of planarizing DRAM passivation layers wherein the stop layer is disclosed to be in the range of 1 to 200 nm (Jeong Col. 8 Line 41, “The CMP stopper 216 is preferably formed on the sacrificial oxide layer 214 to a thickness of about 10 Å to 2,000 Å.”).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply this teachings of Jeong to the disclosure of Lin, in order to have a stopping layer of 200nm, and have a difference between T1 and T2 be equal to 200 nm. This is obvious as stopping layers are widely used in the art as endpoint mechanisms as taught by Lin and Jeong with thickness values that could be varied accordingly using known methods in the art (Jeong Col 8 Line 40).
Regarding the independent Claim 13:
Lin teaches a method for manufacturing a semiconductor device, comprising:
providing a substrate comprising an array region and a peripheral region (Lin Fig. 1, with array region (102) and peripheral region (104)),
wherein the array region and the peripheral region define a stepped structure (Lin Fig. 1, Height difference between array region 102 and peripheral region 104 define a stepped structure.);
performing a deposition process to form a passivation layer over the array region and the peripheral region (Lin Fig. 3, with passivation layer 120.),
wherein the passivation layer has a first thickness (T1) over the peripheral region (Lin Fig. 3, with passivation layer 120 with thickness T1.),
and the T1 ranges from 2000 nm to 2800 nm (Lin Col 3 Line 38 “dielectric layer 120 usually has a great thickness (typically exceeding 1.5 micrometers) in order to make the dielectric layer completely cover the capacitor the thickness of the dielectric layer should be larger than the thickness of the capacitor… For example, the dielectric layer in this embodiment has a thickness of about 1.9 micrometers, but is not limited thereto”. Another example by Jeong also discloses capacitors to have a range of heights between 500 nm and 2000 nm (Jeong Col. 8 Line 26 “the sacrificial oxide layer 214 is preferably formed to a thickness of about 5,000 Å to 20,000 Å”). See rejection of Claim 2.);
performing a chemical mechanical polishing process so that the passivation layer has a substantially continuous surface over the array region and the peripheral region (Lin Fig. 4, planarization process P2, wherein planarization process results in substantially planar surface.)
and forming a plurality of conductive features within the passivation layer (Lin Fig. 6, Col. 4 Line 40, conductive features 140 connected to a plurality of second transistors, which is interpreted by the examiner that there must also be a plurality of these conductive features within the passivation layer 120.).
Regarding Claim 14: The combined disclosure of Lin and Jeong teach the method of claim 13.
Lin further teaches the method wherein the stepped structure has a first height difference (H1) (Lin Fig. 1, Height difference between array region 102 and peripheral region 104 define a first height difference H1.),
the deposition process forms the passivation layer over the array region with a second thickness (T2) (Lin Fig. 4, where the passivation over the array region 102, has a thickness that includes stop layer 130 and dielectric layer 120),
and the continuous surface over the array region has a third thickness (T3) over the array region (Lin Fig. 4, planarization process P2, wherein planarization process is stopped upon exposure of stop layer 130, which gives the passivation layer a third thickness T3 over the array region equal to the thickness of stop layer 130.),
and wherein the H1, the T1, the T2, and the T3 satisfy an inequality (1):(T1-H1- T3) x3<T2-T3<(T1-H1- T3) x7 (Lin Col 3 Line 38 “dielectric layer 120 usually has a great thickness (typically exceeding 1.5 micrometers) in order to make the dielectric layer completely cover the capacitor the thickness of the dielectric layer should be larger than the thickness of the capacitor… For example, the dielectric layer in this embodiment has a thickness of about 1.9 micrometers, but is not limited thereto”).
In this case, it can be shown that if T1 = 1900 nm, and T2 = 2050 nm, T3 = 200 nm and where a reasonable estimate for H1 could be 1200 nm (height less than T1 according to Lin), would satisfy the inequality (T1-H1- T3) x3<T2-T3<(T1-H1- T3) x7. Furthermore, the examiner considers the limitations regarding the variation of dimensional parameters without specificity, to lack the inventive step required for patentability as the determination dimensional parameters that will satisfy the claimed inequality can be done via routine optimization and experimentation.
The examiner also notes that the dimensions for T2 in this case comes from the assumption that the passivation layer of Lin is reasonably conformal. With this assumption, T2 is then equivalent to the sum of T1 and the thickness of the stop layer 130 which is equal to T3 (Lin Fig. 3).
Even though Lin fails to disclose a specific value for the thickness for the stop layer, Jeong, in a similar field of endeavor discloses a method of planarizing DRAM passivation layers wherein the stop layer is disclosed to be in the range of 1 to 200 nm (Jeong Col. 8 Line 41, “The CMP stopper 216 is preferably formed on the sacrificial oxide layer 214 to a thickness of about 10 Å to 2,000 Å.”). Taking 200 nm as an exemplary thickness for the stop layer yields T2 = 1900 nm + 200 nm = 2100 nm. Therefore, it would have been obvious to a person having ordinary skill in the art would, prior to the effective filing date of the claimed invention, that a process for planarizing DRAM dielectric layers would have dimensional quantities for H1, T1, T2, and T3, that would satisfy the inequality (T1-H1- T3) x3<T2-T3<(T1-H1- T3) x7, since these are typical dimensions of passivation layers in DRAM devices that are known in the art as taught by the combined disclosure of Lin and Jeong.
Regarding claim 15: The combined disclosure of Lin and Jeong teach the method of claim 14.
Lin fails to teach the method wherein the T3 ranges from 200 nm to 300 nm.
Lin, however, teaches that the planarization process terminates upon exposure of the stop layer (Lin Fig. 4, Col. 4 Line 49, Stop layer 130, “As shown in FIG. 4 the mask layer 130 in the memory 102 region is used as a stop layer 130, a planarization process P2 is performed to remove the dielectric layer 120… until the top surface of mask layer within the memory region is exposed.”). Therefore, T3 is equal to the thickness of the stop layer. Lin fails to specify a thickness for the stop layer.
However, in a similar field of endeavor, Jeong discloses a method of planarizing DRAM passivation layers wherein a stop layer is disclosed to be in the range of 1 nm to 200 nm (Jeong Col. 8 Line 41, “The CMP stopper 216 is preferably formed on the sacrificial oxide layer 214 to a thickness of about 10 Å to 2,000 Å.”). Similar to Lin, Jeon also discloses that the stop layer serves as an endpoint for the CMP process (Jeong Col. 3 Line 1 “A CMP process is then carried out using the CMP stopping layer as an end point”)
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teaching of Jeong to the disclosure of Lin in order to set the thickness of a stop layer to 200 nm and have the CMP process stop upon the exposure of the stop layer and therefore leave a passivation layer that has a thickness T3 equal to 200 nm or greater. This is an obvious and expected result as the use of stop layers in a CMP process is known in the art as taught by Lin and Jeong and that the remaining dielectric layer could always be varied accordingly.
Regarding Claim 16: The combined disclosure of Lin and Jeong teach the method of claim 14.
Lin teaches the method wherein the H1 ranges from 1200 nm to 2000 nm (Lin Col 3 Line 38 “dielectric layer 120 usually has a great thickness (typically exceeding 1.5 micrometers) in order to make the dielectric layer completely cover the capacitor the thickness of the dielectric layer should be larger than the thickness of the capacitor.). The examiner interprets the thickness of the capacitor to be H1 since the capacitor structure is what gives height to the island structure. According to the disclosure of Lin, since the dielectric layer 120 has to completely cover the capacitor thickness, it is reasonable to assume that H1 typically can be around the range of 1500 nm but can also exceed that depending on device characteristics. Lin for example deposits a dielectric layer of 1900 nm which means that H1 could also be around that thickness range (Lin Col 3 Line 43, “For example, the dielectric layer in this embodiment has a thickness of about 1.9 micrometers, but is not limited thereto”).
Furthermore, Jeong depicts in figure 3B capacitor electrodes 224c, that are the same height with sacrificial oxide layer 214. The sacrificial oxide layer 214 is disclosed to have a thickness of 500 nm to 2000 nm (Jeong Col. 8 Line 26 “the sacrificial oxide layer 214 is preferably formed to a thickness of about 5,000 Å to 20,000 Å”). The examiner interprets this as an indication that H1 is known in the art to vary between 500 nm and 2000 nm.
Regarding claim 17: The combined disclosure of Lin and Jeong teach the method of claim 14.
Lin further teaches the method wherein the T2 is greater than the T1 (Lin Fig. 3, where the examiner T1 as the height of the passivation layer over the peripheral area comprising a dielectric layer 102, and T2 is the height of the passivation layer comprising a dielectric layer 102 + the stopper layer 130. Note that “T2” refers to the applicant’s usage where T2 is a variable representing the total thickness of the passivation layer over the array region as opposed to the “T2” of Lin which refers to the top surface of the mask layer.). Assuming that the passivation layer is conformal, T2 must be greater than T1, since T2 includes an additional stopper layer deposited on top of the island structure.
Claims 7-12, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Jeong, and in further view of Qin et al. (CN 114005845 A), hereinafter referred to as Qin.
Regarding Claim 7: The combined disclosure of Lin and Jeong teaches the method of claim 1.
Lin fails to teach the method further comprising: performing an etching process to form a recess defined by the passivation layer over the array region before performing the chemical mechanical polishing process.
[AltContent: textbox (Exhibit 1: Qin showing etching passivation layer over region A to form recess as shown in Fig. 3d.)]
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However, in a related field of endeavor, Qin teaches a method further comprising: performing an etching process to form a recess defined by the passivation layer over the array region before performing the chemical mechanical polishing process (Qin Fig. 3c and 3d, [0057]).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Qin to the combined disclosure of Lin and Jeong, in order to include an etching process prior to the planarization of the passivation layer, with the obvious result of obtaining a more uniform passivation layer after the planarization process (Qin [0059]).
Regarding Claim 8: The combined disclosure of Lin, Jeong, and Qin teaches the method of claim 7.
Lin fails to teach the method wherein the passivation layer over the peripheral region is free from being removed by the etching process.
However, in a related field of endeavor, Qin teaches a method wherein the passivation layer over the peripheral region is free from being removed by the etching process (Qin Fig. 3c and 3d, [0057]), where the photomask ensures that the passivation layer over peripheral region B is free from being removed by the etching process).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Qin to the combined disclosure of Lin and Jeong, in order to include an etching process that protects the passivation layer over the peripheral region, with the obvious result of minimizing the height difference of the passivation layers between the array region A, and peripheral region B. This is obvious to try as this results in a more uniform passivation layer after the planarization process (Qin [0059]).
Regarding Claim 9: The combined disclosure of Lin, Jeong, and Qin teaches the method of claim 7.
Lin fails to teach the method wherein the recess is free from vertically overlapping the peripheral region.
However, in a related field of endeavor, Qin teaches a method wherein the recess is free from vertically overlapping the peripheral region. (Qin Fig. 3c and 3d, [0057]), where the resulting recess in Fig. 3d is free from vertically overlapping the peripheral region B.).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Qin to the combined disclosure of Lin and Jeong, in order to include an etching process that creates a recess that is free from vertically overlapping the peripheral region B, with the obvious result of minimizing the height difference of the passivation layers between the array region A, and peripheral region B. This is obvious to try as this results in a more uniform passivation layer after the planarization process (Qin [0059]).
Regarding Claim 11: The combined disclosure of Lin, Jeong, and Qin teaches the method of claim 7.
Lin fails to teach the method wherein the recess defines a second height difference (H2) of the passivation layer over the array region, wherein the H2, the T2, and the T3 satisfy an inequality (2):(T2 -H2-T3)x1<H2<(T2-H2-T3)x2.
However, in a related field of endeavor, Qin teaches a method wherein the recess defines a second height difference (H2) of the passivation layer over the array region, wherein the H2, the T2, and the T3 satisfy an inequality (2):(T2 -H2-T3)x1<H2<(T2-H2-T3)x2. (Qin Fig. 3c and 3d, where the second height difference is apparent in Fig. 3d). Qin provides a range of equivalent dimensions relating to H2 (Qin 4 [0058], Fig. 3d), T2 (Qin {| [0018], Fig. 3c), and T3 (Qin 4] [0064], Fig. 3e), where T3, though not explicitly defined, is taken to have dimensions that is proportional to that of the claimed invention while still being consistent with the disclosure of Qin. In this case, the inequality is satisfied if we take T2 to be 11,150 nm, H2, to be 200 nm, and T3 to be 10,653 nm.
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Qin to the combined disclosure of Lin and Jeong, in order to include an etching process that creates a recess with a depth H2 over the array region where H2 satisfies the inequality (2):(T2 -H2-T3)x1<H2<(T2-H2-T3)x2. Applying this to the equivalent features of Lin, a person having ordinary skill in the art would also recognize that this inequality could be satisfied with dimensions consistent with the method of Lin, such as H2 = 2000 nm , T2 =2100, and T3 = 200 nm. The variation of the specific thickness of the passivation layer can be done using known methods in the art, and obtaining the proper dimensional parameters in order to satisfy the inequality can be done via routine experimentation and optimization. This is obvious to try as reducing the height difference of the passivation layers between the array and peripheral region results [AltContent: textbox (Exhibit 2: Qin Fig. 3d showing recess depth H2 indicated by double array over the array region A.)]
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in a more uniform passivation layer after the planarization process (Qin [0059])
Regarding Claim 12: The combined disclosure of Lin, Jeong, and Qin teaches the method of claim 11,
Lin fails to teach wherein the H2 ranges from 800 nm to 1400 nm.
However, in a related field of endeavor, Qin teaches a method wherein the H2 ranges from 800 nm to 1400 nm. (Qin [0019], [0058]). Qin mentions in ¶[0019] that the passivation layer can be greater than 10 um, and in ¶[0058] that the thickness of the passivation layer located in the array region A, is greater than 150 nm. It is therefore conceivable given these ranges that a recess with a depth H2 between 800 nm and 1400 nm can be achieved using the disclosure of Qin. In this case, the inequality is satisfied if we take T2 = 11,150 nm, H2 = 1200 nm, and T3 = 9000 nm. This variation of dimensional parameters are known in the art and can be implemented via known methods. For example, applying this to the disclosure of Lin, the inequality is satisfied when T2 = 2100 nm, T3 = 200 nm, and H2 = 1200 nm.
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Qin to the disclosure of Lin, in order to etch a recess on the passivation layer over the array region, where the recess may have a depth H2 that ranges from 800 nm to 1400 nm. This variation in ranges are known variations in the art and is dependent on the specification on the device made and are implementable using known methods. This is obvious to try as reducing the height difference of the passivation layers between the array and peripheral region results in a more uniform passivation layer after the planarization process (Qin [0059]).
Regarding claim 18: The combined disclosure of Lin and Jeong teaches the method of claim 13.
Lin fails to teach the method further comprising: performing an etching process to form a recess defined by the passivation layer over the array region before performing the chemical mechanical polishing process.
However, in a related field of endeavor, Qin teaches a method further comprising: performing an etching process to form a recess defined by the passivation layer over the array region before performing the chemical mechanical polishing process (Qin Fig. 3c and 3d, [0057]).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Qin to the combined disclosure of Lin and Jeong, in order to include an etching process prior to the planarization of the passivation layer, with the obvious result of obtaining a more uniform passivation layer after the planarization process (Qin [0059]).
Regarding claim 19: The combined disclosure of Lin, Jeong, and Qin teaches the method of claim 18.
Lin fails to teach the method wherein the passivation layer over the peripheral region is free from being removed by the etching process.
However, in a related field of endeavor, Qin teaches a method wherein the passivation layer over the peripheral region is free from being removed by the etching process (Qin Fig. 3c and 3d, [0057]), where the photomask ensures that the passivation layer over peripheral region B is free from being removed by the etching process).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Qin to the combined disclosure of Lin and Jeong, in order to include an etching process that protects the passivation layer over the peripheral region, with the obvious result of minimizing the height difference of the passivation layers between the array region A, and peripheral region B. This is obvious to try as this results in a more uniform passivation layer after the planarization process (Qin [0059]).
Regarding claim 20: The combined disclosure of Lin, Jeong, and Qin teaches the method of claim 18.
Lin fails to teach the method wherein the recess defines a second height difference (H2) of the passivation layer over the array region, wherein the H2, the T2, and the T3 satisfy an inequality (2):(T2 -H2-T3)x1<H2<(T2-H2-T3)x2.
However, in a related field of endeavor, Qin teaches a method wherein the recess defines a second height difference (H2) of the passivation layer over the array region, wherein the H2, the T2, and the T3 satisfy an inequality (2):(T2 -H2-T3)x1<H2<(T2-H2-T3)x2. (Qin Fig. 3c and 3d, where the second height difference is apparent in Fig. 3d). Qin provides a range of equivalent dimensions relating to H2 (Qin 4 [0058], Fig. 3d), T2 (Qin {| [0018], Fig. 3c), and T3 (Qin 4] [0064], Fig. 3e), where T3, though not explicitly defined, is taken to have dimensions that is proportional to that of the claimed invention while still being consistent with the disclosure of Qin. In this case, the inequality is satisfied if we take T2 to be 11,150 nm, H2, to be 200 nm, and T3 to be 10,653 nm.
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention to apply the teachings of Qin to the combined disclosure of Lin and Jeong, in order to include an etching process that creates a recess with a depth H2 over the array region where H2 satisfies the inequality (2):(T2 -H2-T3)x1<H2<(T2-H2-T3)x2. Applying this to the equivalent features of Lin, a person having ordinary skill in the art would also recognize that this inequality could be satisfied with dimensions consistent with the method of Lin, such as H2 = 2000 nm , T2 =2100, and T3 = 200 nm. The variation of the specific thickness of the passivation layer can be done using known methods in the art, and obtaining the proper dimensional parameters in order to satisfy the inequality can be done via routine experimentation and optimization. This is obvious to try as reducing the height difference of the passivation layers between the array and peripheral region results in a more uniform passivation layer after the planarization process (Qin [0059])
Claims 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, Jeong, and Qin and in further view of Chiang et al. (US 6159786 A A), hereinafter referred to as Chiang.
Regarding Claim 10: The combined disclosure of Lin, Jeong, and Qin teaches the method of claim 7.
Lin fails to teach the method wherein the etching process comprises a dry etching process.
Similarly, the even thought the disclosures of Jeong and Qin include etching steps, they fail to specify that the etching step is a dry etching step.
However, in a related field of endeavor, Chiang teaches a method wherein the etching process comprises a dry etching process (Chiang Col. 3 Line 35 “The silicon nitride film 42 is removed by a wet or dry stripping process”).
Therefore, it would have been obvious to a person having ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply the teachings of Chiang to the disclosures of Lin, Jeong, and Qin, in order understand that the etching process can be done through either wet or dry processes. This is obvious to try as wet and dry etching techniques are known processes in the art with the obvious result of being able to strip away materials (Chiang Col. 3 Line 35).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EMILIO ARDEO/Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899