DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 and 21-30 in the reply filed on 6/4/25 is acknowledged.
Claim Rejections - 35 USC § 112
Claim 10 recites the limitation "the lower interposer" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation "the upper interposer" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim 29 recites the limitation "the second side of the interposer" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 3, 4, 5, 8, and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (US pub 20200312700).
With respect to claim 1, Lu et al. teach a semiconductor structure comprising (see figs. 1-5, particularly fig. 2 and associated text):
an interposer S1 (and all structures below S1) including on-interposer bump structures C11, C12, C13 on a first side (top) of the interposer and a redistribution structure (BL1) on a second side (bottom) of the interposer, wherein the second side is opposite to the first side;
a semiconductor die TD12 bonded to a first subset of the on-interposer bump structures C12 through first solder material portions, wherein the semiconductor die comprises a set of transistors and a set of metal interconnect structures;
a spacer die TD11, TD13 bonded to a second subset of the on-interposer bump structures C11 through second solder material portions, wherein the spacer die is free from any transistor therein (see para 0030);
a molding compound die frame E1 laterally surrounding the semiconductor die and the at least one spacer die; and
a substrate (CL,BL2) on the second side of the interposer, wherein the redistribution structure of the interposer is attached to the substrate.
With respect to claim 2, Lu et al. teach horizontal surface of the molding compound die frame is located within a same horizontal plane as top surfaces of the semiconductor die and the at least one spacer die. See fig. 2 and associated text.
With respect to claim 3, Lu et al. teach all outer sidewalls of the interposer are vertically coincident with sidewalls of the molding compound die frame. See fig. 2 and associated text.
With respect to claim 4, Lu et al. teach an underfill material portion (parts of E1 under dies TD11, TD12, TD13 extending as a single continuous structure around, and laterally surrounding each of, the first solder material portions and the second solder material portions. See fig. 2 and associated text.
With respect to claim 5, Lu et al. teach the spacer die comprises a bulk material portion that continuously extends from a bottom surface of the spacer die to a top surface of the one of the at least one spacer die. See fig. 2 and associated text.
With respect to claim 8, Lu et al. teach the spacer die comprises at least one passive device component selected from a resistor, a capacitor, and an inductor, or comprises an electrostatic discharge (ESD) circuit containing at least one diode (see para 0030). See fig. 2 and associated text.
With respect to claim 9, Lu et al. teach the semiconductor die TD12 comprises a system-on-a-chip (SoC) die and a memory dies; the spacer die TD11 or TD13 comprises a plurality of spacer dies; and the semiconductor die is laterally spaced from at least two outer sidewalls of the molding compound die frame by a respective one of the plurality of spacer dies TD11,TD13 (see para 0030). See fig. 2 and associated text.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US pub 20200312700) in combination with Modi et al. (US pat 12068222).
With respect to claim 6, Lu et al. fail to teach the spacer or dummy die made of polymer.
Modi et al. teach a dummy die made of polymer. See fig. 2 and associated text.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Modi et al. to allow the formation of the dummy die. See fig. 2 and associated text.
Claim(s) 27 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US pub 20200312700).
With respect to claims 27 and 28, Lu et al. fail to teach attaching the interposer to a circuit board.
However, the attachment of an interposer to a circuit board is well-known to one of ordinary skill in the art of making semiconductor devices.
With respect to claim 28, Lu et al. teach a ball grid array on a bottom surface of the interposer.
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US pub 20200312700) in combination with Bhagawat et al. (US pat 11670624).
With respect to claim 29, Lu et al. teach a semiconductor structure comprising (see figs. 1-5, particularly fig. 2 and associated text):
an interposer S1, BL1 including a redistribution structure (BL1);
a plurality of semiconductor dies TD12, TD22 attached to the interposer by a plurality of bump structures C11, C12, C13, C21, C22, C23, wherein the plurality of semiconductor dies comprises a functional die and a memory die adjacent the functional die;
a spacer structure TD11, TD13, TD21,TD23 attached to the interposer by the plurality of bump structures and laterally surrounding the plurality of semiconductor dies, wherein an upper surface of the spacer structure is aligned with an upper surface of the plurality of semiconductor dies; and
a molding material layer E1 on the interposer around the plurality of semiconductor dies and the spacer structure, wherein a sidewall of the molding material layer is aligned with a sidewall of the interposer; and
a substrate CL,BL2 on the second side (bottom) of the interposer, wherein the redistribution structure of the interposer is attached to the substrate.
Lu et al. teach the functional die comprises of a memory device but fail the memory device is high bandwidth memory (HBM) device.
Bhagawat et al. teach integrating high bandwidth memory (HBM) device and semiconductor device over interposer. See col 3, lines 1-25.
It would have been obvious to one of ordinary skill in the art of making semiconductor devices to incorporate the teaching of Bhagawat et al. to achieve increase in device density and device functionality. See col 3, lines 1-25.
With respect to claim 31, Lu et al. in combination with Bhagawat et al. teach the plurality of semiconductor dies comprises a functional die and a high bandwidth memory (HBM) die adjacent the functional die. See the above rejection.
Allowable Subject Matter
Claims 7 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 10 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 11/28/25 have been fully considered but they are not persuasive. See the above rejections.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897