Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/16/2026 has been entered.
Response to Arguments/Amendments
Applicant's amendments to claims 1 and 22 and corresponding arguments, page 9 of the remarks, filed 01/16/2026, with respect to the 35 U.S.C 102(a)(1) rejection of claim 1 as unpatentable over US 2022/0293782 A1; Pan et al.; (hereinafter “Pan”) have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Pan in view of US20130309837A1; Chang et al.; (hereinafter “Chang”). Chang has been introduced in view of the amendments to claims 1 and 22 for teaching one of the first spacers is horizontally separated from the first blocking wall by a gap, and another one of the first spacers contacts/interfaces the second blocking wall that renders the amended claims 1 and 22 obvious (see 35 U.S.C. 103 rejection of claims 1 and 22 below).
Applicant's amendments to claim 30 and corresponding arguments, page 9 of the remarks, filed 01/16/2026, with respect to the 35 U.S.C 103 rejection of claim 30 as unpatentable over Pan in view of KR20210086948A; Yu et al.; (hereinafter “Yu”) have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Pan in view of Chang. Chang has been introduced in view of the amendments to claim 30 for teaching one of the first spacers is horizontally separated from the first blocking wall by a gap, and another one of the first spacers interfaces the second blocking wall that renders the amended claim 30 obvious (see 35 U.S.C. 103 rejection of claim 30 below).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 8, 21-30, and 32-33 are rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Chang.
Regarding Claim 1 (currently amended), Pan teaches a semiconductor device (Figure 1, [0019], semiconductor structure #100), comprising:
a substrate (#101, Figure 20B of Pan annotated) comprising a first fin and a second fin (fins #102/#103) separated by an insulating region (insulating material #126 separates #102);
a first stack of semiconductor nanosheets disposed on the first fin (Figure 20A or 21, stacks of nanostructure layers #106 disposes on fins #102/#103);
a second stack of semiconductor nanosheets disposed on the second fin (Figure 20A or 21, stacks of nanostructure layers #106 disposes on fins #102/#103);
a gate structure wrapping the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets (Figure 20A, gate electrode #172 and gate dielectric #170 surround #106); (spacers #152 contact dielectric features #140)
a first strained layer (#156/#EF1, Figure 20B of Pan annotated, multiple source/drain or S/D epitaxial features) disposed on the first fin (#EF1 disposes on #102) and abutting the first stack of semiconductor nanosheets (Figure 17C or 21, #156/#EF1 contacts #106);
a first blocking wall (#140/#DF1, Figure 20B of Pan annotated, dielectric features) disposed on the insulating region (#DF1 disposes on #126);
a second blocking wall (#140, multiple dielectric features) disposed on the insulating region (#126), wherein the first strained layer is sandwiched by the first blocking wall and the second blocking wall (S/D feature #156 disposes between dielectric features #140); and
two first spacers (#152-1, spacers) at opposite sides of the first strained layer (#EF1);
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wherein one of the first spacers is interfacing with the second blocking wall (spacers #152 contact dielectric features #140).
Pan does not explicitly teach one of the first spacers is horizontally separated from the first blocking wall by a gap, and another one of the first spacers is interfacing with the second blocking wall.
However, Chang teaches a semiconductor device ([0028], FinFET device) comprising one of the first spacers is horizontally separated from the first blocking wall by a gap, and another one of the first spacers is interfacing with the second blocking wall (Figures 20B of Pan and 10C of Chang annotated below, distance #d1 between the blocking wall and S/D epitaxial feature of Chang can be greater than distance #d1 of Pan. Accordingly, the blocking wall can be formed to remain in contact with one of the spacers and becomes separated from another one of the spacers).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Pan with the teaching of Chang as it would be a simple substitution of one known element (blocking wall configuration of Pan) for another (blocking wall configuration of Chang) in comparable devices to obtain predictable results (formation of a barrier structure that prevent shorting between S/D structures, see [0041] of Chang). See MPEP 2143(I)(B).
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Regarding Claim 2, Pan in view of Chang teaches the semiconductor device as described in claim 1, wherein Pan further teaches a bottom surface of the first blocking wall (#140) is higher than a top surface of the first fin or the second fin (Figure 20B, bottom surface of #140 is coplanar with top surface of fins #102).
Regarding Claim 3 (currently amended), Pan in view of Chang teaches the semiconductor device as described in claim 1, wherein Pan further teaches a second strained layer (#156, Figure 20B of Pan annotated, multiple S/D features) disposed on the second fin (#102/103, fins) and abutting the second stack of semiconductor nanosheets (Figure 17C or 21, #156 contacts #106), wherein a contact area (#C1) between the first blocking wall and the first strained layer is different from a contact area (#C2) between the first blocking wall and the second strained layer (S/D features #EF1-EF2 contact #140 separately at #C1 and #C2).
Regarding Claim 4 (currently amended), Pan in view of Chang teaches the semiconductor device as described in claim 1, wherein Pan further teaches a second strained layer (#156, Figure 20B of Pan annotated, multiple S/D features) disposed on the second fin (#102/103, fins) and abutting the second stack of semiconductor nanosheets (Figure 17C or 21, #156 contacts #106), and two second spacers (#152-2, Figure 20B of Pan annotated) at opposite sides of the second strained layer (#152-2 dispose on opposite sides of S/D #EF2).
Regarding Claim 5 (currently amended), Pan in view of Chang teaches the semiconductor device as described in claim 4, wherein Pan further teaches a gap (#151, Figure 20B of Pan annotated or Figure 10A) between the first blocking wall and one of the second spacers ([0042], spacers #152 fill #151 up to height #H1, and wherein #151 locates between dielectric features #DF1 and spacers #152-2).
Regarding Claim 6, Pan in view of Chang teaches the semiconductor device as described in claim 5, wherein Pan further teaches at least one of the second spacers (#152-2, Figure 20B of Pan annotated) is connected to the first blocking wall (#152-2 contacts #DF1).
Regarding Claim 8 (currently amended), Pan in view of Chang teaches the semiconductor device as described in claim 1, wherein Pan further teaches a contact etch stop layer (#158, Figure 20B, CESL) disposed on the top surface of the first blocking wall and the top surface of the first strained layer (#158 disposes on top of dielectric features #140 and S/D features #156).
Regarding Claim 21, Pan in view of Chang teaches the semiconductor device as described in claim 1, wherein Pan further teaches the first blocking wall (#140, Figure 20B) has a multi-layer structure ([0034] and [0036], #140 comprises layers #132, #134 and #138 of different dielectric materials).
Regarding Claim 22 (currently amended), Pan teaches a semiconductor device (Figure 1, [0019], semiconductor structure #100), comprising:
a first stack of semiconductor nanosheets (Figure 20A or 21, stacks of nanostructure layers #106);
a second stack of semiconductor nanosheets (#106);
a gate structure wrapping the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets (Figure 20A, gate electrode #172 and gate dielectric #170 surround #106);
a first strained layer (#156/#EF1, Figure 20B of Pan annotated, multiple source/drain or S/D epitaxial features) abutting the first stack of semiconductor nanosheets (Figure 17C or 21, #EF1 contacts #106);
a second strained layer (#156/#EF2) abutting the second stack of semiconductor nanosheets (Figure 17C or 21, #156/#EF2 contacts #106);
a first blocking wall (#140/#DF1, Figure 20B of Pan annotated, dielectric features) disposed on the insulating region (#DF1 disposes on #126) and located between the first strained layer and the second strained layer (#DF1 interposes #EF1 and #EF2);
a second blocking wall (#140, dielectric features) disposed on the insulating region (#140 disposes on #126), wherein the first strained layer is sandwiched by the first blocking wall and the second blocking wall (#EF1 disposes between multiple dielectric features #140); and
two first spacers (#152-1, spacers) at opposite sides of the first strained layer (#EF1);
wherein one of the first spacers is in physical contact with the second blocking wall (spacers #152 contact dielectric features #140).
Pan does not explicitly teach one of the first spacers is horizontally separated from the first blocking wall by an unfilled gap, and another one of the first spacers is in physical contact with the second blocking wall.
However, Chang teaches one of the first spacers is horizontally separated from the first blocking wall by an unfilled gap, and another one of the first spacers is in physical contact with the second blocking wall (Figures 20B of Pan and 10C of Chang annotated, distance #d1 between the blocking wall and S/D epitaxial feature of Chang can be greater than distance #d1 of Pan. Accordingly, the blocking wall can be formed to remain in contact with one of the spacers and becomes separated from another one of the spacers).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Pan with the teaching of Chang as it would be a simple substitution of one known element (blocking wall configuration of Pan) for another (blocking wall configuration of Chang) in comparable devices to obtain predictable results (formation of a barrier structure that prevent shorting between S/D structures, see [0041] of Chang). See MPEP 2143(I)(B).
Regarding Claim 23, Pan in view of Chang teaches the semiconductor device as described in claim 22, wherein Pan further teaches a contact area (#C1, Figure 20B annotated) between the first blocking wall and the first strained layer is different from a contact area (#C2) between the first blocking wall and the second strained layer (S/D features #156 contact dielectric feature #140 at #C1 and #C2).
Regarding Claim 24 (currently amended), Pan in view of Chang teaches the semiconductor device as described in claim 22,
Pan does not explicitly teach a contact area between the first blocking wall and the first strained layer is smaller than a contact area between the second blocking wall and the first strained layer.
However, Chang teaches a contact area between the first blocking wall and the first strained layer is smaller than a contact area between the second blocking wall and the first strained layer (Figure 10C, barrier #162 has different contact areas to its adjacent S/D epitaxial features).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Pan with the teaching of Chang for reason set forth in the rejection of claim 22.
Regarding Claim 25, Pan in view of Chang teaches the semiconductor device as described in claim 22, wherein Pan further teaches two second spacers (#152-2, Figure 20B of Pan annotated) at opposite sides of the second strained layer (#152-2 dispose on opposite sides of #EF2).
Regarding Claim 26 (currently amended), Pan in view of Chang teaches the semiconductor device as described in claim 25, wherein Pan further teaches an unfilled gap (#151, Figure 20B of Pan annotated or Figure 10A) between the first blocking wall and one of the second spacers. ([0042], spacers #152 fill #151 up to height #H1, and wherein #151 locates between #DF1 and #152-2).
Regarding Claim 27 (currently amended), Pan in view of Chang teaches the semiconductor device as described in claim 22, wherein Pan further teaches a first fin under the first stack of semiconductor nanosheets and a second fin under the second stack of semiconductor nanosheets (Figure 20A or 21, fins #102/103 are under semiconductor stacks #106), wherein a bottom surface of the first blocking wall or the second blocking wall (#140, Figure 20B, dielectric features) is higher than a top surface of the first fin or the second fin (bottom surface of #140 is coplanar with top surface of fins #102/103).
Regarding Claim 28, Pan teaches the semiconductor device as described in claim 22, wherein Pan further teaches the first blocking wall (#140, Figure 20B) has a multi-layer structure ([0034] and [0036], #140 comprises layers #132, #134 and #138 of different dielectric materials).
Regarding Claim 29, Pan teaches the semiconductor device as described in claim 22, wherein Pan further teaches the second blocking wall (#140, Figure 20B) has a multi-layer structure ([0034] and [0036], #140 comprises layers #132, #134 and #138 of different dielectric materials).
Regarding Claim 30 (currently amended), Pan teaches the semiconductor device, comprising:
a substrate (#101, Figure 20B);
a gate structure disposed over the substrate (Figure 20A, structure with gate electrode #172 and gate dielectric #170 disposes on #101);
multiple strained layers (#156, Figure 20B of Pan annotated, S/D epitaxial features) disposed at opposite sides of the gate structure (#156 dispose on both sides of #172); and
first and second blocking walls (#140, dielectric features) at opposite sides of an adjacent strained layer (#140 dispose on opposite sides of #172); and
two first spacers (#152-1/#152-2, spacers) at opposite sides of the adjacent strained layer (#156), and
one of the first spacers is interfacing with the second blocking wall (spacers #152-1/#152-2 contact #140).
Pan does not explicitly teach one of the first spacers is horizontally separated from the first blocking wall by a gap, and another one of the first spacers is interfacing with the second blocking wall.
However, Chang teaches one of the first spacers is horizontally separated from the first blocking wall by a gap, and another one of the first spacers is interfacing with the second blocking wall (Figures 20B of Pan and 10C of Chang annotated, distance #d1 between the blocking wall and S/D epitaxial feature of Chang can be greater than distance #d1 of Pan. Accordingly, the blocking wall can be formed to remain in contact with one of the spacers and becomes separated from another one of the spacers).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Pan with the teaching of Chang as it would be a simple substitution of one known element (blocking wall configuration of Pan) for another (blocking wall configuration of Chang) in comparable devices to obtain predictable results (formation of a barrier structure that prevent shorting between S/D structures, see [0041] of Chang). See MPEP 2143(I)(B).
Regarding Claim 32 (currently amended), Pan in view of Yu teaches the semiconductor device as described in claim 30, wherein Pan further teaches each of the first and second blocking walls has a multi-layer structure (Figure 20B, [0034] and [0036], dielectric features #140 comprise layers #132, #134 and #138 of different dielectric materials).
Regarding Claim 33, Pan in view of Yu teaches the semiconductor device as described in claim 30, wherein Pan further teaches a contact etch stop layer covering the multiple strained layers and the first and second blocking walls, wherein the first blocking wall comprises a first blocking layer and a second blocking layer, and top surfaces of the first blocking layer and the second blocking layer respectively interface the contact etch stop layer (Figure 20B, CESL #158 covers top surfaces of S/D epitaxial features #156 and dielectric features #140).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Pan in view of Chang, and further in view of US 2022/0254776 A1; Cheng et al.; (hereinafter “Cheng”).
Regarding Claim 7, Pan in view of Chang teaches the semiconductor structure as described in claim 1.
Pan in view of Chang does not explicitly teach a liner layer between the first fin and the first strained layer and between the second fin and the second strained layer.
However, Cheng teaches a semiconductor structure ([0012], multi-bridge-channel or MBC transistor) comprises a liner layer (#236, Figure 30, Si epitaxial layer) between the first fin (#202, fin sections of the substrate) and the first strained layer (#238/#240, drain features) and between the second fin (#202, fin sections of the substrate) and the second strained layer (#238/#240, drain features).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Pan in view of Chang with the teaching of Cheng so that a liner layer between the first fin and the first strained layer and between the second fin and the second strained layer in order to utilize the high resistivity of the layer to prevent undesirable leakage from the source/drain feature into the substrate according to [0031] of Cheng.
Conclusion
The prior art made of record and no relied upon is considered pertinent to applicant’s disclosure.
US20180337176A1 – Figures 21B-C
US20170012042A1 – Figures 18-21
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812