DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 10/27/2025 Amendment and RCE.
Claims 1-20 are pending and examined.
Claim Rejections - 35 USC § 112
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites limitations “a first metal capacitor connected between a selected bit line and a gate of a second transistor switch, wherein the first metal capacitor is operable to drive the selected bit line to a negative voltage in response to the boost signal; and a second metal capacitor having a first end coupled to the word line voltage node and a second end operative to receive the boost signal” on lines 8-14.
The disclosure does not describe a first metal capacitor connected to a selected bit line in response to a boost signal, and a second metal capacitor coupled to the word line voltage node and in response to a the same boost signal. In other words, the disclosure teaches first and second metal capacitors with parallel connections coupled to either selected bit line node as in FIG. 3 or a word line node as in FIG. 5. There is no suggestion that there are combinations of FIGS. 1 and 4, or FIGS. 3 and 5.
Claim 10 recites limitations “a first metal capacitor connected between a selected bit line and a gate of a second transistor switch, wherein the first metal capacitor is operable to drive the selected bit line to a negative voltage in response to the boost signal; and a second metal capacitor having a first end coupled to the word line voltage node and a second end operative to receive the boost signal, wherein the metal capacitor is operative to drive a word line voltage of the word line voltage node to a boosted value from the supply voltage in response to the boost signal.” on lines 12-18.
Claim 10 is rejected for the same reason as in claim 1.
Claim 16 recites limitations “a first metal capacitor coupled to the word line voltage node, wherein the first metal capacitor is operative to drive a word line voltage of the word line voltage node to a boosted value from the supply voltage in response to the boost signal; and a second metal capacitor connected between a selected bit line and a gate of a second transistor switch, wherein the second metal capacitor is operable to drive the selected bit line to a negative voltage in response to the boost signal.” on lines 12-21.
Claim 16 is rejected for the same reason as in claim 1.
For purpose of examination, Examiner temporary does not consider the amended limitations of claims 1, 10 and 16.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over US 9,424,912 to Wu (hereafter Wu) in view of US 7,227,792 to Takahashi et al. (hereafter Takahashi).
Regarding independent claim 1, Wu teaches a write assist circuit comprising:
a first transistor switch connected between a bit line voltage node and a supply voltage, wherein a gate of the first transistor switch is operative to receive a boost signal FIG. 6A: transistor t0 coupled to bit line voltage node NVS and ground, and receive boost signal BST at the gate);
a second transistor switch connected between the bit line voltage node and the supply voltage, wherein a gate of the second transistor switch is coupled to the bit line voltage node (FIG. 6A: over-boost prevention circuit, which comprises PMOS transistor shown in FIG. 6D); and
a metal capacitor having a first end coupled to the bit line voltage node and a second end operative to receive the boost signal, wherein the metal capacitor is operative to drive a bit line voltage of the bit line voltage node to a boosted value from the supply voltage in response to the boost signal (FIG. 6A: capacitor CAP coupled between BST and NVS).
Wu teaches the write assist circuit is coupled to a bit line voltage node instead of word line voltage node, and the supply voltage is ground voltage instead of high potential supply voltage. Wu doesn’t explicitly teach the boost signal is in response to a write enable signal, but shows they are related (FIG. 2: boost signal BST is active when write enable signal WE is active with some delay).
Takahashi teaches a word line voltage node is boosted in response to write enable signal (FIG. 3: word line voltage node VBST is boosted in response to signal /WE; FIG. 4 shows boost signal ΦBEN is active when write enable signal WE is active with some delay, similar to that of Wu). Takahashi further teaches the word line voltage node is boosted from positive supply voltage to a higher voltage (see FIG. 2).
Since Wu and Takahashi are both from the same field of endeavor, the purpose disclosed by Wu would have been recognized in the pertinent art of Takahashi.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the write assist circuit described in Wu and use it to boost the word line voltage node of memory device in Takahashi from positive supply voltage to higher voltage in order to strengthen the writing operation. Modification made to the write assist circuit of Wu would include replacing the pull-down transistors t0 [coupled to ground] with a pull-up transistor [coupled to positive supply voltage]; signal BST with inverted BST signal. Applicant is kindly noticed that the modified write assist circuit would pretty much look like word line boost circuit 402’ of FIG. 5 in the pending application minus capacitor 406.
Regarding dependent claim 2, Wu teach wherein the boost signal is operative to turn off the first transistor switch, initiate charging of the metal capacitor, and boost the bit line voltage (FIG. 2: signal BST turns off transistor t0, boosting BL0 to negative potential, see 4:58-62).
Regarding dependent claim 3, Takahashi teaches a word line driver circuit operative to provide the word line voltage to a word line of a cell array (FIG. 3: word driver 104).
Claims 4, 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Takahashi in view of US 8,072,823 to Aihara et al. (hereafter Aihara).
Wu and Takahashi teach, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 4, Aihara teaches a write assist circuit used to boost bit line voltage coupled to selected memory cell(s) to a negative voltage (see FIGS. 1 and 2). The write assisted circuit comprises a metal oxide semiconductor connected in parallel to the metal capacitor (e.g. FIG. 9: metal oxide C12 coupled in parallel to a metal oxide semiconductor QND).
Since Wu, Takahashi and Aihara are all from the same field of endeavor, the purpose disclosed by Aihara would have been recognized in the pertinent art of Wu/Takahashi.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace capacitor CAP in FIG. 6A of Wu with parallel connected capacitors in FIG. 9 of Aihara in order to have sufficient capacitance to generated required boosted potential while reducing degradation of each element (see Aihara, 8:1-18).
Regarding independent claim 10,Wu teaches a write assist circuit comprising:
a first transistor connected between a bit line voltage node and a supply voltage, wherein a gate of the first transistor is operative to receive a boost signal FIG. 6A: transistor t0 coupled to bit line voltage node NVS and ground, and receive boost signal BST at the gate);
a second transistor connected between the bit line voltage node and the supply voltage, wherein a gate of the second transistor is coupled to the bit line voltage node (FIG. 6A: over-boost prevention circuit, which comprises PMOS transistor shown in FIG. 6D);
a metal capacitor having a first end coupled to the bit line voltage node and a second end operative to receive the boost signal, wherein the metal capacitor is operative to drive a bit line voltage of the bit line voltage node to a boosted value from the supply voltage in response to the boost signal (FIG. 6A: capacitor CAP coupled between BST and NVS).
Wu doesn’t teach the strikethrough limitations, and the boost signal is in response to a write enable signal, but shows they are related (FIG. 2: boost signal BST is active when write enable signal WE is active with some delay). Wu teaches the write assist circuit is coupled to a bit line voltage node instead of word line voltage node, and the supply voltage is ground voltage instead of high potential supply voltage.
Takahashi teaches a word line voltage node is boosted in response to write enable signal (FIG. 3: word line voltage node VBST is boosted in response to signal /WE; FIG. 4 shows boost signal ΦBEN is active when write enable signal WE is active with some delay, similar to that of Wu). Takahashi further teaches the word line voltage node is boosted from positive supply voltage to a higher voltage (see FIG. 2).
Aihara teaches a write assist circuit used to boost bit line voltage coupled to selected memory cell(s) to a negative voltage (see FIGS. 1 and 2). The write assisted circuit comprises a metal oxide semiconductor connected in parallel to the metal capacitor (e.g. FIG. 9: metal oxide C12 coupled in parallel to a metal oxide semiconductor QND), wherein the metal oxide semiconductor comprising a third transistor connected between the word line voltage node and the supply voltage, wherein a gate of the third transistor is coupled to the word line voltage node, and wherein a source and a drain of the third transistor are connected together and are operative to receive the boost signal.
Since Wu, Takahashi and Aihara are all from the same field of endeavor, the purpose disclosed by Takahashi and Aihara would have been recognized in the pertinent art of Wu.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
modify the write assist circuit described in Wu and use it to boost the word line voltage node of memory device in Takahashi from positive supply voltage to higher voltage in order to strengthen the writing operation. Modification made to the write assist circuit of Wu would include replacing the pull-down transistors t0 [coupled to ground] with a pull-up transistor [coupled to positive supply voltage]; signal BST with inverted BST signal. Applicant is kindly noticed that the modified write assist circuit would pretty much look like word line boost circuit 402’ of FIG. 5 in the pending application minus capacitor 406; and
replace capacitor CAP in FIG. 6A of Wu with parallel connected capacitors in FIG. 9 of Aihara in order to have sufficient capacitance to generated required boosted potential while reducing degradation of each element (see Aihara, 8:1-18).
Regarding dependent claim 11, Takahashi teaches a word line driver circuit operative to provide the word line voltage to a word line of a cell array (FIG. 3: word driver 104).
Claims 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Takahashi in view of US 8,022,458 to Chang et al. (hereafter Chang).
Wu and Takahashi teach, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 5, Chang teaches wherein the metal capacitor is a hand clasping style metal capacitor comprising a first plurality of metal stripes and a second plurality of metal stripes (see FIG. 2).
Since Wu, Takahashi and Chang are all from the same field of endeavor, the purpose disclosed by Chang would have been recognized in the pertinent art of Wu/Takahashi.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that style of capacitor used in Wu/Takahashi is a matter of design choice as long as it serves the purpose of providing sufficient capacitance for the performance of the circuit.
Regarding dependent claim 6, Chang teaches wherein a length of at least one of the first plurality of metal stripes and the second plurality of metal stripes comprises a base length and an extended length, wherein the extended length is less than or equal to a word line length of a cell array (it is seen that the extended length of the first and second metal stripes should be less than the word line length because the desired capacitance of capacitor C21 is just enough to pull the bit line voltage to some negative value as shown in FIG. 2).
Regarding dependent claim 7, Chang teaches wherein the first plurality of metal stripes are in a first metal layer and the second plurality of metal stripes are formed in a second metal layer, the second metal layer being different from the first metal layer (FIG. 2: e.g. metal stripe layers 1 and 2).
Regarding dependent claim 8, Chang teaches wherein the first plurality of metal stripes form a first sub-capacitor and the second plurality of metal stripes form a second sub-capacitor, wherein the second sub-capacitor is parallel to the first sub-capacitor (FIG. 2: the structure as shown comprising parallel sub-capacitors).
Regarding dependent claim 9, Chang teaches wherein at least one of the first sub-capacitor and the second sub-capacitor is selectively enabled (because the capacitor in Chang for usage, they should be enabled while using).
Claims 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Takahashi in view of Aihara in view of Chang.
Wu, Takahashi and Aihara teach, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 12, Chang teaches wherein the metal capacitor is a hand clasping style metal capacitor comprising a first plurality of metal stripes and a second plurality of metal stripes (see FIG. 2).
Since Wu, Takahashi and Aihara and Chang are all from the same field of endeavor, the purpose disclosed by Chang would have been recognized in the pertinent art of Wu/Takahashi/Aihara.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that style of capacitor used in Wu/Takahashi is a matter of design choice as long as it serves the purpose of providing sufficient capacitance for the performance of the circuit.
Regarding dependent claim 13, Chang teaches wherein a length of at least one of the first plurality of metal stripes and the second plurality of metal stripes comprises a base length and an extended length, wherein the extended length is less than or equal to a word line length of a cell array (it is seen that the extended length of the first and second metal stripes should be less than the word line length because the desired capacitance of capacitor C21 is just enough to pull the bit line voltage to some negative value as shown in FIG. 2).
Regarding dependent claim 14, Chang teaches wherein the first plurality of metal stripes are in a first metal layer and the second plurality of metal stripes are formed in a second metal layer, the second metal layer being different from the first metal layer (FIG. 2: e.g. metal stripe layers 1 and 2).
Regarding dependent claim 15, Chang teaches wherein the first plurality of metal stripes form a first sub-capacitor and the second plurality of metal stripes form a second sub-capacitor, wherein the second sub-capacitor is parallel to the first sub-capacitor (FIG. 2: the structure as shown comprising parallel sub-capacitors).
Regarding independent claim 16, Wu teaches a write assist circuit comprising:
a first transistor connected between a bit line voltage node and a supply voltage, wherein a gate of the first transistor is operative to receive a boost signal FIG. 6A: transistor t0 coupled to bit line voltage node NVS and ground, and receive boost signal BST at the gate);
a second transistor connected between the bit line voltage node and the supply voltage, wherein a gate of the second transistor is coupled to the bit line voltage node (FIG. 6A: over-boost prevention circuit, which comprises PMOS transistor shown in FIG. 6D);
a first metal capacitor bit line voltage node, bit line voltage node to a boosted value from the supply voltage in response to the boost signal (FIG. 6A: capacitor CAP coupled between BST and NVS).
Wu doesn’t teach the strikethrough limitations, and the boost signal is in response to a write enable signal, but shows they are related (FIG. 2: boost signal BST is active when write enable signal WE is active with some delay). Wu teaches the write assist circuit is coupled to a bit line voltage node instead of word line voltage node, and the supply voltage is ground voltage instead of high potential supply voltage.
Takahashi teaches a word line voltage node is boosted in response to write enable signal (FIG. 3: word line voltage node VBST is boosted in response to signal /WE; FIG. 4 shows boost signal ΦBEN is active when write enable signal WE is active with some delay, similar to that of Wu). Takahashi further teaches the word line voltage node is boosted from positive supply voltage to a higher voltage (see FIG. 2).
Aihara teaches a write assist circuit used to boost bit line voltage coupled to selected memory cell(s) to a negative voltage (see FIGS. 1 and 2). The write assisted circuit comprises a metal oxide semiconductor connected in parallel to the metal capacitor (e.g. FIG. 9: metal oxide C12 coupled in parallel to a metal oxide semiconductor QND), wherein the metal oxide semiconductor comprising a third transistor connected between the word line voltage node and the supply voltage, wherein a gate of the third transistor is coupled to the word line voltage node, and wherein a source and a drain of the third transistor are connected together and are operative to receive the boost signal.
Chang teaches a metal capacitor comprising a first plurality of metal stripes substantially parallel to each other and a second plurality of metal stripes substantially parallel to each other (see FIG. 2).
Since Wu, Takahashi, Aihara and Chang are all from the same field of endeavor, the purpose disclosed by Takahashi, Aihara and Chang would have been recognized in the pertinent art of Wu.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to:
modify the write assist circuit described in Wu and use it to boost the word line voltage node of memory device in Takahashi from positive supply voltage to higher voltage in order to strengthen the writing operation. Modification made to the write assist circuit of Wu would include replacing the pull-down transistors t0 [coupled to ground] with a pull-up transistor [coupled to positive supply voltage]; signal BST with inverted BST signal. Applicant is kindly noticed that the modified write assist circuit would pretty much look like word line boost circuit 402’ of FIG. 5 in the pending application minus capacitor 406; and
replace capacitor CAP in FIG. 6A of Wu with parallel connected capacitors in FIG. 9 of Aihara in order to have sufficient capacitance to generated required boosted potential while reducing degradation of each element (see Aihara, 8:1-18);
realize that style of capacitor used in Wu/Takahashi is a matter of design choice as long as it serves the purpose of providing sufficient capacitance for the performance of the circuit.
Regarding dependent claim 17, Chang teaches wherein the first metal capacitor is a hand clasping style metal capacitor (see FIG. 2).
Regarding dependent claim 18, Chang teaches wherein the first plurality of metal stripes are in a first metal layer and the second plurality of metal stripes are formed in a second metal layer, the second metal layer being different from the first metal layer (FIG. 2: e.g. metal stripe layers 1 and 2).
Regarding dependent claim 19, Chang teaches wherein the first plurality of metal stripes form a first sub-capacitor and the second plurality of metal stripes form a second sub-capacitor, wherein the second sub-capacitor is parallel to the first sub-capacitor (FIG. 2: the structure as shown comprising parallel sub-capacitors).
Regarding dependent claim 20, Chang teaches wherein at least one of the first sub-capacitor and the second sub-capacitor is selectively enabled (because the capacitor in Chang for usage, they should be enabled while using).
Response to Arguments
Applicant's arguments filed 10/27/2025 have been fully considered but they are not persuasive due to rejection of 112, 1st paragraph above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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December 8, 2025
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824