DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/27/26 has been entered.
Information Disclosure Statement
Applicant’s IDS submitted on 7/25/25, 9/13/23, 4/2/24, 4/17/24, and 10/14/24 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have been considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8, 11, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wan et al., US 20140042298 A1, hereafter Wan in view of Huang et al., US 20210185260 A1, hereafter Huang and Stettner et al., US 20210276545 A1, hereafter Stettner.
Regarding independent claim 1, Wan discloses the following limitations:
A semiconductor device (Wan, Figure 2, sensor chip 20, Read-out chip 100, and peripheral circuit chip 200 [0012] discloses a sensor chip formed on semiconductor substrates), comprising:
a first chip (Wan, Figure 9, image sensor chip 20 ) comprising a plurality of photo-sensitive devices (Wan, Figure 9, image sensors 24), wherein the plurality of photo-sensitive devices are formed as a first array (Wan, Figure 9, image sensors 24, and [0012] discloses Figure 11 as an array of photo diodes 24);
a second chip (Wan, Figure 9, read-out chip 100) bonded to the first chip and comprising:
a plurality of groups of pixel transistors (Wan, Figure 3, and [0017] device chip 100 containing a plurality of transistors, including row selectors 126, source followers 128, and reset transistors 130. Each of pixel unit portions 124 including one of row selectors 126, one of source followers 128, and one of and reset transistors 130), wherein the plurality of groups of pixel transistors are formed as a second array (Wan, Figure 1, 100/102 shows an array); and
a third chip (Wan, Figure 1, peripheral circuit chip 200) bonded to the second chip and comprising a plurality of logic transistors (Wan, Figure 7, logic circuits 204, and [0027] discloses such circuits include Image Signal Processing (ISP) circuits that are used for processing the image-related signals obtained from chips 20 and 100. Exemplary ISP circuits include Analog-to-Digital Converters (ADCs), Correlated Double Sampling (CDS) circuits).
Wan fails to disclose the following limitations:
a plurality of input/output transistors, wherein the plurality of input/output transistors are disposed along edges of the second array;
Huang discloses the following limitations:
a plurality of input/output transistors (Huang, Figure 10, plurality of output circuits 111S, and pulling circuits 12 located outside of the array, and Figure 1 shows transistors in both circuits, and the row decoder 14 and column decoder 15 are also outside of the array).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to have applied the teachings of Huang to the device of Wan and to therefore place the input/output transistors outside of the array. Doing so desirably reduces the size of the pixel array and increases the fill factor.
Wan and Huang fail to disclose the following limitations:
wherein the plurality of input/output transistors collectively at least laterally surround a plurality of edges of the second array;
Stettner discloses the following limitations:
wherein the plurality of input/output transistors collectively at least laterally surround a plurality of edges of the second array (Stettner, Figure 18, detector array 66, shows column amplifiers 264 and row amplifiers 258 surrounding electrical circuit 260, and [0061])
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have placed the input/output circuits around a plurality of edges of the circuits of Wan and Huang. Doing so is taught by Stettner, and would desirably reduce the length of the connections to the bonding pads which are located on a plurality of edges of the chip to allow easy access when wire bonding to the chip.
Regarding claim 2, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 1, wherein each of the photo-sensitive devices of the first array physically and electrically corresponds to a corresponding one of the groups of pixel transistors of the second array (Wan, Figure 9, pixel units 300 shows image sensors 24 physically correspond to and electrically connect to source followers 128 and reset transistors 130).
Regarding claim 3, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 1, wherein the input/output transistors collectively function as an input/output circuit for an image sensor constituted by the first to third chips (Huang, [0012] discloses that the image sensor has a plurality of output circuits and that the plurality of output circuits read the output voltage).
Regarding claim 4, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 3, wherein the input/output circuit is selected from the group consisting of: an electrostatic discharge (ESD) protection circuit, a column decoder, a row decoder, a level shift circuit, and combinations thereof (Huang, Figure 10, row decoder 14 and column decoder 15 supply the pixel position [0032]).
Regarding claim 5, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 1, wherein each of the photo-sensitive devices and a corresponding one of the groups of pixel transistors form at least, in part, one of a plurality of pixel units of an image sensor array (Wan, Figure 9, pixel units 300 are shown that include image sensors 24, source followers 128 and reset transistors 130).
Regarding claim 6, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 5, wherein each of the pixel units further includes a transfer gate transistor (Wan, Figure 9, transfer gate transistors 28) and a capacitor (Wan Figure 9, capacitors 32) formed within the first array (Wan, Figure 9, image sensors 24, and [0012] discloses Figure 11 as an array of photo diodes 24).
Regarding claim 7, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 1, wherein each of the groups of pixel transistor (Wan, Figure 1, where 100/102 is the second array) includes a reset transistor (Wan, Figure 8, reset transistors 130), a source follower (Wan, Figure 8, source followers 128), and a row selector (Wan, Figure 8, row selectors 126).
Regarding claim 8, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 1, wherein the logic transistors collectively function as an Image Signal Processing (ISP) circuit selected from the group consisting of: an Analog-to-Digital Converter (ADC) circuit, a Digital-to-Analog Converter (DAC) circuit, a Correlated Double Sampling (CDS) circuit, and combinations thereof (Wan, Figure 7, logic circuits 204, and [0027] discloses logic circuits to include Analog-to-Digital Converters (ADCs), Correlated Double Sampling (CDS) circuits)
Regarding independent claim 11, Wan discloses the following limitations:
A semiconductor device (Wan, Figure 2, sensor chip 20, Read-out chip 100, and peripheral circuit chip 200 [0012] discloses a sensor chip formed on semiconductor substrates), comprising:
a first chip (Wan, Figure 9, image sensor chip 20 ) comprising:
a first semiconductor substrate (Wan, Figure 2, semiconductor substrate 26);
a plurality of photo-sensitive devices (Wan, Figure 24, image sensors 24) formed over the first semiconductor substrate;
a plurality of transfer gate transistors (Wan, Figure 2, transfer gate transistors 28) formed over the first semiconductor substrate; and
a plurality capacitors (Wan Figure 2, capacitors 32) formed over the first semiconductor substrate;
a second chip (Wan, Figure 9, read-out chip 100) comprising:
a second semiconductor substrate (Wan, Figure 3, substrate 120);
a plurality of reset transistors (Wan, Figure 3, reset transistors 130) formed over the second semiconductor substrate;
a plurality of source followers (Wan, Figure 3, source followers 128) formed over the second semiconductor substrate;
a plurality of row selectors (Wan, Figure 3, row selectors 126) formed over the second semiconductor substrate; and
a third chip (Wan, Figure 1, peripheral circuit chip 200) comprising:
a third semiconductor substrate (Wan, Figure 8, semiconductor substrate 220); and
a plurality of logic transistors formed over the third semiconductor substrate (Wan, Figure 7, logic circuits 204, and [0027] discloses such circuits include Image Signal Processing (ISP) circuits that are used for processing the image-related signals obtained from chips 20 and 100. Exemplary ISP circuits include Analog-to-Digital Converters (ADCs), Correlated Double Sampling (CDS) circuits);
wherein the first to third chips are vertically bonded to one another (Wan, Shown, Figure 7).
Wan fails to disclose the following limitations:
a plurality of input/output transistors formed over the second semiconductor substrate,
wherein the plurality of input/output transistors are collectively disposed along a plurality of edges of the second semiconductor substrate
Huang discloses the following limitations:
a plurality of input/output transistors formed over the second semiconductor substrate; (Huang, Figure 10, plurality of output circuits 111S, and pulling circuits 12 located outside of the array, and Figure 1 shows transistors in both circuits, and the row decoder 14 and column decoder 15 are also outside of the array).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to have applied the teachings of Huang to the device of Wan and to therefore place the input/output transistors outside of the array. Doing so desirably reduces the size of the pixel array and increases the fill factor.
Wan and Huang fail to disclose the following limitations:
wherein the plurality of input/output transistors are collectively disposed along a plurality of edges of the second semiconductor substrate
Stettner discloses the following limitations:
wherein the plurality of input/output transistors are collectively disposed along a plurality of edges of the second semiconductor substrate (Stettner, Figure 18, detector array 66, shows column amplifiers 264 and row amplifiers 258 surrounding electrical circuit 260, and [0061])
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have placed the input/output circuits around a plurality of edges of the circuits of Wan and Huang. Doing so is taught by Stettner, and would desirably reduce the length of the connections to the bonding pads which are located on a plurality of edges of the chip to allow easy access when wire bonding to the chip.
Regarding claim 15, the combination of Wan, Huang and Stettner disclose the following limitations:
The semiconductor device of claim 11, wherein the first chip (Wan, Figure 4, chip 20) is bonded to the second chip (Wan, Figure 4, chip 120), with a front surface of the first semiconductor substrate facing a front surface of the second semiconductor substrate (Wan, Figure 4, shows chip 20 and 120 bonded, where the front surface of chip 20 is the surface away from substrate 26 and the front surface of chip 100 is the surface away from substrate 120), and wherein the second chip (Wan, Figure 8, 100) is bonded to the third chip (Wan, Figure 8, chip 200) through one or more through substrate via (TSV) structures (Wan, Figure 8, through Substrate Vias (TSVs) 146).
Regarding claim 16, the combination of Wan, Huang and Stettner fail to disclose the following limitations:
The semiconductor device of claim 11, wherein the first chip is bonded to the second chip through one or more through substrate via (TSV) structures, with a front surface of the first semiconductor substrate facing a back surface of the second semiconductor substrate, and wherein the second chip is bonded to the third chip through one or more metal pads.
Wan discloses the use of both TSV bonding and bonding though metal pads. The difference between Wan and the instant claim is that Wan uses bonding by metal pads between the first and second chips and TSV bonding between the second and third chips. Both TSV bonding and metal pad bonding were known in the art as both are taught by Wan. One of ordinary skill in the art could have substituted TSV bonding for metal pad bonding or metal pad bonding for TSV bonding and the results of such a substitution would have been predictable. It would have been obvious to one of ordinary skill in the art to substitute one known element TSV bonding (or metal pad bonding) for another known equivalent, metal pad bonding (or TSV bonding) resulting in the predictable result of bonding two chip together.
Regarding claim 17, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 11, wherein the plurality of reset transistors, the plurality of source followers, and the plurality of row selectors are formed as an array, with the plurality of input/output transistors disposed around the array (Huang, Figure 10, plurality of output circuits 111S, and pulling circuits 12, and Figure 1 shows transistors in both circuits, and the row decoder 14 and column decoder 15 are shown outside the pixel array that contains the pixel circuit of which the reset transistors, the plurality of source followers, and the plurality of row selectors are part of because they are circuitry associated with the pixel.)
Regarding claim 18, the combination of Wan, Huang, and Stettner disclose the following limitations:
The semiconductor device of claim 11, wherein the plurality of input/output transistors collectively function as one or more input/output circuits each selected from the group consisting of: an electrostatic discharge (ESD) protection circuit, a column decoder, a row decoder, a level shift circuit, and combinations thereof (Huang, Figure 10, row decoder 14 and column decoder 15 supply the pixel position [0032]).
Regarding independent claim 19, the combination of Wan, Huang, and Stettner disclose the following limitations:
A method, comprising:
forming a first chip (Wan, Figure 2, chip 20) including a plurality of photo-sensitive devices (Wan, Figure 2, image sensors 24) disposed over a first semiconductor substrate (Wan, Figure 2, substrate 26);
forming a second chip (Wan, Figure 3, chip 100) including: (i) a plurality of reset transistors (Wan, Figure 3, reset transistors 130), disposed over a second semiconductor substrate; (ii) a plurality of source followers (Wan, Figure 3, source followers 128) disposed over the second semiconductor substrate; (iii) a plurality of row selectors (Wan, Figure 3, row selectors 126) disposed over the second semiconductor substrate;
bonding the second chip to the first chip (Wan, Figure 4, and [0021] discloses that chips 20 and 100 are bonded);
forming a third chip (Wan, Figure 7, chip 200) including a plurality of logic transistors (Wan, Figure 7, logic circuits 204 [0027]) disposed over a third semiconductor substrate; and
bonding the third chip to the second chip (Wan, Figure 7, and [0027] discloses that chip 200 is bonded to chip 100).
Wan fails to disclose the following limitations:
(iv) a plurality of input/output transistors disposed over the second semiconductor substrate and along edges of the second semiconductor substrate;
Huang discloses the following limitations:
(iv) a plurality of input/output transistors disposed over the second semiconductor substrate; (Huang, Figure 10, plurality of output circuits 111S, pulling circuits 12, Figure 1 shows transistors in both circuits, and the row decoder 14 and column decoder 15 shown outside the array).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date to have applied the teachings of Huang to the device of Wan and to therefore place the input/output transistors outside of the array. Doing so desirably reduces the size of the pixel array and increases the fill factor.
Wan and Huang fail to disclose the following limitations:
collectively disposed along a plurality of edges of the second semiconductor substrate;
Stettner discloses the following limitations:
collectively disposed along a plurality of edges of the second semiconductor substrate (Stettner, Figure 18, detector array 66, shows column amplifiers 264 and row amplifiers 258 surrounding electrical circuit 260, and [0061]);
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have placed the input/output circuits around a plurality of edges of the circuits of Wan and Huang. Doing so is taught by Stettner, and would desirably reduce the length of the connections to the bonding pads which are located on a plurality of edges of the chip to allow easy access when wire bonding to the chip.
Regarding claim 20, the combination of Wan, Huang, and Stettner discloses the following limitations:
The method of claim 19, wherein, on the second semiconductor substrate, the plurality of reset transistors, the plurality of source followers, and the plurality of row selectors are formed as an array, with the plurality of input/output transistors disposed around the array (Huang, Figure 10, plurality of output circuits 111S, pulling circuits 12, Figure 1 shows transistors in both circuits, and the row decoder 14 and column decoder 15 shown outside the array).
Claims 9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wan, Huang, and Stettner as applied to claim 1 and 11 above, and further in view of Lee et al., US 20220102404 A1, hereafter Lee.
Regarding claim 9, the combination of Wan, Huang, and Stettner fail to disclose the following limitations:
The semiconductor device of claim 1, wherein the plurality of groups of pixel transistors and the plurality of input/output transistors operate under a first supply voltage, and the plurality of logic transistors operate under a second supply voltage, and wherein the first supply voltage is substantially higher than the second supply voltage
Lee discloses the following limitations:
The semiconductor device of claim 1, wherein the plurality of groups of pixel transistors and the plurality of input/output transistors operate under a first supply voltage, and the plurality of logic transistors operate under a second supply voltage, and wherein the first supply voltage is substantially higher than the second supply voltage (Lee [0131] discloses logic circuitry wafer may be implemented with low voltage transistors, whereas an inverter implemented on a pixel cell may make use of higher voltage transistors, the voltage difference between low and high transistors is considered to be substantial otherwise a voltage level shifter would not be needed [0131]).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Lee to the device of Wan, Huang, and Stettner because Lee teaches that using transistors with different operating voltages eliminates the need for a voltage level shifter between the output of the pixel cell [0131].
Regarding claim 12, the combination of Wan, Huang, and Stettner fail to disclose the following limitations:
The semiconductor device of claim 11, wherein the plurality of reset transistors, the plurality of source followers, the plurality of row selectors, and the plurality of input/output transistors operate under a first supply voltage, and the plurality of logic transistors operate under a second supply voltage, and wherein the first supply voltage is substantially higher than the second supply voltage.
Lee discloses the following limitations:
wherein the plurality of reset transistors, the plurality of source followers, the plurality of row selectors, and the plurality of input/output transistors operate under a first supply voltage, and the plurality of logic transistors operate under a second supply voltage, and wherein the first supply voltage is substantially higher than the second supply voltage (Lee [0131] discloses logic circuitry wafer may be implemented with low voltage transistors, whereas an inverter implemented on a pixel cell may make use of higher voltage transistors, the voltage difference between low and high transistors is considered to be substantial otherwise a voltage level shifter would not be needed [0131]).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Lee to the device of Wan, Huang, and Stettner because Lee teaches that using transistors with different operating voltages eliminates the need for a voltage level shifter between the output of the pixel cell [0131].
Claims 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Wan and Huang, and Stettner as applied to claim 1 and 11 above, and further in view of Takashima JP H08316328 A, hereafter Takashima and Mochizuki, JP H08240814 A, hereafter Mochizuki.
Regarding claim 10, the combination of Wan, Huang, and Stettner fail to disclose the following limitations:
The semiconductor device of claim 1, wherein the plurality of groups of pixel transistors and the plurality of input/output transistors are formed with a first dimension, and the plurality of logic transistors operate are formed with a second dimension, and wherein the first dimension is substantially greater than the second dimension.
Takashima discloses the following limitations:
wherein the plurality of input/output transistors are formed with a first dimension, and the plurality of logic transistors operate are formed with a second dimension, and wherein the first dimension is substantially greater than the second dimension (Takashima discloses “A plurality of transistors each having a size smaller than that of the transistor of the input / output cell bulk 43 may be formed therein, and a logic circuit may be configured using these transistors.“).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Takashima to the device of Wan, Huang, and Stettner. Doing so would desirably allow the size of the logic circuit to be reduced or allow more transistors to be included in the logic devices.
Wan, Huang, Stettner and Takashima fail to disclose the following limitations:
the plurality of groups of pixel transistors are formed with a first dimension, and the plurality of logic transistors operate are formed with a second dimension, and wherein the first dimension is substantially greater than the second dimension.
Mochizuki discloses the following limitations:
the plurality of groups of pixel transistors are formed with a first dimension, and the plurality of logic transistors operate are formed with a second dimension, and wherein the first dimension is substantially greater than the second dimension (Mochizuki discloses “the processing size of the transistor in the pixel portion is made smaller than that in the peripheral drive circuit portion”).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date to have applied the teachings of Mochizuki to the device of Wan, Huang, Stettner, and Takashima. Doing so would allow more pixels to be fabricated in the same area, and therefore allow for higher resolution of the image device.
Regarding claim 14 the combination of Wan, Huang, and Stettner fail to disclose the following limitations:
The semiconductor device of claim 11, wherein the plurality of reset transistors, the plurality of source followers, the plurality of row selectors, and the plurality of input/output transistors are formed with a first dimension, and the plurality of logic transistors are formed with a second dimension, and wherein the first dimension is substantially greater than the second dimension.
Takashima discloses the following limitations:
The semiconductor device of claim 11, wherein the plurality of input/output transistors are formed with a first dimension, and the plurality of logic transistors are formed with a second dimension, and wherein the first dimension is substantially greater than the second dimension (Takashima discloses “A plurality of transistors each having a size smaller than that of the transistor of the input / output cell bulk 43 may be formed therein, and a logic circuit may be configured using these transistors“ where the differences in sizes is substantial or there would be no reduction in size of the logic array).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Takashima to the device of Wan, Huang, and Stettner. Doing so would desirably allow the size of the logic circuit to be reduced or allow more transistors to be included in the logic devices.
Wan, Huang, Stettner, and Takashima fail to disclose the following limitations:
wherein the plurality of reset transistors, the plurality of source followers, the plurality of row selectors are formed with a first dimension, and the plurality of logic transistors are formed with a second dimension, and wherein the first dimension is substantially greater than the second dimension.
Mochizuki discloses the following limitations:
wherein the plurality of reset transistors, the plurality of source followers, the plurality of row selectors are formed with a first dimension, and the plurality of logic transistors are formed with a second dimension, and wherein the first dimension is substantially greater than the second dimension (Mochizuki discloses “the processing size of the transistor in the pixel portion is made smaller than that in the peripheral drive circuit portion” where the difference in size is substantial because it allows for a higher resolution imaging device).
It would have been obvious to one of ordinary skill in the art at the time of the effective filling date to have applied the teachings of Mochizuki to the device of Wan, Huang, and Takashima. Doing so would allow more pixels to be fabricated in the same area, and therefore allow for higher resolution of the image device.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wan, Huang, Stettner, and Lee as applied to claim 12 above, and further in view of Chen, US 20050275449 A1, hereafter Chen.
Regarding claim 13, Wan, Huang, Stettner, and Lee fail to disclose the following limitations:
The semiconductor device of claim 12, wherein the first supply voltage is greater than about 2 volts, and the second supply voltage is less than 2 volts.
Chen discloses the following limitation:
wherein the first supply voltage is greater than about 2 volts (Chen, [0003] high voltage for circuit components disclosed as 3.3V), and the second supply voltage is less than 2 volts (Chen discloses [0003] that low voltage is disclosed as 1.8V).
It would have been obvious ton one of ordinary skill in the art at the time of the effective filing date of the invention to have applied the teachings of Chen to the device of Wan, Huang, Stettner, and Lee because Chen teaches that using low voltage transistors are typically less expensive then high voltage transistors making it desirable to use them whenever possible (Chen, [0003]).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s argument that the limitations that the input/output circuits be collectively disposed along a plurality of edge of the array (or substrate) are not persuasive in view of the modifications to the rejections which address this limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wadsworth, US 20140097329 A1, discloses an array surrounded by column amplifier and column and row scanner.
Azuhata, US 20260089405 A1, discloses a three layer imaging element.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LINDA J FLECK whose telephone number is (703)756-1253. The examiner can normally be reached 10-2 ET.
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/LINDA J. FLECK/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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