DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/3/2025 has been entered.
Status of the claims
Claims 1-14, 21-23 and 25-27 are pending in this application.
Prior rejections of Claims 21-23, and 25-27 under 35 U.S.C. 112(b), are withdrawn in view of applicant’s amendment to claim 21.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation “a first sidewall” in line 2 and “a second side wall” in line 3. There is insufficient antecedent basis for this limitation in the claim. “A first sidewall” and “a second wall” have already been defined in claim 1, from which claim 8 depends on. It is not clear if the applicant is redefining new sidewalls or referring to the sidewalls in claim 1. Thus claim 8 is indefinite and rejected. For examining purposes, “a first sidewall” in line 2 will be treated as “a third sidewall”, “a second side wall” in line 3 will be treated as “a fourth sidewall”, “the first sidewall” in line 4 will be treated as “the third sidewall”, and “the second sidewall” in line 5 will be treated as “the fourth sidewall”.
Claim 9 depends from claim 8 and inherit the same indefiniteness and hence rejected. For examining purposes, “the second sidewall” in line 2 will be treated as “the fourth sidewall”.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 21-23 and 25-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (US 2019/0067120 A1, hereinafter “Ching’120”, of record).
Re Claim 21, Ching’120 teaches a method for manufacturing an integrated circuit device, comprising:
forming a semiconductor structure (204a, Fig. 9A, para [0087]) over a substrate (202, Fig. 9A, para [0087]);
forming a first dielectric isolation structure (206, Fig. 9A, para [0088]) over the substrate (202) and laterally surrounding (see Figs. 9A/B/C) the semiconductor structure (204a);
patterning the semiconductor structure to form a trench (opening in 204a where1604a will be formed, Fig. 10A, paras [0090] - [0092]) in the semiconductor structure (204a), wherein the trench exposes the first dielectric isolation structure (isolation structure 206 will be exposed when the opening in 204a is formed, see Fig. 10A);
forming a second dielectric isolation structure in the trench (1604a, Figs. 10A-10C, para [0092]) and in contact with the first dielectric isolation structure (206), wherein a first sidewall of the second dielectric isolation structure is in contact with the semiconductor structure (sidewall of 1604a touching 204a, marked “sidewall-1” in annotated Figs. 11A and 11C below);
etching the first dielectric isolation structure (206 can be pulled back by an etching process, see para [0094]) to expose a second sidewall of the second dielectric isolation structure (exposed sidewall of 1604a see Fig. 11A, also marked “sidewall-2” in annotated Figs. 11A and 11C below) after forming the second dielectric isolation structure (1604a); and
forming a metal gate structure (2nd metal gate structure from the left-hand-side in Fig. 13C, also marked as “2nd metal gate structure” in annotated Fig. 13C below, 1002+1108+1106, paras [0075] - [0076], also see Figs. 11C and 12C) across the semiconductor structure (204a) and the second dielectric isolation structure (1604a), wherein a portion of a gate metal layer of the metal gate structure (gate metal 1108 of “2nd metal gate structure”) is on the first sidewall of the second dielectric isolation structure (“2nd metal gate structure” is formed on the intersection of dielectric fin 1604a and semiconductor structure 204a, hence formed on the first sidewall, “sidewall-1” of the dielectric fin 1604a, compare annotated Fig. 13C with Figs. 11C and 12C below).
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Re Claim 22, Ching’120 teaches the method of claim 21, wherein the metal gate structure (2nd metal gate structure) is in contact with the first and the second sidewall of the second dielectric isolation structure (2nd metal gate structure is in contact with both “sidewall-1” and “sidewall-2” of 1604a, see annotated Figs. 11C, 12C and 13C above).
Re Claim 23, Ching’120 teaches the method of claim 21, wherein the first dielectric isolation structure (206 can be made of dielectric material like silicon oxide, para [0088]) and the second dielectric isolation structure have different materials (1604a can be SiOCN, para [0092]).
Re Claim 25, Ching’120 teaches the method of claim 21, wherein a first portion of the metal gate structure (“2nd metal gate structure”) stands on the semiconductor structure (204a, see claim 21 and annotated Figs. 12C and 13C above), a second portion of the metal gate structure stands on the second dielectric isolation structure (1604a, see claim 21 and annotated Figs. 12C and 13C above), and a third portion of the metal gate structure stands on the first dielectric isolation structure (206, see annotated Figs. 12C and 13C above).
Re Claim 26, Ching’120 teaches the method of claim 21, wherein a width of the second dielectric isolation structure (1604a) is substantially the same as a width of the semiconductor structure (width of 1604a and 204a are substantially same, see Fig. 10C).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-9 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 2019/0067120 A1, hereinafter “Ching’120”, of record), and further in view of Ching et al. (US 2019/0165094 A1, hereinafter “Ching’094”, of record).
Re Claim 1, Ching’120 teaches a method for manufacturing an integrated circuit device, comprising:
forming a semiconductor fin (204a, Fig. 9A, para [0087]) over a semiconductor substrate (202, Fig. 9A, para [0087]);
forming an isolation structure (206, Fig. 9A, para [0088]) surrounding the semiconductor fin (204a);
etching a trench (opening in 204a where1604a will be formed, Fig. 10A, paras [0090] - [0092]) in the semiconductor fin (204a);
forming a dielectric fin in the trench (1604a, Figs. 10A-10C, para [0092]), and the dielectric fin has a first sidewall in contact with the isolation structure (sidewall of 1604a touching 206, see Figs. 10A-10C) and a second sidewall in contact with the semiconductor fin (sidewall of 1604a touching 204a, see Figs. 10A and 11A);
after forming the dielectric fin (1604a), recessing a top surface of the isolation structure (206 can be pulled back by an etching process, see para [0094]), such that the dielectric fin (1604a) and the semiconductor fin (204a) protrude from the recessed top surface of the isolation structure (see Fig. 11A); and
forming a first metal gate structure (marked “1st metal gate structure” in annotated Fig. 13C below, 1002+1108+1106, paras [0075] - [0076], also see Figs. 11C and 12C) and a second metal gate structure (marked “2nd metal gate structure” in annotated Fig. 13C below, 1002+1108+1106, paras [0075] - [0076], also see Figs. 11C and 12C) across the semiconductor fin (204a) and the dielectric fin (1604a), respectively, wherein a portion of a gate metal layer of the second metal gate structure (gate metal 1108 of “2nd metal gate structure”) is on the second sidewall of the dielectric fin (“2nd metal gate structure” is formed on the intersection of dielectric fin 1604a and semiconductor fin 204a, hence formed on the second sidewall of the dielectric fin, which is the sidewall of 1604a touching 204a, compare Fig. 13C with Figs. 11C and 12C).
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Ching’120 does not explicitly show that the bottom surface of the dielectric fin is level with a bottom surface of the isolation structure.
However, in a related semiconductor art Ching’094 discloses a dielectric fin 510 (Figs. 5A-5B, para [0033]) formed in the trenches (312, Figs. 5A-5B, para [0033]) between two adjacent semiconductor fins (310, Figs. 5A-5B, para [0031]), such that the bottom surface of the dielectric fin 510 is at the same level as the bottom surface of the isolation structure 610 (compare Figs. 5B and 6, para [0034]). The dielectric fins provide complete isolation and end-to-end spacings between two adjacent semiconductor fins along the fin-direction (para [0031]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor device of Ching’120, such that the bottom surface of the dielectric fin is at the same level as the bottom surface of the isolation structure, as disclosed by Ching’094, because the modified dielectric fins will provide complete isolation and end-to-end spacings between two adjacent semiconductor fins along the fin-direction (para [0031], Ching’094).
Re Claim 2, Ching’120 modified by Ching’094 teaches the method of claim 1, wherein etching the trench (opening in 204a where1604a will be formed, Fig. 10A, paras [0090] - [0092], Ching’120) in the semiconductor fin (204a, Ching’120) is performed such that the trench exposes a sidewall of the isolation structure (opening in 204a will expose the sidewall of the isolation structure 206, Fig. 10A, paras [0090] - [0092], Ching’120).
Re Claim 3, Ching’120 modified by Ching’094 teaches the method of claim 1, wherein etching the trench (opening in 204a where the dielectric fin 1604a will be formed, Ching’120) is performed such that a bottom of the trench is lower than the top surface of the isolation structure (The bottom of the trench, and hence the bottom surface of the dielectric fin, are at the same level as the bottom surface of the isolation structure, Ching’120 modified by Ching’094, see Claim 1 rejection. Thus, the bottom of the trench, opening in 204a, is lower than the top surface of the isolation structure, 206).
Re Claim 4, Ching’120 modified by Ching’094 teaches the method of claim 1, wherein forming the dielectric fin (1604a, Ching’120) comprises:
filling the trench (opening in 204a where1604a will be formed) with a dielectric material (para [0092]); and
planarizing a top surface of the dielectric material with the top surface of the semiconductor fin (planarization processes was carried out such that the upper surfaces of dielectric fins 1604a-1604f, semiconductor fins 204a-204f, and isolation structures 206 are substantially coplanar, para [0094]).
Re Claim 5, Ching’120 modified by Ching’094 teaches the method of claim 4, wherein planarizing the top surface of the dielectric material is performed such that the top surface of the dielectric fin, the top surface of the semiconductor fin, and the top surface of the isolation structure are planarized (planarization processes was carried out such that the upper surfaces of dielectric fins 1604a-1604f, semiconductor fins 204a-204f, and isolation structures 206 are substantially coplanar, para [0094], Ching’120).
Re Claim 6, Ching’120 modified by Ching’094 teaches the method of claim 1, wherein the dielectric fin (1604a) comprises a material (1604a can be SiOCN, para [0092]) different from that of the isolation structure (isolation structure 206 can be made of dielectric material like silicon oxide, para [0088]).
Re Claim 7, Ching’120 modified by Ching’094 teaches the method of claim 1, wherein the dielectric fin (1604a) comprises SiOCN (1604a can be SiOCN, para [0092]).
Re Claim 8, Ching’120 modified by Ching’094 teaches the method of claim 1, wherein forming the isolation structure (206, Ching’120) is performed such that the isolation structure (206) is in contact with a third sidewall (marked “Sidewall3” in annotated Figs. 10B and 10C below, Ching’120) of the semiconductor fin (204a, Ching’120), and etching the trench (opening in 204a where1604a will be formed) is performed such that a fourth sidewall (marked “Sidewall4” in annotated Fig. 10C below in a top view, Ching’120) of the semiconductor fin (204a) is exposed (sidewall4 will be exposed when the opening in 204a is formed and before the formation of the dielectric fin 1604a), and the third sidewall (Sidewall3) of the semiconductor fin (204a) is longer than the fourth sidewall (Sidewall4) of the semiconductor fin (204a) from a top view (see annotated Fig. 10C below).
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Re Claim 9, Ching’120 modified by Ching’094 teaches the method of claim 8, wherein forming the dielectric fin (1604a, Ching’120) is performed such that the dielectric fin (1604a) is in contact with the fourth sidewall (sidewall4, see annotated Fig. 10C above) of the semiconductor fin (204a, Ching’120).
Re Claim 27, Ching’120 teaches the method of claim 21, but does not disclose that a bottom surface of the second dielectric isolation structure is coplanar with a bottom surface of the first dielectric isolation structure.
However, in a related semiconductor art Ching’094 discloses a dielectric fin 510 (Figs. 5A-5B, para [0033]) formed in the trenches (312, Figs. 5A-5B, para [0033]) between two adjacent semiconductor fins (310, Figs. 5A-5B, para [0031]), such that the bottom surface of the dielectric fin 510 is coplanar with the bottom surface of the isolation structure 610 (compare Figs. 5B and 6, para [0034]). The dielectric fins provide complete isolation and end-to-end spacings between two adjacent semiconductor fins along the fin-direction (para [0031]).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the semiconductor device of Ching’120, such that the bottom surface of the dielectric fin is coplanar with the bottom surface of the isolation structure, as disclosed by Ching’094, because the modified dielectric fins will provide complete isolation and end-to-end spacings between two adjacent semiconductor fins along the fin-direction (para [0031], Ching’094).
Allowable Subject Matter
Claims 10-14 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 10 is allowable for at least the following reasons. Most of the limitation of claim 10 are taught by Ching et al. (US 2019/0067120 A1, hereinafter “Ching’120”, of record) and further in view of Ching et al. (US 2017/0154973 A1, hereinafter “Ching’973”, of record), as explained in the last Office Action dated 8/15/2025. Ching’973 also teaches the newly added limitation wherein, “recessing the first semiconductor layers (314, Figs. 13B-13C, para [0057]) to form recesses (830, Figs. 13B-13C, para [0057]) between the second semiconductor layers (316, Figs. 13B-13C, para [0057]) and forming inner spacers (840, Figs. 13B-13C, para [0057]) in the recesses”. Ching’120 teaches the newly added limitation wherein, “forming a first metal gate structure across a boundary between the dielectric fin and the semiconductor fin and surrounding the second semiconductor layers (see rejection of claim 1 above)”. However, in the Examiner’s opinion, the newly added limitation, “wherein a portion of a gate metal layer of the first metal gate structure is sandwiched between the dielectric fin and one of the inner spacers”, is neither anticipated nor made obvious by the prior art of record, when viewed in the context of the whole claim.
Claims 11-14 depend from claim 10 and are allowable for at least the reasons above.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 1 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/P.D./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898