DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on December 26, 2025 has been entered.
Claim Rejections - 35 USC § 112
Claims 1-2, 4 and 6-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Specifically, claim 1 recites “a top surface” (third indented limitation), “an upper surface” (seventh indented limitation), and “the surface” (eighth indented limitation) in reference to the copper conductive pillar which creates a lack of clarity as to which surfaces are being referenced. Further, claim 1 recites “the remaining insulating layer” which lacks antecedent basis and clarity as to which portion of the insulating layer is being referenced. Claim 7 recites “a top surface” (sixth indented limitation) and “an upper surface” (seventh indented limitation) in reference to the copper conductive pillar which creates a lack of clarity as to which surfaces are being referenced. Claim 11 recites “a top surface” (fourth indented limitation) and “an upper surface” (fourth indented limitation) in reference to the copper conductive pillar which creates a lack of clarity as to which surfaces are being referenced. Claims 2, 4, 6 and 8-10 depend from claims 1 and 7, respectively, and so are similarly rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s admitted prior art (hereinafter “AAPA” – previously cited reference) and further in view of US 2016/0297674 A1 to Man et al. (hereinafter “Man” – previously cited reference).
Regarding claim 11, as best understood, AAPA discloses a semiconductor packaging structure, comprising an adapter board for packaging (adapter board for packaging of semiconductor device; paragraphs [0003]-[0005]), wherein the adapter board for packaging comprises:
a separation layer on a support substrate (separation layer 102 on substrate 101 as shown in Fig. 1; paragraph [0006]);
the support substrate bonded to a top surface of the separation layer and a silicon substrate bonded to a bottom surface of the separation layer respectively (support substrate 101 is bonded to top surface of separation layer 102 and silicon substrate 103 bonded to bottom surface of separation layer 102 as shown in Fig. 1; paragraph [0006]);
a TSV disposed vertically in the silicon substrate (exemplary TSV 104 extending vertically is formed in the silicon substrate 103; Fig. 1; paragraph [0006]);
a copper conductive pillar, filling the TSV, wherein a protective layer of material fills the recess (TSV 104 is filled with a copper conductive pillar 105 and may have an insulating layer material 107 disposed within recesses between TSVs 104; Figs. 1 and 4; paragraphs [0006] and [0009]);
a diffusion barrier formed between the copper conductive pillar, the protective layer in the recess and side walls of the TSV, wherein the diffusion barrier wraps around the copper conductive pillar and the protective layer in the recess (a diffusion barrier layer 106 is formed between the copper conductive pillar 105, the insulating layer material 107 and the side walls of the TSV hole 104, where portions of diffusion barrier layer 106 are disposed around pillar 105 and material 107 in recess between TSVs 104; Fig. 1; paragraph [0006]), so copper particles in the copper conductive pillar do not diffuse into a surface of the silicon substrate under protection of the protective layer of material and the diffusion barrier (diffusion barrier layer 106 prevents diffusion of copper particles A of pillars 105 into surface of silicon substrate 103 disposed under insulating material layer 107; Figs. 1 and 5; paragraphs [0006], [0010]-[0011]); and
an insulating layer, formed on the surface of the silicon substrate and covering a circumference of the copper conductive pillar (insulating layer 108 disposed over top surface of stacked structure which includes filled vertical gaps, tops of sidewalls and silicon substrate 103 outside of TSV 104 as shown in Figs. 5 and 6; paragraphs [0010]-[0011]).
AAPA fails to disclose filling the TSV except leaving a recess on an upper surface above the copper conductive pillar.
However, Man discloses filling the TSV except leaving a recess on an upper surface above the copper conductive pillar (via 309 disposed within channel at bottom of silicon pit 307 comprises recess disposed above copper metal pad 305 stack; Figs. 3C, 3G; paragraphs [0038], [0041], [0043]).
AAPA and Man are both considered to be analogous to the claimed invention because they are in the same field of semiconductor packaging structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Man in order to potentially provide mechanical stress relief, contamination and corrosion prevention, electrical insulation, and improved planarity.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of US 2020/0090988 A1 to Peethala et al. (hereinafter ‘Peethala’ – previously cited reference) and US 2013/0134508 A1 to Oh et al. (hereinafter “Oh” – previously cited reference).
Regarding claim 7, as best understood, AAPA discloses an adapter board for packaging (adapter board for packaging; paragraph [0005]), comprising:
a separation layer (separation layer 102 as shown in Fig. 1; paragraph [0006]);
a support substrate bonded to a top surface and a silicon substrate bonded to a bottom surface of the separation layer respectively (support substrate 101 is bonded to top surface of separation layer 102 and silicon substrate 103 bonded to bottom surface of separation layer 102 as shown in Fig. 1; paragraph [0006]);
a TSV, disposed vertically in the silicon substrate;
a copper conductive pillar, filling the TSV;
a diffusion barrier, disposed between the copper conductive pillar and side walls (exemplary TSV 104 extending vertically is formed in the silicon substrate 103, the TSV 104 is filled with a copper conductive pillar 105, and a diffusion barrier layer 106 is formed between the copper conductive pillar 105 and the side walls of the TSV hole 104; Fig. 1; paragraph [0006]);
a groove, disposed at one end of the copper conductive pillar (top surface of the silicon substrate 103 and copper particles A of the conductive pillar 105 are etched away to expose the copper conductive pillar 105 to a predetermined height forming grooves therebetween as shown in Fig. 4; paragraphs [0009] and [0040]);
a protective layer, filling in the groove (insulating material layer 107 deposited over top of stacked structure 100 which includes opening to vertical gaps as shown in Fig. 5; paragraphs [0010]-[0011]); and
an insulating layer, disposed on a top surface of the protective layer in the groove, a top surface of the sidewalls, and a top surface of the silicon substrate outside the TSV (insulating layer 108 disposed over top surface of stacked structure which includes filled vertical gaps, tops of sidewalls and silicon substrate 103 outside of TSV 104 as shown in Figs. 5 and 6; paragraphs [0010]-[0011]).
AAPA fails to disclose a groove, disposed at one end of the copper conductive pillar inside sidewalls of the diffusion barrier; and wherein an insulating layer disposed on a top surface of the sidewalls of the diffusion barrier.
However, Peethala discloses a groove, disposed at one end of the copper conductive pillar inside sidewalls of the diffusion barrier (semiconductor wafer having semi-liner interconnect structures where a conductive material fill layer 44 is partially etched away to form a conductive material recessed area 50 disposed within the sidewalls of a barrier layer 20 within the interconnect structure as shown in Figs. 7-8; paragraphs [0035]-[0037]).
AAPA and Peethala are both considered to be analogous to the claimed invention because they are in the same field of semiconductor fabrication. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Peethala in order to provide a better template for deposition of additional materials that potentially reduces voids or seam formation and which overall facilitates better process control while improving physical and electrical properties of the interconnects.
AAPA as modified still fails to disclose an insulating layer disposed on a top surface of the sidewalls of the diffusion barrier.
However, Oh discloses an insulating layer disposed on a top surface of the sidewalls of the diffusion barrier layer (insulation layer 27 disposed upon top of surface of sidewalls of diffusion barrier layer 23A as shown in Fig. 4A; paragraphs [0042]-[0043]).
AAPA and Oh are both considered to be analogous to the claimed invention because they are in the same field of semiconductor device fabrication. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Oh in order to potentially provide prevention of electrical shorting and enhanced dielectric isolation.
Regarding claim 9, AAPA in view of Peethala and Oh discloses the adapter board for packaging according to claim 7.
AAPA fails to disclose wherein the diffusion barrier layer comprises one or a stack of at least two of a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer.
However, Peethala discloses wherein the diffusion barrier layer comprises one or a stack of at least two of a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer (barrier layer 20 may utilize at least one of tantalum nitride, titanium nitride, silicon nitride and silicon oxynitride; paragraph [0025]).
AAPA and Peethala are both considered to be analogous to the claimed invention because they are in the same field of semiconductor fabrication. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Peethala in order to use compounds commonly used in the semiconductor fabrication process to create a barrier layer given the insulating nature of both silicon nitride and silicon oxynitride (see Peethala, paragraph [0025]).
Claims 8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of Peethala, Oh, and further in view of US 2019/0189577 A1 to Chen et al. (hereinafter “Chen” – previously cited reference).
Regarding claim 8, AAPA in view of Peethala and Oh discloses the adapter board for packaging according to claim 7. AAPA further discloses wherein the support substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate (support substrate 101 of stacked structure 100 for semiconductor device; paragraphs [0003]-[0006]).
AAPA as modified fails to disclose wherein the separation layer comprises a polymer layer or an adhesive layer.
However, Chen discloses wherein the separation layer comprises a polymer layer or an adhesive layer (temporary adhesive layer may be utilized to separate the first structure 10 to the carrier substrate; paragraph [0072]).
AAPA and Chen are both considered to be analogous to the claimed invention because they are in the same field of semiconductor device packaging. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Chen in order to use a well-known and widely available adhesive layer to temporarily adhere a semiconductor structure to a carrier substrate for enhanced process control during manufacture processes (see Chen, paragraph [0072]) to prevent the layers from unexpectedly separating.
Regarding claim 10, AAPA in view of Peethala and Oh discloses the adapter board for packaging according to claim 7.
AAPA as modified fails to disclose wherein the insulating layer comprises one or a stack of two of a silicon nitride layer and a silicon oxide layer.
However, Chen discloses wherein the insulating layer comprises one or a stack of two of a silicon nitride layer and a silicon oxide layer (dielectric layer 120 may be made from silicon oxide and silicon nitride; paragraph [0025]).
AAPA and Chen are both considered to be analogous to the claimed invention because they are in the same field of semiconductor device packaging. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified AAPA to incorporate the teaching of Chen in order to use compounds commonly used in the semiconductor fabrication process to create an insulating layer given the insulating nature of both silicon nitride and silicon oxide (see Chen, paragraph [0072]).
Allowable Subject Matter
Claims 1-2, 4 and 6, as best understood, appear to be allowable subject matter but for the 35 USC 112(b) rejections of claim 1. Examiner notes that amendments made to claim 1 to overcome this rejection may change the scope thereof, which would require a further allowability determination.
Response to Arguments
Applicant's arguments filed December 26, 2025 have been fully considered. Applicant amends claims 1, 7 and 11 and presents corresponding arguments related to the amendments made to claim 1 solely. Examiner agrees, as noted above, that claim 1, as best understood, appears to be allowable subject matter, but will require a further allowability determination once amendments are made to claim 1 to overcome the 35 USC 112(b) rejection. Applicant again states that claims 7 and 11 have been amended in a similar manner to claim 1 but this is not correct and as evidenced by Applicant’s listed amendments. Also, Applicant continues to make errors in the formatting of their amendments. For example, the last indented limitation of claim 1 fails to underline ‘keep’ in the amendment of adding the phrase “keep the remaining” in line 3 of that limitation. Examiner requests that Applicant follow MPEP formatting guidelines when making future amendments to expedite prosecution and avoid procedural rejections related to submissions of non-compliant amendments.
Conclusion
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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