Prosecution Insights
Last updated: July 17, 2026
Application No. 17/852,768

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Non-Final OA §103§112
Filed
Jun 29, 2022
Examiner
HUNTER III, CARNELL
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
2 (Non-Final)
91%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
63 granted / 69 resolved
+23.3% vs TC avg
Strong +16% interview lift
Without
With
+16.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
21 currently pending
Career history
92
Total Applications
across all art units

Statute-Specific Performance

§103
78.7%
+38.7% vs TC avg
§102
8.3%
-31.7% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 69 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The previously issued claim objections are hereby withdrawn in view of the amended claims. Applicant’s arguments with respect to claim(s) 1, 10, and 21 have been considered but are moot in view of new grounds of rejection. The instant Non-Final Rejection replaces the previous Non-Final Rejection mailed on 12/18/2025. Claim Rejections - 35 U.S.C. § 112(b) The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 25 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 25, it is unclear how a top surface of the epitaxial sacrificial structure 136 is higher than a top surface of the second S/D contact structure 187. Independent claim 21 states that the top portion of the second S/D contact structure is wider than the bottom portion of the second S/D contact structure. The top surface of the second S/D contact structure would be located on the top portion i.e. wider side of the second S/D contact structure, and Figs. 2M, 3, 4, and 5 fail to support the previously mentioned claim language. No prior art has been applied due to the uncertainty. Claim Rejections - 35 U.S.C. § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-6 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. (US 2021/0391421 A1), hereafter “Chu”, in view of Wang et al. (US 2021/0083114 A1), hereafter “Wang”, and further in view of Wang et al. (US 2020/0168742 A1), hereafter “Wang ‘742”. As to claim 1, Chu teaches a semiconductor structure, comprising: a plurality of nanostructures (⁋ [0010], “nanosheet FETs, nanowire FETs”; ⁋ [0012], 215) surrounded by a gate structure (Fig. 13C, 240’, ⁋ [0036]); a source/drain (S/D) structure (Fig. 13B, 260, ⁋ [0030]) adjacent to the gate structure; a first S/D contact structure (Fig. 14B, ⁋ [0041], 275) formed over a first side of the S/D structure; a second S/D contact structure (Fig. 20B, ⁋⁋ [0028], [0049], 282) formed over a second side of the S/D structure, wherein the second S/D contact structure comprises a conductive layer (⁋ [0049], 282, “via or metal plug”); and a dielectric layer (⁋ [0011], 230) adjacent to the second S/D contact structure (Fig. 20C). Chu fails to teach wherein the dielectric layer is doped with germanium (Ge); and an epitaxial sacrificial structure formed adjacent to the gate structure, wherein the epitaxial sacrificial structure is separated from the second S/D contact structure by the dielectric layer. Wang teaches a semiconductor structure with a dielectric layer (Fig. 7, ⁋ [0022], 222) adjacent to a s/d contact structure (⁋ [0025], 238), wherein the dielectric layer is doped with germanium (⁋ [0031], “In some examples, the dopant particles include elements such as germanium”) It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize germanium dopants in an insulator material as taught by Wang to merge portions of the ILD layer with sidewall portions of the S/D contact (⁋ [0029]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Chu modified by Wang fails to teach an epitaxial sacrificial structure formed adjacent to the gate structure, wherein the epitaxial sacrificial structure is separated from the second S/D contact structure by the dielectric layer. Wang ‘742 teaches a similar semiconductor structure with an epitaxial sacrificial structure (⁋ [0033], Figs. 6A-6B, 240) formed adjacent to a gate structure (⁋ [0016], 210). It would have been obvious to one having ordinary skill in the art at the time the invention was made to apply the teaching of the epitaxial sacrificial structure as taught by Wang ‘742 into the device of Chu and Wang for the benefit of achieving better different oxidation rates and/or different etch selectivity (⁋ [0034]). The combination of Chu modified by Wang and Wang ‘742 teaches the limitation wherein the epitaxial sacrificial structure of Wang ‘742 (240) is separated from the second S/D contact structure of Chu (282) by Chu’s dielectric layer (230). As to claim 2, Chu in view of Wang and Wang ‘742 teach wherein the second S/D contact structure comprises a silicide layer (⁋ [0049], 280, Fig. 20B) formed on the S/D structure, and a first liner layer (Fig. 4C, 229/232, ⁋ [0019]) adjacent to the silicide layer (280) (Fig. 20C). As to claim 3, Chu in view of Wang and Wang ‘742 teach further comprising: a second liner layer (Fig. 20D, ⁋ [0047], 274) adjacent to the first liner layer (229/232), wherein a top surface of the second liner layer is higher than a top surface of the first liner layer (top of 274 is higher than 229/232 in Fig. 20D). As to claim 4, Chu in view of Wang and Wang ‘742 fails to explicitly teach wherein the second liner layer is doped with germanium (Ge). Wang teaches a semiconductor structure with a dielectric layer (Fig. 7, ⁋ [0022], 222) adjacent to a s/d contact structure (⁋ [0025], 238), wherein the dielectric layer is doped with germanium (⁋ [0031], “In some examples, the dopant particles include elements such as germanium”). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize germanium dopants in an insulator material as taught by Wang to merge portions of second liner layer with sidewalls of adjacent portions (⁋ [0029]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. As to claim 5, Chu in view of Wang and Wang ‘742 teach further comprising: a filling layer (⁋ [0047], 276, Fig. 20B) formed over the second liner layer (274). Chu in view of Wang fail to teach explicitly teach wherein the filling layer is doped with germanium (Ge). Wang teaches a semiconductor structure with a dielectric layer (Fig. 7, ⁋ [0022], 222) adjacent to a s/d contact structure (⁋ [0025], 238), wherein the dielectric layer is doped with germanium (⁋ [0031], “In some examples, the dopant particles include elements such as germanium”). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize germanium dopants in a dielectric material as taught by Wang to merge portions of the filling layer with adjacent sidewall portions (⁋ [0029]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. As to claim 6, Chu in view of Wang and Wang ‘742 teach wherein the filling layer is further doped with fluorine (F) (⁋ [0047], “fluoride-doped silica glass”) or carbon (C) or carbon (C). As to claim 29, Chu in view of Wang and Wang ‘742 teach the semiconductor structure as claimed in claim 1, but fail to teach wherein the second S/D contact structure comprises a T-shaped like structure. On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Chu in view of Wang, Wang ‘742, and further in view of Chu et al. (US 2021/0376093 A1), hereafter “Chu ‘093”. As to claim 28, Chu in view of Wang and Wang ‘742 fail to teach further comprising: a filling layer between the second S/D contact structure and the epitaxial sacrificial structure. Chu ‘093 teaches a similar device with a filling layer (⁋ [0037], Fig. 15A, 270) that is located over the drain features (⁋ [0029], 246D). It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the filling layer as taught by Chu into the device of Chu, Wang and Wang ‘742 to enable self-alignment of backside source contact openings and backside source contacts (⁋ [0037]). As a result of the combination, the remaining limitation of the filling layer taught by Chu ‘093 being located between the second S/D contact structure of Chu and the epitaxial sacrificial structure of Wang ‘742 is taught. Claims 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chu in view of Wang, Wang ‘742, and further in view of Huang et al. (US 2021/0375857 A1), hereafter “Huang”. As to claim 7, Chu in view of Wang and Wang ‘742 fail to teach further comprising: an isolation layer below the epitaxial sacrificial structure. Huang teaches a similar semiconductor structure with an isolation layer (Fig. 14B, ⁋ [0035], 230) located below a sacrificial epitaxial plug i.e. structure (220). It would have been obvious to one having ordinary skill in the art at the time the invention was made to apply the teaching of the isolation layer as taught by Huang into the device of Chu, Wang and Wang ‘742 because the isolation layers are benefit for reducing current leakage from top epitaxial structures to the substrate (⁋ [0035]). As to claim 8, Chu in view of Wang, Wang ‘742 and Huang teach the semiconductor structure as claimed in claim 7, Chu teaches further comprising: an inner spacer (⁋ [0025], 255, Fig. 6B) formed adjacent to the nanostructures, wherein the inner spacer of Chu is in direct contact with Huang’s isolation layer (230) (see Huang’s Fig. 14B for the location of 230). As to claim 9, Chu in view of Wang, Wang ‘742 and Huang teach the semiconductor structure as claimed in 7, Wang ‘742 further teaches wherein the epitaxial sacrificial structure is doped with fluorine (F) or carbon (C) (⁋ [0033]). Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Chu in view of Wang, and Huang. As to claim 10, Chu teaches a semiconductor structure, comprising: a plurality of nanostructures (⁋ [0010], “nanosheet FETs, nanowire FETs”; ⁋ [0012], 215) surrounded by a gate structure (Fig. 13C, 240’, ⁋ [0036]); an inner spacer (⁋ [0025], 255, Fig. 6B) adjacent to the nanostructures; a source/drain (S/D) structure (Fig. 13B, 260, ⁋ [0030]) adjacent to the gate structure; a first S/D contact structure (⁋ [0041], 275) formed over a first side of the first S/D structure; and a second S/D contact structure (Fig. 20B, ⁋⁋ [0028], [0049], 282+280) formed over a second side of the S/D structure, wherein the second S/D contact structure comprises a conductive layer (⁋ [0028], 282) and a first liner layer (Fig. 20D, ⁋ [0047], 274), and the first liner layer is between the inner spacer and the conductive layer (Fig. 20B shows 274 between 282 and 255). Chu fails to teach wherein the first liner layer is doped with germanium (Ge); an epitaxial sacrificial structure formed adjacent to the gate structure; and an isolation layer below the epitaxial sacrificial structure. Wang teaches a semiconductor structure with a dielectric layer (Fig. 7, ⁋ [0022], 222) adjacent to a s/d contact structure (⁋ [0025], 238), wherein the dielectric layer is doped with germanium (⁋ [0031], “In some examples, the dopant particles include elements such as germanium”). Examiner notes that the first liner layer of Chu (274) is described as a dielectric liner (⁋ [0047]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize germanium dopants in a dielectric material as taught by Wang to merge portions of the first liner layer with sidewall portions of the S/D contact (⁋ [0029]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Chu and Wang fail to teach an epitaxial sacrificial structure formed adjacent to the gate structure; and an isolation layer below the epitaxial sacrificial structure. Huang teaches a similar semiconductor structure with an epitaxial sacrificial structure (⁋ [0034], Fig. 14B, 220) formed adjacent to a gate structure (⁋ [0028], Fig. 5, 180) and an isolation layer (Fig. 14B, ⁋ [0035], 230) located below a sacrificial epitaxial plug i.e. structure (220). It would have been obvious to one having ordinary skill in the art at the time the invention was made to apply the teaching of the isolation layer as taught by Huang into the device of Chu and Wang because the isolation layers are benefit for reducing current leakage from top epitaxial structures to the substrate (⁋ [0035]). Additionally, it would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of the sacrificial epitaxial plug taught by Huang into the device of Chu and Wang for the benefit of the different etch selectivity between the sacrificial epitaxial plug and the substrate (⁋ [0034]. This allows for thinning the substrate, for removal, from the backside (⁋ [0050]), therefore facilitating the manufacturing of components on the backside of the device. As to claim 11, Chu in view of Wang and Huang teach further comprising: a dielectric layer (⁋ [0011], 230) adjacent to the second S/D contact structure, wherein the conductive layer (282) is in direct contact with dielectric layer (Fig. 20B). As to claim 12, Chu in view of Wang and Huang teach further comprising: a second liner layer (Fig. 4C, 229/232, ⁋ [0019]) adjacent to the first liner layer. Chu and Wang fail to teach wherein the second liner layer is doped with germanium (Ge). Wang teaches a semiconductor structure with a dielectric layer (Fig. 7, ⁋ [0022], 222) adjacent to a s/d contact structure (⁋ [0025], 238), wherein the dielectric layer is doped with germanium (⁋ [0031], “In some examples, the dopant particles include elements such as germanium”). Examiner notes that the second liner layer of Chu (232) is described as a dielectric liner (⁋ [0047]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize germanium dopants in a dielectric material as taught by Wang to merge portions of the second liner layer with adjacent sidewall portions (⁋ [0029]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Claims 21, 23-24, and 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chu in view of Wang, and further in view of Guler et al. (US 2026/0143748 A1), hereafter “Guler”. As to claim 21, Chu teaches a semiconductor structure, comprising: a plurality of nanostructures (⁋ [0010], “nanosheet FETs, nanowire FETs”; ⁋ [0012], 215) surrounded by a gate structure (Fig. 13C, 240’, ⁋ [0036]); a source/drain (S/D) structure (Fig. 13B, 260, ⁋ [0030]) adjacent to the gate structure; a first S/D contact structure (⁋ [0041], 275) formed over a first side of the S/D structure; a second S/D contact structure (Fig. 20B, ⁋⁋ [0028], [0049], 282+280) formed over a second side of the S/D structure, wherein the second S/D contact structure has a top portion and a bottom portion, wherein the top portion is wider than the bottom portion (Fig. 20C shows 282 with a top and bottom portion, and the top portion is wider), wherein the second S/D contact structure comprises a conductive layer (⁋ [0049], 282, “via or metal plug”), a dielectric layer (⁋ [0011], 230) adjacent to the second S/D contact structure; and a filling layer (⁋ [0047], 276, Fig. 20B) adjacent to the second S/D contact structure (282+280) and below the dielectric layer (230) (Fig. 20E). Chu fails to teach wherein the conductive layer is doped with germanium (Ge); wherein the dielectric layer is doped with germanium (Ge), and wherein the filling layer is doped with germanium (Ge). Wang teaches a semiconductor structure with a dielectric layer (Fig. 7, ⁋ [0022], 222) adjacent to a s/d contact structure (⁋ [0025], 238), wherein the dielectric layer is doped with germanium (⁋ [0031], “In some examples, the dopant particles include elements such as germanium”). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize germanium dopants in a dielectric material as taught by Wang to merge portions of the first liner layer and filling layer with sidewall portions of the S/D contact (⁋ [0029]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Chu in view of Wang fail to teach wherein the conductive layer is doped with germanium (Ge). Guler teaches a semiconductor device in a similar field of endeavor and teaches a conductive later (⁋ [0112], 420) doped with Ge (e.g. Ge). It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of a doped conductive layer as taught by Guler into the device of Chu and Wang to enable robust contacts (⁋ [0112]). As to claim 23, Chu in view of Wang and Guler teach a filling layer (see claim 21) but fail to teach wherein the filling layer has a step-like structure. On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). As to claim 24, Chu in view of Wang and Guler teach wherein the filling layer is further doped with fluorine (F) (⁋ [0047], “fluoride-doped silica glass”) or carbon (C). As to claim 26, Chu in view of Wang and Guler teach further comprising: a liner layer (Fig. 20D, ⁋ [0047], 274) between the second S/D contact structure (280+282) and the filling layer (276). Chu in view of Wang fail to explicitly teach wherein the liner layer is doped with germanium (Ge). Wang teaches a semiconductor structure with a dielectric layer (Fig. 7, ⁋ [0022], 222) adjacent to a s/d contact structure (⁋ [0025], 238), wherein the dielectric layer is doped with germanium (⁋ [0031], “In some examples, the dopant particles include elements such as germanium”). Examiner notes that the first liner layer of Chu (274) is described as a dielectric liner (⁋ [0047]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize germanium dopants in a dielectric material as taught by Wang to merge portions of the first liner layer with sidewall portions of the S/D contact (⁋ [0029]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. As to claim 27, Chu in view of Wang and Guler teach further comprising: an inner spacer (⁋ [0025], 255, Fig. 6B) adjacent to the nanostructures; and a liner layer (Fig. 20B, ⁋ [0047], 274) between the inner spacer and the second S/D contact structure. Chu in view of Wang fail to explicitly teach wherein the liner layer is doped with germanium (Ge). Wang, however, does teach a semiconductor structure with a dielectric layer (Fig. 7, ⁋ [0022], 222) adjacent to a s/d contact structure (⁋ [0025], 238), wherein the dielectric layer is doped with germanium (⁋ [0031], “In some examples, the dopant particles include elements such as germanium”). Examiner notes that the first liner layer of Chu (274) is described as a dielectric liner (⁋ [0047]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to utilize germanium dopants in a dielectric material as taught by Wang to merge portions of the first liner layer with sidewall portions of the S/D contact (⁋ [0029]), since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARNELL HUNTER whose telephone number is (571)270-1796. The examiner can normally be reached Monday - Friday 7:30 am - 4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CARNELL HUNTER III/Examiner, Art Unit 2893 /SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Jun 29, 2022
Application Filed
Dec 18, 2025
Non-Final Rejection mailed — §103, §112
Mar 16, 2026
Response Filed
Jun 05, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

2-3
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+16.1%)
3y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
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