DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claims 1 and 10 are amended in the communication filed by the applicant on 18 November 2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220051930 A1, hereinafter “Gupta”), in view of Kim et al (KR 20010105760 A, hereinafter “Kim”), and further in view of Sim et al (US 20120058639 A1, hereinafter “Sim”).
Regarding Claim 1 – Gupta discloses a method for manufacturing a semiconductor structure, comprising: providing a substrate (“The device structure 100 includes a first isolation material 102 overlying a base material (not shown).” as in Gupta [0028] regarding Figure 1A (same device 100 as in annotated Gupta Figure 1F below), and “base material” defined as substrate in [0026]); forming a word line (conductive structure 244 of tier 248 in Gupta Fig. 2; [0071}) over the substrate and extending parallel to the substrate along a first direction (considered as X in Gupta Fig. 2 and X-direction in [0080]); forming a first bit line (shown as “First Bit Line” in Annotated Gupta Fig. 1F; conductive lines 122 in [0046] or 222 in [0078]) over the word line (as shown in Gupta Fig. 2, where 222 is over 244) and extending parallel to the substrate along a second direction (considered as Y in Gupta Fig. 2; conductive lines 122 extending in Y-direction in [0048]) different from the first direction (as described in [0027]); forming a second bit line (“Second Bit Line” in Annotated Gupta Fig. 1F; conductive lines 122 in [0046] or 222 in [0078]) at the same level as the first bit line (as shown in Gupta Fig. 2, where 222 is over 244) and extending along the second direction (considered as Y in Gupta Fig. 2; conductive lines 122 extending in Y-direction in [0048]); and forming a dielectric layer over and between the first bit line and the second bit line (130 in Gupta Fig. 1F; over and on the sidewalls of conductive lines 122 [0053]), wherein an air gap is formed between the first bit line and the second bit line, and extending along the second direction (air gap 132 in Annotated Gupta Fig. 1F; formed in openings, 120, between conductive lines 122, extending in second direction [0055]);
Gupta fails to disclose the first bit line includes a metal layer, a metal nitride layer, an oxide layer and a nitride layer stacked in sequence over the substrate.
However, Kim discloses the first bit line includes a metal layer (“a lower Ti film” in 81a, Kim [11] and Fig. 2) a metal nitride layer (“an upper TiN film”, Kim [11] and Fig. 2), an oxide layer (90, Kim [6] and Fig. 2) and a nitride layer (91, Kim [6] and Fig. 2) stacked in sequence over the substrate (10, Kim [6] and Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Gupta, as taught by Kim. The ordinary artisan would have been motivated to modify Gupta in the above manner for purpose of preventing metal alloy distortion (Abstract of Kim).
Gupta modified by Kim fails to disclose a top level of the air gap is disposed between a top level of the nitride layer of the first bit line and a top level of the dielectric layer and a height of the air gap is greater than a height of the first bit line.
However, Sim discloses a top level of the air gap (160c, Sim [0056] and Fig. 2C) is disposed between a top level of the first bit line (150a, Sim [0056] and Fig. 2C) and a top level of the dielectric layer (155, Sim [0056] and Fig. 2C) and a height of the air gap is greater than a height of the first bit line (Sim [0056] and Fig. 2C).
Sim describes a conductive line structure for a memory device, similar to Gupta. Sim teaches air gaps may be formed taller than the bit lines to minimize parasitic capacitance between conductive patterns (Sim [0050]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form an air gap taller than the bit lines to achieve the benefit of reducing parasitic capacitance between conductive lines.
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Regarding Claim 2 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 1.
The combination of Gupta, Kim, and Sim further discloses forming an isolation (202 in Gupta Fig. 2; described in Gupta [0082]) between the first bit line (222 in Gupta Fig. 2; [0078]) and the word line (244 in Gupta Fig. 2; [0071]). (In Gupta [0082], isolation 202 is descried as being over the stack structure 242, which includes the word line 244, and below the second isolation 230. In Figure 2, it can be seen below conductive lines 222 as well.)
Regarding Claim 3 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 1.
The combination of Gupta, Kim, and Sim further discloses forming a first landing pad (114 under “First Bit Line” in Annotated Gupta Fig. 1F; [0036]) between the first bit line (“First Bit Line” in Annotated Gupta Fig. 1F; [0046]) and the word line (244 in Gupta Fig. 2; [0071]); and forming a second landing pad between the second bit line (“Second Bit Line” in Annotated Gupta Fig. 1F; [0046]) and the word line (244 in Gupta Fig. 2; [0071])(Second landing pad not shown, because it is in a different position in the Y-direction under “Second Bit Line” in Annotated Gupta Fig. 1F; described in Gupta [0036] and [0052]).
Regarding Claim 4 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 3.
The combination of Gupta, Kim, and Sim further discloses the air gap (132 in Annotated Gupta Fig. 1F); is disposed at least between the first landing pad (114 under “First” in Annotated Gupta Fig. 1F) and the second landing pad (Air gaps 132 extend downward to be adjacent to interconnect structures 114, as in Gupta [0054], and shown in Figure 1F).
Regarding Claim 5 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 1.
The combination of Gupta, Kim, and Sim further discloses the first direction (X in Gupta Fig. 1F and 2; X-direction in Gupta [0027]) is substantially perpendicular to the second direction (Y in Gupta Fig. 1F and 2; Y-direction in Gupta [0027]).
Regarding Claim 7 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 1.
The combination of Gupta, Kim, and Sim further discloses forming an isolation between the first bit line and the substrate, and between the second bit line and the substrate (In [Gupta 0082], isolation 202 is descried as being over the stack structure 242, which includes the word line 244, and below the second isolation 230. In Figure , it can be seen below conductive lines 222 as well.), wherein the air gap (132 in Annotated Gupta Fig. 1F; [0055]) is disposed at least between portions of the isolation (Air gaps 132 extend downward to be adjacent to segments of the isolation material 102, as in [0054], and shown in Figure 1F)
Regarding Claim 8 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 1.
The combination of Gupta, Kim, and Sim further discloses a thickness of a vertical portion of the dielectric layer on a sidewall ((W3-WM)/2 in Annotated Gupta Fig. 1F; [0066]) of the first bit line (“First” in Annotated Gupta Fig. 1F; [0046]) is less than a thickness of a horizontal portion of the dielectric layer on a top ((W3-WT)/2 in Annotated Gupta Fig. 1F; [0066]) of the first bit line (It can be seen in annotated Fig. 1F that (W3-WT)/2 > (W3-WM)/2, as the air gap is curved in cross section).
Regarding Claim 10 – Gupta discloses a method for manufacturing a semiconductor structure, comprising: forming a first bit line (“First Bit Line” in Annotated Gupta Fig. 1F; 122 in [0046]) and a second bit line (“Second Bit Line” in Annotated Gupta Fig. 1F; 122 in [0046]) over a substrate (“base material” in [0028], as defined in [0026])(The first isolation 102 overlies the substrate as in [0028], and the conductive lines 122 overlie the first isolation 102 as in [0046]); forming a first dielectric layer (130 in Gupta Fig. 1F; [0053]) conformally over the first bit line and the second bit line (as described in [0053]); and connecting a portion of the first dielectric layer over a top of the first bit line to an adjacent portion of the first dielectric layer over a top of the second bit line (the isolation material 130 covers the openings (between bit lines) and dielectric structures (top of each bit line stack), as described in [0053] and shown in Fig. 1F); wherein the connecting of the portion of the first dielectric layer over the top of the first bit line to the adjacent portion of the first dielectric layer over the top of the second bit line defines an air gap between the first bit line and the second bit line (enclosing air gap 132 at the top, as described in [0053] and shown in Fig. 1F).
Gupta fails to disclose the forming of the first bit line and the second bit line comprises: forming a metal layer over the substrate; forming a metal-containing layer over the metal layer; forming an oxygen-containing layer over the metal-containing layer; forming a hard layer over the oxygen-containing layer; and patterning the metal layer, the metal-containing layer, the oxygen-containing layer and the hard layer.
However, Kim discloses the forming of the first bit line and the second bit line comprises: forming a metal layer over the substrate (“a lower Ti film” in 81a, Kim [11] and Fig. 2); forming a metal-containing layer over the metal layer (“an upper TiN film”, Kim [11] and Fig. 2); forming an oxygen-containing layer over the metal-containing layer (90, Kim [6] and Fig. 2); forming a hard layer over the oxygen-containing layer (91, Kim [6] and Fig. 2); and patterning the metal layer, the metal-containing layer, the oxygen-containing layer and the hard layer (“pattern of the bit line 81”, Kim [11] and Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Gupta, as taught by Kim. The ordinary artisan would have been motivated to modify Gupta in the above manner for purpose of preventing metal alloy distortion (Abstract of Kim).
Gupta modified by Kim fails to disclose a top level of the air gap is disposed between a top level of the hard layer of the first bit line and a top level of the first dielectric layer, and a height of the air gap is greater than a height of the first bit line.
However, Sim discloses a top level of the air gap (160c, Sim [0056] and Fig. 2C) is disposed between a top level of the first bit line (150a, Sim [0056] and Fig. 2C) and a top level of the first dielectric layer (155, Sim [0056] and Fig. 2C), and a height of the air gap is greater than a height of the first bit line (Sim [0056] and Fig. 2C).
Sim describes a conductive line structure for a memory device, similar to Gupta. Sim teaches air gaps may be formed taller than the bit lines to minimize parasitic capacitance between conductive patterns (Sim [0050]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to form an air gap taller than the bit lines to achieve the benefit of reducing parasitic capacitance between conductive lines.
Regarding Claim 11 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 10.
The combination of Gupta, Kim, and Sim further discloses the forming of the first bit line and the second bit line comprises: forming a metal layer (116 of Gupta [0042], becoming 122 of Gupta Fig. 1F; [0049]) over the substrate (The first isolation 102 overlies the substrate as in Gupta [0028], and the conductive lines 122 overlie the first isolation 102 as in Gupta [0046]); forming a metal-containing layer (included in the “at least one electrically conductive material” 116 in Gupta [0042], becoming 122 of Gupta Fig. 1F) over the metal layer (116 of Gupta [0042], becoming 122 of Gupta Fig. 1F); forming an oxygen-containing layer (118 “may include at least one of … silicon dioxide…” in Gupta [0044], becoming 124 in Gupta Fig. 1F) over the metal-containing layer; forming a hard layer (118 in Gupta [0044] may include at least two materials, becoming 124 in Gupta Fig. 1F; hard mask in Gupta [0048]) over the oxygen-containing layer; and patterning the metal layer, the metal-containing layer, the oxygen-containing layer and the hard layer (device patterned to create openings (120), extending in the Y-direction and vertically (in the Z-direction) down through the dielectric (118) and metal (116) stack into the isolation material (102) as in Gupta [0045]).
Regarding Claim 12 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 11.
The combination of Gupta, Kim, and Sim further discloses the patterning of the metal layer, the metal-containing layer, the oxygen-containing layer and the hard layer comprises: forming a patterned layer over the hard layer (patterning for openings 120 as in Gupta [0048]); and removing portions of the metal layer, the metal-containing layer, the oxygen-containing layer and the hard layer exposed through the patterned layer (creating opening 120 as in Gupta [0049]).
Regarding Claim 13 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 10.
The combination of Gupta, Kim, and Sim further discloses the first dielectric layer (130 in Gupta Fig. 1F; [0053]) is formed by a chemical vapor deposition (CVD) (Gupta [0058]).
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220051930 A1, hereafter “Gupta”), in view of Kim et al (KR 20010105760 A, hereinafter “Kim”), and further in view of Sim et al (US 20120058639 A1, hereinafter “Sim”), and further in view of Yieh et al (US 5,994,209 A, hereinafter “Yieh”)
Regarding Claim 6 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 1.
The combination of Gupta, Kim, and Sim does not disclose the dielectric layer includes one or more of silane (SiH4) and TEOS oxide.
However, Yieh teaches “Of course, those of ordinary skill in the art will understand that other process recipes and other reaction systems like plasma enhanced CVD (PECVD) may also be used to deposit the dielectric films. …Examples of silicon sources include silane (SiH4), TEOS, or a similar silicon source…” (Yieh [0145])
Similarly to Gupta, Yieh teaches silicon dioxide deposition on semiconductor wafers by chemical vapor deposition (CVD). Silane and TEOS are well-known sources for silicon to use in the process of depositing silicon oxide by CVD, as mentioned by Yieh. Therefore, it would have been obvious prior to the effective filing date of the instant application to use silane or TEOS for deposition of the dielectric layer.
Regarding Claim 15 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 1.
The combination of Gupta, Kim, and Sim does not disclose the first dielectric layer includes silane.
However, Yieh teaches “Of course, those of ordinary skill in the art will understand that other process recipes and other reaction systems like plasma enhanced CVD (PECVD) may also be used to deposit the dielectric films. …Examples of silicon sources include silane (SiH4), TEOS, or a similar silicon source…” (Yieh [0145])
Silane is well-known sources for silicon to use in the process of depositing silicon oxide. Therefore, it would have been obvious prior to the effective filing date of the instant application to consider using silane for deposition of the dielectric layer.
Claims 9, 16-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220051930 A1, hereafter “Gupta”), in view of Kim et al (KR 20010105760 A, hereinafter “Kim”), and further in view of Sim et al (US 20120058639 A1, hereinafter “Sim”), and further in view of Hwang et al (US 20220208687 A1, hereinafter “Hwang”).
Regarding Claim 9 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 1.
The combination of Gupta, Kim, and Sim does not disclose a redistribution structure over the dielectric layer and electrically connected to the first bit line or the second bit line.
However, Hwang teaches “The upper structure 100U may include insulation materials 151, 152, and 153 and an in-line redistribution layer 156.” (Hwang Fig. 1; [0019]). “The in-line redistribution layer 156 may be electrically connected to one among the top interconnections 142 by passing through the insulation materials 151, 152, and 153.” (Hwang [0019])
Gupta and Hwang are considered to be analogous because both are in the area of semiconductor memory device structures. Hwang describes additional top layers, their constituents and method of making, including additional dielectric and redistribution layers in preparation for packaging (Hwang [0025]). Thus, it would have been obvious prior to the effective filing date to incorporate at least one more dielectric layer, as well as a redistribution layer, to make the device ready for external interconnects.
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Regarding Claim 16 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 10.
The combination of Gupta, Kim, and Sim fails to disclose forming a second dielectric layer over the first dielectric layer.
However, Hwang discloses forming a second dielectric layer (153) over the first dielectric layer (151). (Hwang [0020], as shown in Hwang Fig. 1)
Gupta and Hwang are considered to be analogous because both are in the area of semiconductor memory device structures. Hwang describes additional top layers, their constituents, planarization, and method of making, including additional dielectric and redistribution layers in preparation for packaging (Hwang [0025]). Thus, it would have been obvious prior to the effective filing date to incorporate at least one more dielectric layer, as well as a redistribution layer, to make the device ready for external interconnects.
Regarding Claim 17 – Gupta modified by Kim, and further modified by Sim and Hwang, discloses all the limitations of claim 16.
The combination of Gupta, Kim, Sim, and Hwang further discloses the second dielectric layer (153) is formed by a chemical vapor deposition. (The first passivation layer 151 and the in-line top dielectric layer 153 may be made of a same material as explained in Hwang [0020] and layer 151 may include a high-density plasma (HDP) oxide as explained in [0031], which is a CVD process. Layer 151 in Hwang is also analogous to layer 130 in Gupta, which is deposited by CVD as in Gupta [0058])
Regarding Claim 19 – Gupta modified by Kim, and further modified by Sim and Hwang, discloses all the limitations of claim 17.
The combination of Gupta, Kim, Sim, and Hwang further discloses planarizing the second dielectric layer (153). (Hwang [0038])
Regarding Claim 20 – Gupta modified by Kim, and further modified by Sim and Hwang, discloses all the limitations of claim 17.
The combination of Gupta, Kim, Sim, and Hwang further discloses forming a redistribution layer (156) over the second dielectric layer (153). (Hwang [0019], and shown in Hwang Fig. 1)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220051930 A1, hereafter “Gupta”), in view of Kim et al (KR 20010105760 A, hereinafter “Kim”), and further in view of Sim et al (US 20120058639 A1, hereinafter “Sim”), and further in view of Moghadam (US 5,426,076 A, hereinafter “Moghadam”).
Regarding Claim 14 – Gupta modified by Kim, and further modified by Sim, discloses all the limitations of claim 13.
The combination of Gupta, Kim, and Sim does not disclose a deposition rate of the CVD is greater than 70 angstroms per second.
However, Moghadam teaches “These parameters will give a deposition rate of approximately 7,000-9,000 Å per minute of SiO2 formed by PECVD TEOS. Deposition of SiO2 by PECVD TEOS gives poor step coverage, therefore, depositions of SiO2 by PECVD TEOS tend to leave cavities between raised surface structures” (Moghadam column 5, lines 58-63). This is equivalent to 116 to 150 Å per minute, well above 70 Å per minute.
Moghadam reported the effect on step coverage of a high deposition rate of a silicon dioxide layer, which is analogous to the instant application wherein the cavities between raised surface structures are intentional. High deposition rate was taught to produce this result (Moghadam column 5, lines 58-63). Therefore, the deposition rate of silicon dioxide by CVD above 70 Å per minute is well known in the industry, and would have been obvious prior to the effective filing date of the instant application to consider applying to the deposition of this dielectric layer to gain the benefit of intentionally leaving air gaps between bit lines.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al (US 20220051930 A1, hereafter “Gupta”), in view of Kim et al (KR 20010105760 A, hereinafter “Kim”), and further in view of Sim et al (US 20120058639 A1, hereinafter “Sim”), and further in view of Hwang et al (US 20230164980 A1, hereinafter “Hwang”), and further in view of Moghadam (US 5,426,076 A, hereinafter “Moghadam”).
Regarding Claim 18 – Gupta modified by Kim, and further modified by Sim and Hwang, discloses all the limitations of claim 17.
The combination of Gupta, Kim, Sim, and Hwang does not disclose a deposition rate of the second dielectric layer is less than a deposition rate of the first dielectric layer.
However, Moghadam teaches deposition of silicon oxide dielectric layers slower to achieve better uniformity and fill in cavities. “The depositional characteristics of THCVD TEOS are such that it tends to fill in cavities…and any nonuniformities on the depositional surface…” (Moghadam column 6, lines 30-33) and “These parameters will give a deposition rate of approximately 2,500-3,000 Å per minute” (Moghadam column 6, lines 60-62), which is significantly slower than the range of 7,000-9,000 Å per minute for fast deposition to trap cavities, or air gaps.
Hwang and Moghadam are considered to be analogous because both are concerned with depositing a subsequent dielectric layer onto a nonuniformly deposited first dielectric layer. Moghadam teaches low deposition rate for the advantage of excellent step coverage (Moghadam col. 2, lines 21-24). Therefore, it would have been obvious to one skilled in the art prior to the effective filing date of the instant application to use a slower deposition rate for the second dielectric layer to gain the benefit of greater uniformity and excellent step coverage.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898