Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/22/2025 has been entered.
Specification Objection Withdrawal
Applicant’s amendment of the title of the invention is acknowledged. Thus, the objection to specification is withdrawn.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim 9 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (U.S. Patent Pub. No. 2021/0098468).
Regarding Claim 9
FIG. 5 of Chen discloses a semiconductor structure, comprising: a first functional transistor comprising a first gate stack (left 430) over an active region; an isolation transistor comprising a second gate stack (right 430) over the active region, wherein the first functional transistor and the isolation transistor share a first source/drain feature (400); and a first contact plug (243) directly above the first source/drain feature between the first gate stack and the second gate stack, wherein: in operation, the first contact plug and the second gate stack receive a same voltage [0032]; a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
The limitations “functional transistor” and “isolation transistor” containing recitations with respect to the manner in which a claimed apparatus is intended to be employed, for example for controlling, amplifying, or generating electrical signals, and for electrical isolation from other components on an integrated circuit. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Chen teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Claims 9 and 13 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw (U.S. Patent Pub. No. 2014/0035056).
Regarding Claim 9
FIG. 2 of Liaw discloses a semiconductor structure, comprising: a first functional transistor (PU-2) comprising a first gate stack over an active region; an isolation transistor (PU-1) comprising a second gate stack over the active region, wherein the first functional transistor and the isolation transistor share a first source/drain feature [0014]; and a first contact plug (42) directly above the first source/drain feature between the first gate stack and the second gate stack, wherein: in operation, the first contact plug and the second gate stack receive a same voltage [0023]; a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
The limitations “functional transistor” and “isolation transistor” containing recitations with respect to the manner in which a claimed apparatus is intended to be employed, for example for controlling, amplifying, or generating electrical signals, and for electrical isolation from other components on an integrated circuit. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Liaw teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 13
FIG. 2 of Liaw discloses a metal layer over the first contact plug [0015], wherein the metal layer comprises a power supply line, and both the first contact plug and the second gate stack are electrically connected to the power supply line [0014].
Claim 9 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Matsui (U.S. Patent Pub. No. 2007/0023832).
Regarding Claim 9
FIG. 10 of Matsui discloses a semiconductor structure, comprising: a first functional transistor comprising a first gate stack (16) over an active region; an isolation transistor comprising a second gate stack (8) over the active region, wherein the first functional transistor and the isolation transistor share a first source/drain feature (14b); and a first contact plug (12) directly above the first source/drain feature between the first gate stack and the second gate stack, wherein: in operation, the first contact plug and the second gate stack receive a same voltage [0007]; a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
The limitations “functional transistor” and “isolation transistor” containing recitations with respect to the manner in which a claimed apparatus is intended to be employed, for example for controlling, amplifying, or generating electrical signals, and for electrical isolation from other components on an integrated circuit. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Matsui teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Claim 9 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ference (U.S. Patent No. 6,534,389).
Regarding Claim 9
FIG. 7 of Ference discloses a semiconductor structure, comprising: a first functional transistor comprising a first gate stack (right 14) over an active region; an isolation transistor comprising a second gate stack (left 14) over the active region, wherein the first functional transistor and the isolation transistor share a first source/drain feature (30); and a first contact plug (34) directly above the first source/drain feature between the first gate stack and the second gate stack, wherein: in operation, the first contact plug and the second gate stack receive a same voltage; a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
The limitations “functional transistor” and “isolation transistor” containing recitations with respect to the manner in which a claimed apparatus is intended to be employed, for example for controlling, amplifying, or generating electrical signals, and for electrical isolation from other components on an integrated circuit. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Matsui teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Bergendahi (U.S. Patent Pub. No. 2018/0219101) of record, in view of Lee (KR 20090025084, machine-translation provided).
Regarding Claim 9
FIG. 13 of Bergendahi discloses a semiconductor structure, comprising: a first transistor comprising a first gate stack (802) over an active region (110); a second transistor comprising a second gate stack (804) over the active region, wherein the first transistor and the second transistor share a first source/drain feature (402).
Bergendahi is silent with respect to “a first contact plug directly above the first source/drain feature between the first gate stack and the second gate stack, wherein: in operation, the first contact plug and the second gate stack receive a same voltage; a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined is greater than a distance between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance”.
FIG. 9 of Lee discloses a similar semiconductor structure, comprising a first contact plug (412) directly above the first source/drain feature (230) between the first gate stack (220B) and the second gate stack (220A), wherein a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined is greater than a distance between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Bergendahi, as taught by Lee. The ordinary artisan would have been motivated to modify Bergendahi for purpose of improving stability (text of Lee).
The limitations “functional transistor” and “isolation transistor” containing recitations with respect to the manner in which a claimed apparatus is intended to be employed, for example for controlling, amplifying, or generating electrical signals, and for electrical isolation from other components on an integrated circuit. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Bergendahi teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Kim (U.S. Patent Pub. No. 2022/0246738) of record, in view of Yoon (U.S. Patent Pub. No. 2018/0005943).
Regarding Claim 9
FIG. 7 of Kim discloses a semiconductor structure, comprising: a first transistor comprising a first gate stack (GSTB) over an active region; a second transistor comprising a second gate stack (GSTA) over the active region, wherein the first transistor and the second transistor share a first source/drain feature (SD), a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined is greater than a distance between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
Kim is silent with respect to “in operation, the first contact plug and the second gate stack receive a same voltage”.
FIG. 3 of Yoon discloses a similar semiconductor structure, comprising a first contact plug (VP) between the first gate stack (G1) and the second gate stack (G2), wherein in operation, the first contact plug and the second gate stack receive a same voltage, wherein a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined is greater than a distance between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Yoon. The ordinary artisan would have been motivated to modify Kim for purpose of improving electrical characteristics ([0006] of Yoon).
The limitations “functional transistor” and “isolation transistor” containing recitations with respect to the manner in which a claimed apparatus is intended to be employed, for example for controlling, amplifying, or generating electrical signals, and for electrical isolation from other components on an integrated circuit. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Kim teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Liu (U.S. Patent Pub. No. 2018/0076139), in view of Soss (U.S. Patent Pub. No. 2011/0062501).
Regarding Claim 9
FIG. 5 of Liu discloses a semiconductor structure, comprising: a first transistor comprising a first gate stack (right 512) over an active region; a second transistor comprising a second gate stack (left 512) over the active region, wherein the first transistor and the second transistor share a first source/drain feature (506), a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined is greater than a distance between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
Liu is silent with respect to “in operation, the first contact plug and the second gate stack receive a same voltage”.
FIG. 9C of Soss discloses a similar semiconductor structure, comprising a first contact plug (903) directly above the first source/drain feature (203) between the first gate stack (left 701) and the second gate stack (right 701), wherein in operation, the first contact plug and the second gate stack receive a same voltage, wherein a first distance is defined between a first sidewall of the first contact plug facing the first gate stack and a sidewall of the first gate stack facing the first contact plug; a second distance is defined is greater than a distance between a second sidewall of the first contact plug facing the second gate stack and a sidewall of the second gate stack facing the first contact plug; and the first distance is greater than the second distance.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Liu, as taught by Soss. The ordinary artisan would have been motivated to modify Liu for purpose of improving transistor performance ([0004] of Soss).
The limitations “functional transistor” and “isolation transistor” containing recitations with respect to the manner in which a claimed apparatus is intended to be employed, for example for controlling, amplifying, or generating electrical signals, and for electrical isolation from other components on an integrated circuit. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Liu teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Claims 10, 11 and 14 rejected under 35 U.S.C. 103 as being unpatentable over Kim and Yoon, in view of Rastogi (U.S. Patent Pub. No. 2018/0102364) of record.
Regarding Claim 10
Kim as modified by Yoon discloses Claim 1, comprising: a second functional transistor comprising a third gate stack over the active region, wherein the first functional transistor and the second functional transistor share a second source/drain feature; and a second contact plug directly above the second source/drain feature between the first gate stack and the third gate stack.
Kim as modified by Yoon is silent with respect to “the first contact plug is longer and wider than the second contact plug”.
FIG. 2 of Rastogi discloses a similar semiconductor structure, comprising a second functional transistor comprising a third gate stack over the active region, wherein the first functional transistor and the second functional transistor share a second source/drain feature; and a second contact plug directly above the second source/drain feature between the first gate stack and the third gate stack, wherein the first contact plug (with DCU) is longer and wider than the second contact plug (CP1 without DCU).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Rastogi. The ordinary artisan would have been motivated to modify Kim, because the claimed configuration was a matter of choice, which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration was significant. In re Dailey 149 USPQ 47, 50 (CCPA 1966). See also Glue Co. v. Upton 97 US 3,24 (USSC 1878). MPEP 2144.04.
Regarding Claim 11
FIG. 2 of Rastogi discloses a second functional transistor comprising a third gate stack over the active region, wherein the isolation transistor and the second functional transistor share a second source/drain feature, wherein the active region comprises a fin element (FA1) continuously extending below the first gate stack, the second gate stack and the third gate stack.
Regarding Claim 14
FIG. 2 of Rastogi discloses an interlayer dielectric layer (154) surrounding the first contact plug; and a second contact plug in the interlayer dielectric layer, wherein the second contact plug (including DCU) is in contact with both the first contact plug and the second gate stack.
Claim 12 rejected under 35 U.S.C. 103 as being unpatentable over Kim, Yoon and Rastogi, in view of Varshavskij (SU 1624530) of record.
Regarding Claim 12
Kim as modified by Yoon and Rastogi discloses Claim 11.
Kim as modified by Yoon and Rastogi is silent with respect to “a NAND circuit comprising the first functional transistor; and an inverter circuit comprising the second functional transistor, wherein the isolation transistor is located between the NAND circuit and the inverter circuit”.
Varshavskij discloses a similar semiconductor structure, comprising a NAND circuit comprising the first functional transistor; and an inverter circuit comprising the second functional transistor, wherein the isolation transistor is located between the NAND circuit and the inverter circuit (Claims).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Rastogi. The ordinary artisan would have been motivated to modify Kim for purpose of forming a parallel asynchronous register (Abstract).
Claim 15 rejected under 35 U.S.C. 103 as being unpatentable over Bergendahi and Lee, in view of Baek (U.S. Patent Pub. No. 2021/0074697) of record.
Regarding Claim 15
Bergendahi as modified by Lee discloses Claim 9.
Bergendahi as modified by Lee is silent with respect to “the active region includes a first set of nanostructures wrapped by the first gate stack and a second set of nanostructures wrapped by the second gate stack”.
FIG. 17 of Baek discloses a similar semiconductor structure, wherein the active region includes a first set of nanostructures (112) wrapped by the first gate stack (125_1U) and a second set of nanostructures (114) wrapped by the second gate stack (125_1L).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Bergendahi, as taught by Baek. The ordinary artisan would have been motivated to modify Bergendahi for purpose of improving a degree of integration of the layout and the performance and reliability of a designed semiconductor device ([0005] of Baek).
Claim 16 rejected under 35 U.S.C. 103 as being unpatentable over Bergendahi and Lee, in view of Shu (U.S. Patent Pub. No. 2020/0411684) of record.
Regarding Claim 16
Bergendahi as modified by Lee discloses Claim 9.
Bergendahi as modified by Lee is silent with respect to “a contact etching stop layer over the first source/drain feature, wherein the contact etching stop layer includes a first vertical portion along a first sidewall of the first gate stack and a second vertical portion along a second sidewall of the second gate stack; and an interlayer dielectric layer over the contact etching stop layer, wherein the first contact plug is in contact with the second vertical portion of the contact etching stop layer and separated from the first vertical portion of the contact etching stop layer by the interlayer dielectric layer”.
FIG. 7 of Shu discloses a similar semiconductor structure, comprising a contact etching stop layer over the first source/drain feature, wherein the contact etching stop layer includes a first vertical portion (34) along a first sidewall of the first gate stack (130B) and a second vertical portion (40) along a second sidewall of the second gate stack (130A); and an interlayer dielectric layer (42) over the contact etching stop layer, wherein the first contact plug is in contact with the second vertical portion of the contact etching stop layer and separated from the first vertical portion of the contact etching stop layer by the interlayer dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Bergendahi, as taught by Shu. The ordinary artisan would have been motivated to modify Bergendahi for purpose of improving device performance ([0003] of Shu).
Claims 21-28 rejected under 35 U.S.C. 103 as being unpatentable over Baek (U.S. Patent Pub. No. 2021/0074697) of record, in view of Matsui (U.S. Patent Pub. No. 2007/0023832).
Regarding Claim 21
FIG. 17 of Baek discloses a semiconductor structure, comprising: a first transistor comprising a first gate stack (125_1U) over an active region (112); a second transistor comprising a first set of nanostructures (114) vertically stacked and spaced apart from one another; a second gate stack (125_1L) over (at a higher level or layer than) the active region, wrapping around the first set of nanostructures, and extending in a first direction; and a first source/drain feature and a second source/drain feature (130, FIG. 16) adjoining opposite sides of the first set of nanostructures [0051], wherein the first transistor and the second transistor share the first source/drain feature, and the first source/drain feature extends between the first gate stack (125_1) and the second gate stack (125_2); and a first contact plug (170_1) above (at a higher level or layer than) the first source/drain feature between the first gate stack and the second gate stack (120), and a second contact plug (170) over (at a higher level or layer than) the second source/drain feature, as measured in a second direction which is perpendicular to the first direction, a width of the second contact plug is less than a width of the first contact plug (FIG. 5).
Baek is silent with respect to “a first contact plug directly above the first source/drain feature between the first gate stack and the second gate stack, and a second contact plug over the second source/drain feature, wherein as measured in a second direction which is perpendicular to the first direction, a width of the second contact plug at a height above the first source/drain feature is less than a width of the first contact plug at the height above the first source/drain feature”.
FIG. 10 of Matsui discloses a similar semiconductor structure, comprising a first contact plug (12) directly above the first source/drain feature (14b) between the first gate stack (16) and the second gate stack (12), and a second contact plug (20) over the second source/drain feature (14a), wherein as measured in a second direction which is perpendicular to the first direction, a width of the second contact plug at a height above the first source/drain feature is less than a width of the first contact plug at the height above the first source/drain feature.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Baek, as taught by Matsui. The ordinary artisan would have been motivated to modify Baek for purpose of forming a shared contact connecting the source/drain feature and the gate electrode for the micronization advances ([0017] of Matsui).
The limitations “functional transistor” and “isolation transistor” containing recitations with respect to the manner in which a claimed apparatus is intended to be employed, for example for controlling, amplifying, or generating electrical signals, and for electrical isolation from other components on an integrated circuit. This recitation does not differentiate the claimed apparatus from the prior art apparatus because the apparatus of Baek teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), see MPEP 2114 R-1.
Regarding Claim 22
FIG. 10 of Matsui discloses a distance between the second contact plug and the second gate stack is greater than a distance between the first contact plug and the second gate stack.
Regarding Claim 23
FIGS. 9 and 17 of Baek disclose a metal layer (195_2) over the first contact plug and the second contact plug, wherein the second contact plug is electrically connected to the first gate stack through the metal layer.
Regarding Claim 24
FIGS. 9 and 17 of Baek disclose the first contact plug is electrically isolated from the first gate stack.
Regarding Claim 25
FIG. 17 of Baek discloses a second transistor comprising a second set of nanostructures (114NS) vertically stacked and spaced apart from one other, and a second gate stack wrapping around the second set of nanostructures and extending in the first direction; and a gate isolation structure (124) sandwiched between and in contact with the first gate stack and the second gate stack.
Regarding Claim 26
FIG. 17 of Baek discloses the first transistor is a p-channel transistor and the second transistor is an n-channel transistor [0008].
Regarding Claim 27
FIG. 17 of Baek discloses a second set of nanostructures vertically stacked and spaced apart from one another, the first gate stack wraps around the second set of nanostructures and extends in the first direction, the first source/drain feature adjoins a first side of the second set of nanostructures, and a third source/drain feature adjoins a second side of the second set of nanostructures.
Regarding Claim 28
With respect to “a ratio of the width of the first contact plug to the width of the second contact plug is in a range from about 1.05 to about 1.25”, said ratio is related to the electrical characteristics. Therefore, said ratio is considered to be a result effective variable. The claim to a specific ratio therefore constitutes an optimization of ranges. In re Huang, 100 F.3d 135, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996). It would have been obvious to one of ordinary skill in the art at the time of the invention to use the parameters as claimed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art (MPEP 2144.05).
Claims 29-32 rejected under 35 U.S.C. 103 as being unpatentable over Bergendahi, in view of Tsugane (U.S. Patent No. 6,881,995), in view of Rastogi (U.S. Patent Pub. No. 2018/0102364) of record.
Regarding Claim 29
FIG. 13 of Bergendahi discloses a semiconductor structure, comprising: a first circuit in a first cell region, the first circuit comprising: a first transistor comprising a first gate stack (802) over an active region (110); a second transistor comprising a second gate stack (804) over the active region; a third transistor comprising a third gate stack (806) over the active region, wherein the second transistor and the third transistor share a first source/drain feature (404), and the first gate stack, the second gate stack, and the third gate stack are sequentially arranged in a first direction.
Bergendahi is silent with respect to “a first contact plug between the first gate stack and the second gate stack; a second contact plug directly above the first source/drain feature between the second gate stack and the third gate stack, wherein, a first distance is defined between a first sidewall of the second contact plug facing the second gate stack and a sidewall of the second gate stack facing the second contact plug; a second distance is defined between a second sidewall of the second contact plug facing the third gate stack and a sidewall of the third gate stack facing the second contact plug; and the first distance is greater than the second distance; and a power branch line over the first contact plug and the second contact plug, wherein both the second contact plug and the third gate stack are electrically connected to the power branch line”.
FIG. 7 of Tsugane discloses a similar semiconductor structure, comprising a first contact plug (58b) between the first gate stack (100b) and the second gate stack (17b); a second contact plug (300) directly above the first source/drain feature between the second gate stack and the third gate stack (17a), wherein, a first distance is defined between a first sidewall of the second contact plug facing the second gate stack and a sidewall of the second gate stack facing the second contact plug; a second distance is defined between a second sidewall of the second contact plug facing the third gate stack and a sidewall of the third gate stack facing the second contact plug; and the first distance is greater than the second distance.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Bergendahi, as taught by Tsugane. The ordinary artisan would have been motivated to modify Bergendahi for purpose of shortening the chip interface delay and reducing the cost (Col. 1, Lines 24-30 of Tsugane).
Bergendahi as modified by Tsugane is silent with respect to “a power branch line over the first contact plug and the second contact plug, wherein both the second contact plug and the third gate stack are electrically connected to the power branch line”.
FIG. 2 of Rastogi discloses a similar semiconductor structure, comprising a first contact plug (CP1 without DCU) between the first gate stack and the second gate stack (GL); a second contact plug (with DCU) directly above the first source/drain feature (170) between the second gate stack and the third gate stack, wherein both the second contact plug and the third gate stack are electrically connected to the power supply line [0054].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Bergendahi, as taught by Rastogi. The ordinary artisan would have been motivated to modify Bergendahi for purpose of connecting a power line to source/drain region ([0004] of Rastogi).
Regarding Claim 30
FIG. 2 of Rastogi discloses a second circuit in a second cell region, the second circuit comprising a fourth gate stack, wherein the third gate stack is located between the second gate stack and the fourth gate stack; and a third contact plug between the third gate stack and the fourth gate stack, wherein, in the first direction, the second contact plug is wider than the third contact plug.
Regarding Claim 31
Bergendahi as modified by Rastogi discloses a second circuit in a second cell region, the second circuit comprising a fourth gate stack and a fifth gate stack; a second isolation transistor comprising a sixth gate stack, wherein: the fourth gate stack, the fifth gate stack, and the sixth gate stack are sequentially arranged in the first direction, and the sixth gate stack is electrically connected to the power branch line; a first gate isolation structure sandwiched between the first gate stack and the fourth gate stack; a second gate isolation structure sandwiched between the second gate stack and the fifth gate stack; and a third gate isolation structure sandwiched between the third gate stack and the sixth gate stack, because mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See MPEP 2144.04.
Regarding Claim 32
FIG. 2 of Rastogi discloses the second contact plug extends between the fifth gate stack and the sixth gate stack.
Pertinent Art
US 20190165118 discloses a semiconductor structure, comprising: a first transistor comprising a first gate stack over an active region; a second transistor comprising a second gate stack over the active region, wherein the first transistor and the second transistor share a first source/drain feature; and a first contact plug directly above the first source/drain feature between the first gate stack and the second gate stack. Pertinent art also includes U.S. Patent No. 6,037,216, 10516064, 5,994,730, 6593632, and U. S. Pub. 20240063221, 20030107133, 20210036121, 20220406775, 20220231016 and 20210376101, JP H09116113 and JP H11214656.
Response to Arguments
Applicant's arguments with respect to Claim 9 have been considered but but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897