DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dalmia et al. (US 2019/0035749 A1) in view of Lin et al. (US 2017/0040266 A1).
Regrading Claim 1, Dalmia (Fig. 6) discloses a package structure, comprising:
chip package (600), comprising at least one semiconductor die (606), a first insulating encapsulation (608) encapsulating the at least one semiconductor die (606), and a plurality of conductive pillars (610) next to the at least one semiconductor die (606) and penetrating through the first insulating encapsulation (608), wherein
a height of the plurality of the conductive pillars (610) are greater than a height of the at least one semiconductor die (606); and
an antenna package (614), disposed on and electrically coupled to the chip package (600), wherein
the antenna package (614) comprises:
metallic patterns (616), embedded in a second insulating encapsulation (see encapsulant around 616), wherein
each of the metallic patterns (616) has a first surface (bottom), a second surface opposite to the first surface and a side surface connecting the first surface and the second surface (see surfaces of 616) (Fig. 6 and 1B), wherein
the first surface and the side surface of the at least one of the metallic patterns are covered by the second insulating encapsulation (see encapsulant around 616), and the second surface (top) of the at least one of the metallic patterns is substantially coplanar with a third surface of the second insulating encapsulation (top of encapsulant around 616), wherein
the first surface (bottom of 616) of the at least one of the metallic patterns (616) is closer to the at least one semiconductor die (606) than the second surface (top of 616) of the at least one of the metallic patterns (616).
wherein in a cross section of the package structure, an outermost sidewall of the second insulating encapsulation (encapsulant around 616) is laterally offset from an outermost sidewall of the first insulating encapsulation (608) See Fig. 6B).
Dalmia does not explicitly disclose the plurality of conductive pillars are electrically coupled to the at least one semiconductor die.
Lin (Fig. 1) discloses a plurality of conductive pillars (122) are electrically coupled to at least one semiconductor die. (110)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a package structure in Dalmia in view of Lin such that the plurality of conductive pillars are electrically coupled to the at least one semiconductor die in order to connect semiconductor die to an antenna pattern [0044-0046]
Regrading Claim 2, Dalmia in view of Lin discloses the package structure of claim 1, wherein
the second surface of the at least one of the metallic patterns (616) is accessibly revealed by the third surface of the second insulating encapsulation. (See Fig. 6B of Dalmia)
Regrading Claim 3, Dalmia in view of Lin discloses the package structure of claim 1, further comprising:
a connecting film (602, 612), disposed on a fourth surface of the second insulating encapsulation (encapsulation around 616), wherein
the third surface is opposite to the fourth surface, and the connecting film is disposed between the chip package (600) and the antenna package. (614) (Fig. 6B of Dalmia)
Regrading Claim 4, Dalmia in view of Lin discloses the package structure of claim 3, wherein
two opposite sides of the connecting film (602, 612) physically contact the second insulating encapsulation (encapsulation around 616) and the chip package (600), respectively.
Regrading Claim 5, Dalmia in view of Lin discloses the package structure of claim 1, wherein
the chip package further comprises:
a first redistribution circuit structure (602), disposed between the antenna package (614) and the first insulating encapsulation (608) and electrically coupled to the at least one semiconductor die (606) and the plurality of conductive pillars (610), wherein
the first insulating encapsulation (608) is in physical contact with the first redistribution circuit structure (602).
Regrading Claim 6, Dalmia in view of Lin discloses the package structure of claim 5, wherein
the first redistribution circuit structure (602) comprises at least one alignment mark, and the at least one alignment mark comprises a predetermined pattern of a solid metal plate having at least one slit. (See pads on 602 and slit between them) (“ the pads on the antenna package may be aligned to corresponding pads on the semiconductor package and attached using “ and “the antenna package may be aligned and placed on to the semiconductor package substrate and held using epoxy. The alignment may be performed with a pick-and-place system to align corresponding pads of the semiconductor package substrate and the antenna package”.) [0022, 0062, 0070, 0083].
Regrading Claim 7, Dalmia in view of Lin discloses the package structure of claim 6, wherein a shape of the at least one slit comprises a L-shape, a cross-shape, a circular-shape, a triangular-shape, a rectangular shape, or combinations thereof. (See a triangular-shape, a rectangular shape of pads on 602)
Regrading Claim 8, Dalmia in view of Lin discloses the package structure of claim 5, wherein
the chip package further comprises:
a second redistribution circuit structure (620), disposed on the first insulating encapsulation (608) and electrically coupled to the at least one semiconductor die, wherein
the first insulating encapsulation (608) is disposed between the first redistribution circuit (602) and the second redistribution circuit (620), and the plurality of conductive pillars (610) are connected to and electrically coupled to the first redistribution circuit (602) structure and the second redistribution circuit structure (620); and
conductive elements (618, Examiner notes that PCB 618 includes multiple conductive elements), disposed on and electrically coupled to the second redistribution circuit structure (620), wherein
the second redistribution circuit structure (320) is disposed between the first insulating encapsulation (610) and the conductive elements (618).
Dalmia in view of Lin as previously combined does not explicitly disclose that a second redistribution circuit structure electrically coupled to the at least one semiconductor die.
Lin (Dig. 1) discloses second redistribution circuit structure (104, 100C) electrically coupled to the at least one semiconductor die.(110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a package structure in Dalmia in view of Lin such that a second redistribution circuit structure electrically coupled to the at least one semiconductor die in order to connect semiconductor die to an antenna pattern [0044-0046].
Regrading Claim 10, Dalmia in view of Lin discloses the package structure of claim 1, wherein
a sidewall of the antenna package is distant from a sidewall of the chip package on a direction perpendicular to a stacking direction of the antenna package and the chip package. (See Fig. 6B)
Claim(s) 9, 19 and 20is/are rejected under 35 U.S.C. 103 as being unpatentable over Dalmia et al. (US 2019/0035749 A1) in view of Lin et al. (US 2017/0040266 A1) and further in view of Dalmia et al. (US 2019/0139915 A1; hereinafter Dalmia/915).
Regrading Claim 9, Dalmia in view of Lin discloses the package structure of claim 1, wherein
Dalmia in view of Lin does not explicitly disclose a sidewall of the antenna package is aligned with a sidewall of the chip package along a stacking direction of the antenna package and the chip package.
However, Dalmia/915 (Fig. 7) discloses a sidewall of an antenna package (220) is aligned with a sidewall of a chip package (704)) along a stacking direction of the antenna package (220) and the chip package (704).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a package structure in Dalmia in view of Lin and Dalmia/915 such that a sidewall of the antenna package is aligned with a sidewall of the chip package along a stacking direction of the antenna package and the chip package in order to meet designed height and volume targets of the wireless module [0072].
Regrading Claim 19, Dalmia discloses a package structure, comprising:
a chip package (600, 602), comprising:
a plurality of conductive pillars (610);
at least one semiconductor die (606), laterally disposed next to the plurality of conductive pillars (610), wherein
a height of the plurality of the conductive pillars (610) is greater than a height of the at least one semiconductor die (606); and
a first insulating encapsulation (608), encapsulating the at least one semiconductor die (606) and the plurality of conductive pillars (610), the plurality of conductive pillars penetrating through the first insulating encapsulation (608); and
an antenna package (614), disposed on and electrically coupled to the chip package (600), wherein
the antenna package (614) comprises:
metallic patterns (616), wherein
each of the metallic patterns has a first surface (buttom), a second surface opposite to the first surface and a side surface connecting the first surface and the second surface (see surfaces of 616 in Fig. 6B);
a second insulating encapsulation (see encapsulant around 616), covering the metallic patterns (616), wherein
the first surface and the side surface of each of the metallic patterns are covered by the second insulating encapsulation (see encapsulant around 616), and the second surface of each of the metallic patterns is substantially coplanar with a third surface of the second insulating encapsulation (top of encapsulant around 616); and
Dalmia does not explicitly disclose the plurality of conductive pillars are electrically coupled to the at least one semiconductor die and a third insulating encapsulation, embedding the second insulating encapsulation, wherein a lateral size of the third insulating encapsulation is greater than a lateral size of the second insulating encapsulation and is less than or substantially equal to a lateral size of the chip package.
Lin (Fig. 1) discloses a plurality of conductive pillars (122) are electrically coupled to at least one semiconductor die. (110)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a package structure in Dalmia in view of Lin such that the plurality of conductive pillars are electrically coupled to the at least one semiconductor die in order to connect semiconductor die to an antenna pattern [0044-0046]
Dalmia in view of Lin does not explicitly disclose a third insulating encapsulation, embedding the second insulating encapsulation, wherein a lateral size of the third insulating encapsulation is greater than a lateral size of the second insulating encapsulation and is less than or substantially equal to a lateral size of the chip package.
Dalmia/915 (Fig. 7) discloses a third insulating encapsulation (728), embedding a second insulating encapsulation (222), wherein a lateral size of the third insulating encapsulation (728) is greater than a lateral size of the second insulating encapsulation (222) and is less than or substantially equal to a lateral size of a chip package (704).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a package structure in Dalmia in view of Lin and Dalmia/915 such that a sidewall of the antenna package is aligned with a sidewall of the chip package along a stacking direction of the antenna package and the chip package in order to meet designed height and volume targets of the wireless module [0072].
Regrading Claim 20, Dalmia in view of Lin and Dalmia/915 discloses the package structure of claim 19, wherein
the chip package further comprises:
a first redistribution circuit structure (602), disposed on a first side of the first insulating encapsulation (608) and electrically coupled to the at least one semiconductor die (606) and the plurality of conductive pillars (610), wherein
the first insulating encapsulation (608) is in physical contact with the first redistribution circuit structure (602);
a second redistribution circuit structure (620), disposed on a second side of the first insulating encapsulation (608) and electrically coupled to the plurality of conductive pillars (620), wherein
the first insulating encapsulation (620 is in physical contact with the second redistribution circuit structure (620), and the plurality of conductive pillars (610) are connected to and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure (See Fgi. 6B), wherein
the first side is opposite to the second side; and
conductive elements (PCB 618 contains conductive elements), disposed on and electrically coupled to the second redistribution circuit structure (620), wherein
the second redistribution circuit structure (620) is disposed between the first insulating encapsulation (608) and the conductive elements (618), wherein
the first redistribution circuit structure (602) is sandwiched between the antenna package (614) and the first insulating encapsulation (610).
Dalmia in view of Lin and Dalmia/915 as previously combined does not explicitly disclose that a second redistribution circuit structure electrically coupled to the at least one semiconductor die.
Lin (Dig. 1) discloses second redistribution circuit structure (104, 100C) electrically coupled to the at least one semiconductor die.(110).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a package structure in Dalmia in view of Lin and Dalmia/915 such that a second redistribution circuit structure electrically coupled to the at least one semiconductor die in order to connect semiconductor die to an antenna pattern [0044-0046].
Allowable Subject Matter
Claim 11-18 allowed.
The following is an examiner's statement of reasons for allowance:
With regards to claim 11, none of the prior art teaches or suggests, alone or in combination, “at least one alignment mark, disposed inside the first redistribution circuit structure, wherein the at least one alignment mark is distant from a conductive feature of the first redistribution circuit structure, and the at least one alignment mark is laterally offset from the plurality of conductive pillars;”…” wherein along the stacking direction, the at least one alignment mark is between the metallic patterns and the first insulating encapsulation.” ” in the combination required by the claim.
Claims 12-18 are allowed by virtue of their dependency on the independent claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance
Response to Arguments
Applicant’s arguments, see Applicant Arguments, filed 12/10/2025, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 as being unpatentable over Lin et al. (“Lin” US 2017/0040266 published 02/09/2017) in view of Liu et al. (“Liu” US 2019/0348748) a have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made under 35 U.S.C. 103 as being unpatentable over Dalmia et al. (US 2019/0035749 A1) in view of Lin et al. (US 2017/0040266 A1).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/ Examiner, Art Unit 2891