DETAILED ACTION
This correspondence is in response to the communications received 12/29/2025. Claims 3-9, 14, and 16-19 have been withdrawn. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to claim 10 overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendment to claim 20 overcomes the 112(b) rejection outlined in the previous Office Action. The 112(b) rejection is withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1, 2, 10-13, and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see ¶(f) on page 10, filed 12/29/2025, with respect to claim 20 have been fully considered and are persuasive. The rejection of 12/01/2025 has been withdrawn.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a semiconductor testing structure (100c/100d), comprising:
a substrate (110);
a first metal layer (140) disposed on the substrate and comprising a plurality of fingers (141) extending along a first direction (the X direction);
a dielectric structure (150) disposed on the first metal layer; and
a second metal layer (160) disposed on the dielectric structure and electrically isolated from the first metal layer (see [0052]), wherein the second metal layer extends along a second direction different from the first direction (the Y direction), wherein the dielectric structure defines a sidewall extending between the first metal layer and the second metal layer (see Fig. 6).
wherein a lateral surface of the second metal layer is not coplanar with the sidewall of the dielectric structure (see Fig. 6).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over LiCausi (US 10,677,855 B2, hereinafter “LiCausi”) in view of Sills et al. (US 8,021,897 B2, hereinafter “Sills”) in view of Li et al. (US 20110210306 A1, hereinafter “Li”).
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Regarding claim 1, Fig. 1 of LiCausi discloses a semiconductor testing structure (“structure 100”, col. 3, line 62, see title), comprising:
a first metal layer (“single electrical ground element 120”, col. 4, line 65, wherein “Electrical ground element 120, regardless of form (e.g., plate, comb or serpentine), can have the same compositional make-up as that of the metal wires. Specifically, the electrical ground element may include a metal selected from Cu, Ru, Co, W, Ti, Al and Mo”, col. 4, lines 49-53) extending along a first direction (as seen in Fig. 1, 120 extends in the horizontal direction);
a dielectric structure disposed on the first metal layer (“an electrical ground element formed beneath one or more portions of the dielectric cap layer”, col. 1, lines 66-67, and col. 2, line 1); and
a second metal layer (“sub-arrays of metal wires 110a, 110b, 110c, 110d, 110e”, col. 5, lines 63-64) disposed on the dielectric structure (“a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires”, col. 2, lines 2-5) and electrically isolated from the first metal layer (“electrical ground element 120 is electrically isolated from the sub-arrays by, for example, a dielectric layer”, col. 4, lines 5-6), wherein the second metal layer extends along a second direction (as seen in Fig. 1, 110a, 110b, 110c, 110d, and 110e extend in the vertical direction) different from the first direction (the vertical direction is different than the horizontal direction).
Fig. 1 of LiCausi fails to disclose “a substrate;
a first metal layer disposed on the substrate and comprising a plurality of fingers extending along a first direction; and
wherein the dielectric structure defines a sidewall extending between the first metal layer and the second metal layer,
wherein a lateral surface of the second metal layer is not coplanar with the sidewall of the dielectric structure.”
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1-11 of Sills teach a substrate (“base 12”, col. 2, line 36, “If the base comprise a semiconductor material, base 12 may be referred to as a semiconductor substrate”, col. 2, lines 36-38);
a first metal layer (“first electrode material 14”, col. 2, line 53, 14 of Sills is equivalent to 120 of LiCausi) disposed on the substrate (“first electrode material 14 physically contacts an upper surface of base 12”, col. 2, lines 53-54); and
wherein the dielectric structure (together “first insulative material 18”, col. 2, line 61, and “second insulative material 20”, col. 2, line 62, form a dielectric structure, 18 and 20 of Sills are equivalent to the dielectric cap layer of LiCausi) defines a sidewall extending between the first metal layer and the second metal layer (“top electrode material 46”, col. 5, line 1, where 46 of Sills is equivalent to 110a, 110b, 110c, 110d, and 110e of LiCausi, and as seen in Fig. 11, 18 and 20 define a sidewall extending between 14 and 46, wherein the sidewalls of 18 are formed during an etch process to pattern 14, see Figs. 1 and 2, and col. 4, lines 14-23).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a substrate;
a first metal disposed on the substrate; and
wherein the dielectric structure defines a sidewall extending between the first metal layer and the second metal layer” as taught by Sills in the system of LiCausi for the purpose of supporting the testing structure and providing a continuous insulator layer between the top and bottom electrodes that electrically isolates the top electrode from the bottom electrode to enable the function of the test structure.
Fig. 1 of LiCausi in combination with Figs. 1-11 of Sills fails to disclose “a first metal layer comprising a plurality of fingers extending along a first direction,
wherein a lateral surface of the second metal layer is not coplanar with the sidewall of the dielectric structure.”
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However, in a similar field of endeavor, Fig. 2 of LiCausi teaches a first metal layer (“single electrical ground element 220”, col. 4, lines 56-57, 220 of Fig. 2 is equivalent to 120 of Fig. 1) comprising a plurality of fingers extending along a first direction (as seen in Fig. 2, 220 is comprising a plurality of fingers extending in the horizontal direction).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first metal layer comprising a plurality of fingers extending along a first direction” as taught by Fig. 2 of LiCausi in the system of Fig. 1 of LiCausi for the purpose of forming discrete overlapping regions between the first and second metal layers.
LiCausi in combination with Sills fails to disclose “wherein a lateral surface of the second metal layer is not coplanar with the sidewall of the dielectric structure”.
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 3A-3C of Li teach wherein a lateral surface of the second metal layer (“conductive layer 140, which may include any suitable conductive material such as tungsten, any appropriate metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the like”, [0052], where 140 of Li is equivalent to 46 of Sills or 110a, 110b, 110c, 110d, and 110e of LiCausi) is not coplanar with the sidewall of the dielectric structure (“a dielectric plug 58c”, [0051], where 58c of Li is equivalent to 18 and 20 of Sills, as seen in Fig. 3, a lateral surface of 140 is not coplanar with the sidewall of 58c).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein a lateral surface of the second metal layer is not coplanar with the sidewall of the dielectric structure” as taught by Li in the system of LiCausi in combination with Sills for the purpose of increasing the margin of error for alignment of the second metal layer.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over LiCausi (US 10,677,855 B2, hereinafter “LiCausi”) in view of Sills et al. (US 8,021,897 B2, hereinafter Sills) in view of Li et al. (US 20110210306 A1, hereinafter “Li”) in view of Kato et al. (US 9,431,412 B1, hereinafter “Kato”).
Regarding claim 2, Figs. 1 and 2 of LiCausi in combination with Figs. 1-11 of Sills and Figs. 3A-3D of Li disclose the semiconductor testing structure of claim 1, Figs. 1-11 of Sills further disclose wherein the dielectric structure comprises a first dielectric layer (18) disposed on and in contact with the first metal layer (as seen in Fig. 11, 18 is on and in contact with 14) and a second dielectric layer (20) disposed on and in contact with the first dielectric layer (as seen in Fig. 11, 20 is disposed on and in contact with 18).
LiCausi in combination with Sills and Li fails to disclose “further comprising:
a conductive layer disposed on the lateral surface and an upper surface of the second metal layer, wherein the second metal layer is enclosed by the conductive layer and the second dielectric layer of the dielectric structure.”
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1-3 of Kato teach further comprising:
a conductive layer (“barrier metal film 23”, col. 6, line 39) disposed on the lateral surface and an upper surface of the second metal layer (as seen in Fig. 2, 23 is disposed on the lateral surface and an upper surface of “electrically conductive member 24”, col. 6, lines 28-39, where “barrier metal film 23 is a film for preventing the electrically conductive material of the electrically conductive member 24 from spreading”, col. 6, lines 50-53, and 24 of Kato is equivalent to 110a, 110b, 110c, 110d, and 110e of LiCausi), wherein the second metal layer is enclosed by the conductive layer (as seen in Fig. 3, 24 is enclosed by 23) and the second dielectric layer of the dielectric structure (as seen in Fig. 11 of Sills, the bottom surface of 46 is enclosed by 20, thus after combining the prior art of Sills and Kato, 46 of Sills, or its equivalent 24 of Kato is enclosed by 23 of Kato and 20 of Sills).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising:
a conductive layer disposed on the lateral surface and an upper surface of the second metal layer, wherein the second metal layer is enclosed by the conductive layer and the second dielectric layer of the dielectric structure” as taught by Kato in the system of LiCausi in combination with Sills and Li for the purpose of preventing atomic diffusion of the second metal layer.
Claims 10-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over LiCausi (US 10,677,855 B2, hereinafter “LiCausi”) in view of Sills et al. (US 8,021,897 B2, hereinafter “Sills”) in view of Kato et al. (US 9,431,412 B1, hereinafter “Kato”).
Regarding claim 10, Fig. 1 of LiCausi discloses a semiconductor testing structure (“structure 100”, col. 3, line 62, see title), comprising:
a first metal layer (“single electrical ground element 120”, col. 4, line 65, wherein “Electrical ground element 120, regardless of form (e.g., plate, comb or serpentine), can have the same compositional make-up as that of the metal wires. Specifically, the electrical ground element may include a metal selected from Cu, Ru, Co, W, Ti, Al and Mo”, col. 4, lines 49-53) extending along a first direction (as seen in Fig. 1, 120 extends in the horizontal direction);
a dielectric structure disposed on the first metal layer (“an electrical ground element formed beneath one or more portions of the dielectric cap layer”, col. 1, lines 66-67, and col. 2, line 1); and
a plurality of second metal layers (“sub-arrays of metal wires 110a, 110b, 110c, 110d, 110e”, col. 5, lines 63-64, where “a second metal layer on top of the dielectric cap layer, the second metal layer having an array of one or more sub-arrays of metal wires”, col. 2, lines 2-5, 110a, 110b, 110c, 110d, 110e are therefore the second metal layer on top of the dielectric cap layer) extending along a second direction (as seen in Fig. 1, 110a, 110b, 110c, 110d, and 110e extend in the vertical direction) different form the first direction (the vertical direction is different than the horizontal direction).
Fig. 1 of LiCausi fails to disclose “a substrate;
a first metal layer comprising a plurality of fingers extending along a first direction; and
a plurality of conductive layers disposed on the dielectric structure;
wherein the second metal layers are disposed on and in contact with the dielectric structure and are enclosed by the conductive layers and the dielectric structure.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1-11 of Sills teach a substrate (“base 12”, col. 2, line 36, “If the base comprise a semiconductor material, base 12 may be referred to as a semiconductor substrate”, col. 2, lines 36-38);
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a substrate” as taught by Sills in the system of LiCausi for the purpose of supporting the testing structure.
Fig. 1 of LiCausi in combination with Figs. 1-11 of Sills fails to disclose “a first metal layer comprising a plurality of fingers extending along a first direction; and
a plurality of conductive layers disposed on the dielectric structure;
wherein the second metal layers are disposed on and in contact with the dielectric structure and are enclosed by the conductive layers and the dielectric structure.”
However, in a similar field of endeavor, Fig. 2 of LiCausi teaches a first metal layer (“single electrical ground element 220”, col. 4, lines 56-57, 220 of Fig. 2 is equivalent to 120 of Fig. 1) comprising a plurality of fingers extending along a first direction (as seen in Fig. 2, 220 is comprising a plurality of fingers extending in the horizontal direction).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first metal layer comprising a plurality of fingers extending along a first direction” as taught by Fig. 2 of LiCausi in the system of Fig. 1 of LiCausi for the purpose of providing a continuous insulator layer between the top and bottom electrodes that electrically isolates the top electrode from the bottom electrode to enable the function of the test structure.
LiCausi in combination with Sills fails to disclose “a plurality of conductive layers disposed on the dielectric structure;
wherein the second metal layers are disposed on and in contact with the dielectric structure and are enclosed by the conductive layers and the dielectric structure.”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 1-3 of Kato teach
a plurality of conductive layers (“barrier metal film 23”, col. 6, line 39, 23 is disposed around “electrically conductive member 24”, col. 6, lines 28-39, as “barrier metal film 23 is a film for preventing the electrically conductive material of the electrically conductive member 24 from spreading”, col. 6, lines 50-53 where 24 of Kato is equivalent to 110a, 110b, 110c, 110d, and 110e of LiCausi, after modifying LiCausi with Kato, each of 110a, 110b, 110c, 110d, and 110e of LiCausi would have a respective instance of 23 of Kato, thus there is a plurality of 23) disposed on the dielectric structure (as discussed above, 110a, 110b, 110c, 110d, and 110e of LiCausi are on the dielectric cap layer of LiCausi, thus the plurality of 23 of Kato would therefore also be on the dielectric cap layer of LiCausi);
wherein the second metal layers are disposed on and in contact with the dielectric structure (as discussed above, 110a, 110b, 110c, 110d, and 110e of LiCausi are on the dielectric cap layer of LiCausi, and would be in contact with the dielectric cap layer of LiCausi via 23 of Kato) and are enclosed by the conductive layers and the dielectric structure ((after the modification of LiCausi by Kato, 110a, 110b, 110c, 110d, and 110e of LiCausi would each be enclosed by 23 of Kato and the dielectric cap of LiCausi).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a plurality of conductive layers disposed on the dielectric structure;
wherein the second metal layers are disposed on and in contact with the dielectric structure and are enclosed by the conductive layers and the dielectric structure” for the purpose of preventing atomic diffusion of the second metal layer.
Regarding claim 11, Figs. 1 and 2 of LiCausi in combination with Figs. 1-11 of Sills and Figs. 1-3 of Kato disclose the semiconductor testing structure of claim 10, Fig. 2 of LiCausi further discloses wherein a first portion of the second metal layer has a first pitch (as seen in Fig. 2, 210a has a first pitch, 210a of Fig. 2 is equivalent to 110a of Fig. 1), and a second portion of the second metal layer has a second pitch (as seen in Fig. 2, 210e has a second pitch, 110a of Fig. 2 is equivalent to 110a of Fig. 1) different from the first pitch (as seen in Fig. 2, the second pitch is different from the first pitch).
Regarding claim 12, Figs. 1 and 2 of LiCausi in combination with Figs. 1-11 of Sills and Figs. 1-3 of Kato disclose the semiconductor testing structure of claim 10, Fig. 1 of LiCausi further discloses wherein the plurality of second metal layers has a first terminal (the connection line between 110a and “bond pad A”, col. 4, lines 30-31, is a first terminal) electrically connected to a first conductive pad (“sub-arrays 110a, 110b, 110c, 110d, 110e are each connected to a given bond pad (in this case, bond pads A, B, C, D, E, respectively)”, col. 4, lines 29-31, wherein the “metal of bond pads A, B, C, D, E, F can be copper (Cu), aluminum (Al), gold (Au), cobalt (Co), ruthenium (Ru), tungsten (W) or silver (Ag)”, col. 4, lines 34-37), and a second terminal (the connection line between 110e and “bond pad E”, col. 4, lines 30-31, is a first terminal) electrically connected to a second conductive pad (bond pad E).
Regarding claim 13, Figs. 1 and 2 of LiCausi in combination with Figs. 1-11 of Sills and Figs. 1-3 of Kato disclose the semiconductor testing structure of claim 10, Figs. 1-3 of Kato further disclose wherein each of the conductive layers disposed on a lateral surface and an upper surface of each of the plurality of second metal layers (as seen in Fig. 2, 23 is disposed on the lateral surface and an upper surface of each of the plurality of 24).
Regarding claim 15, Figs. 1 and 2 of LiCausi in combination with Figs. 1-11 of Sills and Figs. 1-3 of Kato disclose the semiconductor testing structure of claim 13, Figs. 1-11 of Sills further disclose wherein the dielectric structure (together “first insulative material 18”, col. 2, line 61, and “second insulative material 20”, col. 2, line 62, form a dielectric structure, 18 and 20 of Sills are equivalent to the dielectric cap layer of LiCausi) comprises a first dielectric layer (18) and a second dielectric layer (20) over the first dielectric layer (as seen in Fig. 11, 20 is over 18).
Figs. 1-3 of Kato further disclose wherein the second metal layers are enclosed by the conductive layers (as seen in Fig. 3, 24 is enclosed by 23) and second dielectric layer of the dielectric structure (as seen in Fig. 11 of Sills, the bottom surface of 46 is enclosed by 20, thus after combining the prior art of Sills and Kato, 46 of Sills, or its equivalent 24 of Kato is enclosed by 23 of Kato and 20 of Sills).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the semiconductor testing structure as recited in the claims of the instant application.
Regarding claim 20, the prior art of LiCausi (US 10,677,855 B2) in combination with Sills et al. (US 8,021,897 B2), Kato et al. (US 9,431,412 B1), and Kamata (US 10,026,895 B2) discloses a semiconductor test structure but fails to disclose the specific claims of the instant application regarding the arrangement of the plurality of fingers and the connection portion e.g. “wherein the connecting portion extends along the second direction and at a same horizontal level of the plurality of fingers in order to connect ends of the plurality of fingers”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893