Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 1, 2025 has been entered.
Response to Arguments
Per applicants’ arguments filed 04/08/2026, with regards to independent claims 22, 26, 29, the amended claims have changed the scope of the claims and thus a new rejection based on the amendment is warranted. In particular, the change from “flushed with” to “flush with” is a change from past to present tense, indicating that the current device as it stands has two layers flush with one another. The past tense verb, “flushed with” indicates a formation process, in particular “a state, event or action that occurred before the present moment” but does not necessarily restrict the interpretation to the current moment. The past tense has implications for the present and future but those implications are not limited to the scope and definition of the coined term (i.e. if I formed something, it does not mean it currently has the form in which it was formed, rather it could be formed in one way and the implication is that final, and present state, of said formed thing is now different than the formation process). Thus, the term “flush with” and “flushed with” carry different semantic ranges, where “flush with” limits (and thus changes) the scope of the claim. Upon further search and consideration, a new rejection is formulated below. Some of the second sources remain the same but are not used in relation to the amended portions nor to what is argued by the applicant as deficiencies.
Regarding claim 34, the argument is found persuasive and upon further search and consideration no prior art rejection can formally be made such that it would be obvious to render the claimed device in the present application.
Allowable Subject Matter
Claim 34 is allowed. In particular, the prior art does not teach or render obvious wherein the semiconductor layer has an upper surface and four lateral surfaces, and the thermal dissipation layer covers the upper surface and the four lateral surfaces of the semiconductor layer, wherein the thermal dissipation layer and the semiconductor layer each has a lower surface, and the lower surface of the thermal dissipation layer and the lower surface of the semiconductor layer are substantially aligned with each other and in the combination as claimed. O’Connor et al does teach a thermal dissipation layer on top of the semiconductor portion of the composite semiconductor die, and England et al does teach a thermal dissipation layer surrounding the semiconductor die, but England et al does not teach that the lower surfaces of the thermal dissipation layer and the semiconductor die are substantially aligned. Additionally, this is not a matter of changing size or shape as the length of the heat dissipation layer does have a materially effect on the function of the device, a longer heat dissipation layer in England et al would transfer heat to the lower semiconductor die [by the way it is structured] so the gap is necessary. Thus, claim 34 is in a state of allowance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 22-23, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by O’Connor et al (US 20020145194).
O’Conner et al teaches
[claim 22] A heterogeneous semiconductor structure, comprising: a substrate (paragraph 0004, figure 3B, where the IC [element 40] can be placed on a substrate]);
and a composite semiconductor chip over the substrate (paragraph 0026, figure 3B, where element 40 is the composite semiconductor chip [also known as a die/IC in the art], made up of composite material – specifically elements 110 and 100);
wherein the composite semiconductor chip includes a thermal dissipation side and a semiconductor side (paragraph 0041, figure 3B, where element 100 is the thermal dissipation side of the semiconductor die [element 40]);
wherein the thermal dissipation side has a thermal conductivity which is equal to or greater than that of copper (paragraph 0048, figure 3B, where element 100 may be made of copper, thus having a thermal conductivity equal to copper);
wherein a lateral surface of the thermal dissipation side and a lateral surface of the semiconductor side are flush with each other (paragraph 0041, figure 3B, where layer 100 has lateral surfaces that are flush with the semiconductor portion of the composite device [elements 100 and 110 are flush with each other on their lateral surfaces]).
[claim 23] The heterogeneous semiconductor structure in claim 22, further comprising: a heat spreader over the thermal dissipation side of the composite semiconductor chip (paragraph 0026, figure 3B, where element 60 is the heat spreader over the thermal dissipation side [element 100] of the composite semiconductor chip [element 40]);
and a heat sink over the heat spreader (paragraph 0026, figure 3B, where element 80 is a heat sink over the heat spreader [element 60]).
[claim 26] A heterogeneous semiconductor structure, comprising: a substrate (paragraph 0004, figure 3B, where the IC [element 40] can be placed on a substrate]);
and a composite semiconductor chip over the substrate (paragraph 0026, figure 3B, where element 40 is the composite semiconductor chip [also known as a die/IC in the art], made up of composite material – specifically elements 110 and 100);
wherein the composite semiconductor chip includes a thermal dissipation layer and a semiconductor layer (paragraph 0042, figure 3B, where element 40 is the composite semiconductor chip and includes a thermal dissipation layer [element 100] and a semiconductor layer [element 110]),
the thermal dissipation layer directly contacts to the semiconductor layer without any adhesive material between the thermal dissipation layer and the semiconductor layer (paragraphs 0041-0043, where element 100 [thermal dissipation layer] directly contacts the semiconductor layer [element 110] without any adhesive material between the two);
wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper (paragraph 0048, figure 3B, where the thermal dissipation layer [element 100] may be made of copper, thus having a thermal conductivity equal to copper);
wherein a lateral surface of the thermal dissipation layer and a lateral surface of the semiconductor layer are flush with each other (paragraph 0042, figure 3B, where the lateral surfaces of the thermal dissipation layer [element 100] are flush with the lateral surfaces of the semiconductor portion [element 110]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Connor et al (US 20020145194) in view of Chang (US 20220384359).
O’Conner et al teaches all of the limitations of the parent claim, claim 22, but does not specifically disclose
[claim 24] the heterogeneous semiconductor structure in claim 22, further comprising another semiconductor chip bonded to the semiconductor side of the composite semiconductor chip.
[claim 25] the heterogeneous semiconductor structure in claim 22, further comprising another composite semiconductor chip bonded to the composite semiconductor chip.
[claim 27] the heterogeneous semiconductor structure in claim 26, further comprising another semiconductor chip electrically connected to the composite semiconductor chip, wherein the semiconductor layer of the composite semiconductor chip includes a first plurality of active circuits and another semiconductor chip includes a second plurality of active circuits.
[claim 28] the heterogeneous semiconductor structure in claim 26, further comprising another composite semiconductor chip electrically connected to the composite semiconductor chip, wherein another composite semiconductor chip comprises another thermal dissipation layer and another semiconductor layer bonded to the another thermal dissipation layer.
However, a different embodiment in Chang does teach
[claim 24] the heterogeneous semiconductor structure in claim 22, further comprising another semiconductor chip bonded to the semiconductor side of the composite semiconductor chip (figure 2, element 120A [another semiconductor chip] is connected to element 120C [a first semiconductor chip, having the semiconductor side on the bottom side and the thermal dissipation layer on the top half]).
[claim 25] the heterogeneous semiconductor structure in claim 22, further comprising another composite semiconductor chip bonded to the composite semiconductor chip (figure 2, element 120A and element 160 [another semiconductor chip, composite in nature] is connected to element 120C [a first semiconductor chip, having the semiconductor side on the bottom side and the thermal dissipation layer on the top half]).
[claim 27] the heterogeneous semiconductor structure in claim 26, further comprising another semiconductor chip electrically connected to the composite semiconductor chip, wherein the semiconductor layer of the composite semiconductor chip includes a first plurality of active circuits and another semiconductor chip includes a second plurality of active circuits (figure 2, paragraph 0024, element 120A and element 160 [another semiconductor chip, composite in nature] is connected to element 120C [a first semiconductor chip, having the semiconductor side on the bottom side and the thermal dissipation layer on the top half], and each chip contains integrated circuits which are active circuits [both 120A and 120C contain these circuits]).
[claim 28] the heterogeneous semiconductor structure in claim 26, further comprising another composite semiconductor chip electrically connected to the composite semiconductor chip, wherein another composite semiconductor chip comprises another thermal dissipation layer and another semiconductor layer bonded to the another thermal dissipation layer (figure 2, element 120A and element 160 [another semiconductor chip, composite in nature] is connected to element 120C and element 162 [a first semiconductor chip, having the semiconductor side on the bottom side and the thermal dissipation layer on the top half], where both chips contain a semiconductor portion and a thermal dissipation layer and are connected together).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified O’Connor to incorporate Chang in order to produce a multi-level chip structure so as to maximize density, providing multiple chips in one package all with the same characteristics of having good heat dissipation thus aiding in the electronic performance and quality of the device (paragraph 0009).
Claim(s) 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over O’Connor et al (US 20020145194) in view of Bathan et al (US 20100078834).
[claim 29] A heterogeneous semiconductor structure, comprising: a substrate (paragraph 0004, figure 3B, where the IC [element 40] can be placed on a substrate]);
and a composite semiconductor chip over the substrate (paragraph 0026, figure 3B, where element 40 is the composite semiconductor chip [also known as a die/IC in the art], made up of composite material – specifically elements 110 and 100);
wherein the composite semiconductor chip includes a thermal dissipation side and a semiconductor side (paragraph 0041, figure 3B, where element 100 is the thermal dissipation side of the semiconductor die [element 40]);
wherein the thermal dissipation side has a thermal conductivity which is equal to or greater than that of copper (paragraph 0048, figure 3B, where element 100 may be made of copper, thus having a thermal conductivity equal to copper);
wherein a lateral surface of the thermal dissipation side and a lateral surface of the semiconductor side are flush with each other (paragraph 0041, figure 3B, where layer 100 has lateral surfaces that are flush with the semiconductor portion of the composite device [elements 100 and 110 are flush with each other on their lateral surfaces]).
However, O’Conner et al does not specifically disclose
[claim 29] and a molding compound covering sidewalls of the thermal dissipation layer and the semiconductor layer
However, Bathan et al does teach
[claim 29] and a molding compound covering sidewalls of the thermal dissipation layer and the semiconductor layer (paragraph 0048, figure 4D, where element 128 and 124 replaces element 40 of O’Connor et al [that is the composite semiconductor die], where element 136 is the molding compound covering the sidewalls of the thermal dissipation layer and semiconductor layer [where element 100 of O’Conner et al [thermal dissipation layer] is read onto element 124 of Bathan et al, and where element 110 of O’Connor et al [semiconductor material] is read onto element 128 of Bathan et al, thus molding compound covers sidewall of both).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of O’Connor et al to incorporate the teachings of Bathan et al to provide a molding compound around the die to ensure structural stability and thus improving the overall stability of the device.
Claim(s) 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over O’Connor et al (US 20020145194) in view of Bathan et al (US 20100078834) and in further view of Chang (US 20220384359).
O’Connor et al as modified teaches all of the limitations of the parent claim, claim 29, but does not specifically disclose
[claim 30] The heterogeneous semiconductor structure in claim 29, further comprising another semiconductor chip electrically connected to the composite semiconductor chip, wherein the composite semiconductor chip includes a first plurality of through vias and the another semiconductor chip includes a plurality of active circuits.
However, Chang does teach
[claim 30] The heterogeneous semiconductor structure in claim 29, further comprising another semiconductor chip electrically connected to the composite semiconductor chip (figure 2, paragraph 0054, where element 120C is the first composite semiconductor die read into from O’Connor et al, where element 40 of O’Connor et al replaces element 120C of Chang, which is electrically connected to another composite semiconductor chip, element 120A),
wherein the composite semiconductor chip includes a first plurality of through vias and the another semiconductor chip includes a plurality of active circuits (figure 2, paragraph 0050, where element 120C [composite semiconductor chip] includes a plurality of through vias [element 180] that connect the first chip to the second chip [element 120C to element 120A], and the another semiconductor chip [element 120A] includes a plurality of active circuits).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of O’Connor et al as modified with the teachings of Chang in order to incorporate more circuits in a small space to maximize spatial efficiency and effectiveness of the semiconductor device by connecting devices together in one device instead of having external wires connecting the two.
Regarding claim 31,
O’Connor et al as modified teaches
[claim 31] wherein the another composite semiconductor chip includes a thermal dissipation side and a semiconductor side (paragraph 0041, figure 3B, where element 100 is the thermal dissipation side of the semiconductor die [element 40]);
the thermal dissipation layer directly contacts to the semiconductor layer without any adhesive material between the thermal dissipation layer and the semiconductor layer (paragraphs 0041-0043, where element 100 [thermal dissipation layer] directly contacts the semiconductor layer [element 110] without any adhesive material between the two);
Per MPEP VI. REVERSAL, DUPLICATION, OR REARRANGEMENT OF PARTS
B. Duplication of Parts
In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) (Claims at issue were directed to a water-tight masonry structure wherein a water seal of flexible material fills the joints which form between adjacent pours of concrete. The claimed water seal has a "web" which lies in the joint, and a plurality of "ribs" projecting outwardly from each side of the web into one of the adjacent concrete slabs. The prior art disclosed a flexible water stop for preventing passage of water between masses of concrete in the shape of a plus sign (+). Although the reference did not disclose a plurality of ribs, the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced.).
In the present case, Chang et al discloses two semiconductor chips electrically connected with through vias, that is figure 2, paragraphs 0050-0054 where element 120C is the first semiconductor chip and element 120A is the second semiconductor chip. It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to have modified the teachings of O’Connor et al as modified to duplicate the composite semiconductor chip of O’Connor et al [element 40] in the formation as shown in Chang, figure 2. Where element 120C would be the first composite semiconductor chip as element 40 of O’Connor et al is read onto element 120C, additionally, element 40 of O’Connor et al could also be read onto element 120A as a duplication of parts. Where both have through vias (element 180) connecting the first composite semiconductor chip and the second semiconductor chip. Thus, according to O’Connor et al the second composite semiconductor chip would also have all of the properties of the first. Duplicating the parts would allow one of ordinary skill in the art to connect two semiconductor dies integrated into one total device instead of connecting them through external wires, thus maximizing spatial efficiency.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET.
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/ANDREW JOHN ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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