Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 1, 2025 has been entered.
Response to Arguments
Per applicants’ arguments filed 10/01/2025, applicants’ arguments on pages 14-18 regarding independent claims 22, 26, and 29 include an amendment which is argued that the prior art lacks teaching the features of the amendment. While the arguments are correct that the previous rejection does not include the new limitations present, a new rejection is presented below after further search and consideration with a new reference.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22-28 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220384359 A1), Jain et al (US 20170223839 A1) and in further view of Liff et al (US 11049791 B1).
Regarding claims 22 and 26, Chang teaches
[claim 22] a heterogeneous semiconductor structure, comprising: a substrate; and a composite semiconductor chip over the substrate; wherein the composite semiconductor chip includes a thermal dissipation side and a semiconductor side (figure 1, paragraphs 0040-0041, where the substrate is element 110, the composite semiconductor chip includes a semiconductor side designated by element 122 and a thermal dissipation side designated by element 160).
[claim 26] a heterogeneous semiconductor structure, comprising: a substrate; and a composite semiconductor chip over the substrate; wherein the composite semiconductor chip includes a thermal dissipation layer and a semiconductor layer, the thermal dissipation layer directly contacts to the semiconductor layer without any adhesive material between the thermal dissipation layer and the semiconductor layer (figure 1, paragraphs 0040-0041, where the substrate is element 110, the composite semiconductor chip includes a semiconductor side designated by element 122 and a thermal dissipation side designated by element 160, no adhesive is used between the thermal dissipation layer and the semiconductor layer).
However, Chang does not specifically disclose
[claims 22 & 26] wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper; wherein a lateral surface of the thermal dissipation side and a lateral surface of the semiconductor side are flushed with each other.
However, Jain et al does teach
[claims 22 & 26] wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper (paragraph 0019, figures 1A and 1B where element 120 is the thermal dissipation layer on the device and is made of copper).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Chang to incorporate the teachings of Jain et al in order to dissipate more heat by attaching a material, such as copper or one that has greater dissipation, in order to allow the device to generate more heat and still function properly, thus maximizing efficiency of the device and performance.
However, Chang as modified above does not specifically disclose
[claims 22 & 26] wherein a lateral surface of the thermal dissipation side and a lateral surface of the semiconductor side are flushed with each other.
However, Liff et al does teach
[claims 22 & 26] wherein a lateral surface of the thermal dissipation side and a lateral surface of the semiconductor side are flushed with each other (figure 1, col 4 lines 58-65 and col 5 lines 7-12, where element 106 is the thermal dissipation portion and element 102 is the IC, where they each have a lateral side flush with one another).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Chang as modified to incorporate the teachings of Liff et al in order to maximize heat dissipation by making the IC flush with the heat dissipation layer/section in order to let the IC cool quicker and more efficiently, making the device more efficient overall.
Regarding claim 23, Chang further discloses
[claim 23] the heterogeneous semiconductor structure in claim 22, further comprising: a heat spreader over the thermal dissipation side of the composite semiconductor chip; and a heat sink over the heat spreader (figure 1, paragraphs 0024 and 0054, element 240 is the heat spreader and element 300 is the heat sink all over the thermal dissipation side).
Regarding claims 24-25, 27 and 28,
Chang as modified in the embodiment described above teaches all of the limitations of the parent claims, claims 22 and 26, but do not specifically disclose
[claim 24] the heterogeneous semiconductor structure in claim 22, further comprising another semiconductor chip bonded to the semiconductor side of the composite semiconductor chip.
[claim 25] the heterogeneous semiconductor structure in claim 22, further comprising another composite semiconductor chip bonded to the composite semiconductor chip.
[claim 27] the heterogeneous semiconductor structure in claim 26, further comprising another semiconductor chip electrically connected to the composite semiconductor chip, wherein the semiconductor layer of the composite semiconductor chip includes a first plurality of active circuits and another semiconductor chip includes a second plurality of active circuits.
[claim 28] the heterogeneous semiconductor structure in claim 26, further comprising another composite semiconductor chip electrically connected to the composite semiconductor chip, wherein another composite semiconductor chip comprises another thermal dissipation layer and another semiconductor layer bonded to the another thermal dissipation layer.
However, a different embodiment in Chang does teach
[claim 24] the heterogeneous semiconductor structure in claim 22, further comprising another semiconductor chip bonded to the semiconductor side of the composite semiconductor chip (figure 2, element 120A [another semiconductor chip] is connected to element 120C [a first semiconductor chip, having the semiconductor side on the bottom side and the thermal dissipation layer on the top half]).
[claim 25] the heterogeneous semiconductor structure in claim 22, further comprising another composite semiconductor chip bonded to the composite semiconductor chip (figure 2, element 120A and element 160 [another semiconductor chip, composite in nature] is connected to element 120C [a first semiconductor chip, having the semiconductor side on the bottom side and the thermal dissipation layer on the top half]).
[claim 27] the heterogeneous semiconductor structure in claim 26, further comprising another semiconductor chip electrically connected to the composite semiconductor chip, wherein the semiconductor layer of the composite semiconductor chip includes a first plurality of active circuits and another semiconductor chip includes a second plurality of active circuits (figure 2, paragraph 0024, element 120A and element 160 [another semiconductor chip, composite in nature] is connected to element 120C [a first semiconductor chip, having the semiconductor side on the bottom side and the thermal dissipation layer on the top half], and each chip contains integrated circuits which are active circuits [both 120A and 120C contain these circuits]).
[claim 28] the heterogeneous semiconductor structure in claim 26, further comprising another composite semiconductor chip electrically connected to the composite semiconductor chip, wherein another composite semiconductor chip comprises another thermal dissipation layer and another semiconductor layer bonded to the another thermal dissipation layer (figure 2, element 120A and element 160 [another semiconductor chip, composite in nature] is connected to element 120C and element 162 [a first semiconductor chip, having the semiconductor side on the bottom side and the thermal dissipation layer on the top half], where both chips contain a semiconductor portion and a thermal dissipation layer and are connected together).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the first embodiment of Chang as modified to incorporate the other embodiment of Chang in order to produce a multi-level chip structure so as to maximize density, providing multiple chips in one package all with the same characteristics of having good heat dissipation thus aiding in the electronic performance and quality of the device (paragraph 0009).
Claim(s) 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220384359 A1) in view of Knickerbocker et al (US 20210366789 A1) and Liff et al (US 11049791 B1).
Chang as modified teaches
[claim 29] a heterogeneous semiconductor structure, comprising: a substrate; and a composite semiconductor chip over the substrate; wherein the composite semiconductor chip includes a thermal dissipation layer, and a semiconductor layer (figure 2, paragraphs 0050-0052, where the substrate is element 100, the composite semiconductor chip includes a semiconductor side designated by element 120C and a thermal dissipation side designated by element 162).
However, Chang does not specifically disclose
[claim 29] and a molding compound covering sidewalls of the thermal dissipation layer and the semiconductor layer; wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper; wherein a lateral surface of the thermal dissipation layer and a lateral surface of the semiconductor layer are flushed with each other.
However, Knickerbocker et al does teach
[claim 29] and a molding compound covering sidewalls of the thermal dissipation layer and the semiconductor layer (figure 1, element 170 is the molding compound, paragraphs 0011 and 0063).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Chang to incorporate the teachings of Knickerbocker et al to use a molding layer that covers both the thermal dissipation layer and the semiconductor layer in order to create a more physically stable stacked die structure preserving electrical connections (paragraph 0011), as Chang has a ceramic layer and spaces (elements 200, SP1 and SP2) which gives some stability but to have used a molding layer in the entirety would bring greater electrical and thermal stability to the overall structure.
However, Chang as modified does not specifically disclose
[claim 29] wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper; wherein a lateral surface of the thermal dissipation layer and a lateral surface of the semiconductor layer are flushed with each other.
However, Liff et al does teach
[claim 29] wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper (figure 1, col 6 line 59 – col 7 line 6, where the thermal dissipation layer is element 106 and can be made of boron nitride which has a higher thermal conductivity than copper).
wherein a lateral surface of the thermal dissipation layer and a lateral surface of the semiconductor layer are flushed with each other (figure 1, col 4 lines 58-65 and col 5 lines 7-12, where element 106 is the thermal dissipation portion and element 102 is the IC, where they each have a lateral side flush with one another).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Chang as modified to incorporate the teachings of Jain et al in order to dissipate more heat by attaching a material, such as copper or one that has greater dissipation, in order to allow the device to generate more heat and still function properly, thus maximizing efficiency of the device and performance.
Regarding claim 30, Chang as modified discloses the heterogeneous semiconductor structure in claim 29, further comprising another semiconductor chip electrically connected to the composite semiconductor chip, wherein the composite semiconductor chip includes a first plurality of through vias and the another semiconductor chip includes a plurality of active circuits (figure 2, element 120A and 160 comprise the second semiconductor chip and it includes a plurality of through vias labeled element 184, where element 120A contains active circuits as it is an IC [paragraph 0021]).
Regarding claim 31, Chang as modified discloses the heterogeneous semiconductor structure in claim 29, further comprising another composite semiconductor chip electrically connected to the composite semiconductor chip, wherein the composite semiconductor chip includes a first plurality of through vias, the another composite semiconductor chip includes another thermal dissipation layer and another semiconductor layer, the another thermal dissipation layer directly contacts to the another semiconductor layer without any adhesive material between the another thermal dissipation layer and the another semiconductor layer (figure 2, element 120A and 160 comprise the second semiconductor chip and it includes a plurality of through vias labeled element 184 which electrically connect to the first semiconductor chip [element 120C], where the thermal dissipation layer [element 160] does not have an adhesive layer or another layer between it and the semiconductor portion via an adhesive to the semiconductor die [element 120A]).
Claim(s) 34 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 20220384359 A1) in view of England et al (US 10818570 B1) and in further view of Liff et al (US 11049791 B1)
Chang teaches
[claim 34] a heterogeneous semiconductor structure, comprising: a composite semiconductor chip over the substrate; wherein the composite semiconductor chip includes a thermal dissipation side and a semiconductor side (figure 1, paragraphs 0040-0041, the composite semiconductor chip includes a semiconductor side designated by element 122 and a thermal dissipation side designated by element 160).
However, Chang does not specifically disclose
[claim 34] wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper, wherein the semiconductor layer has an upper surface and four lateral surfaces, and the thermal dissipation side covers the upper surface and the four lateral surfaces of the semiconductor side; wherein the thermal dissipation layer and the semiconductor layer each has a lower surface, and the lower surface of the thermal dissipation layer and the lower surface of the semiconductor layer are substantially aligned with each other.
However, England et al does teach
[claim 34] wherein the semiconductor layer has an upper surface and four lateral surfaces, and the thermal dissipation layer covers the four lateral surfaces of the semiconductor side (figure 6, col 7 lines 36-52, where element 608 is the thermal dissipation layer and element 604 is the semiconductor layer. The semiconductor layer has an upper surface and four lateral surfaces, and the thermal dissipation layer covers the four lateral surfaces);
wherein the thermal dissipation layer and the semiconductor layer each has a lower surface, and the lower surface of the thermal dissipation layer and the lower surface of the semiconductor layer are substantially aligned with each other (figure 6, col 7 lines 35-52, where element 608 is the thermal dissipation layer and element 604 is the semiconductor layer, and each have a lower surface substantially aligned with one another, which is equivalent to the top surface of the element 602).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Chang as modified to incorporate the teachings of England et al to use a thermal dissipation layer that covers the semiconductor layer in order to create more ways for heat to dissipate, by laterally surrounding the semiconductor die, making the die more thermally efficient and hence increasing its performance.
However, Chang as modified does not specifically disclose
[claim 34] wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper, and the thermal dissipation side covers the upper surface
However, Liff et al does teach
[claim 34] wherein the thermal dissipation layer has a thermal conductivity which is equal to or greater than that of copper (figure 1, col 6 line 59 – col 7 line 6, where the thermal dissipation layer is element 106 and can be made of boron nitride which has a higher thermal conductivity than copper),
and the thermal dissipation side covers the upper surface (figure 1, col 4 lines 58-65 and col 5 lines 7-12, where element 106 is the thermal dissipation portion and element 102 is the IC, where element 106 [thermal dissipation layer] covers an upper surface of the semiconductor portion [element 102]).
It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Chang as modified to incorporate the teachings of Liff et al in order to maximize heat dissipation by making the IC flush with the heat dissipation layer/section in order to let the IC cool quicker and more efficiently making the device more efficient overall.
Conclusion
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/ANDREW ZABEL/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818