DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Discussion of 102/103 Rejections, filed 10/14/2025, with respect to the rejection(s) of claims 1, 10 and 21 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Onuki, Tatsuya et al (Pub No. US20220328486A1) (hereinafter, Onuki) in view of Kato, Kiyoshi et al. (Pub No. US 20200144310 A1) (hereinafter, Kato).
6. Applicant’s arguments, see Discussion of Claim 4, filed 10/14/2025, with respect to the rejection of claim 4 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Onuki, Tatsuya et al (Pub No. US20220328486A1) (hereinafter, Onuki).
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1-3, 6-11, 13-14, 21-22 and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Onuki, Tatsuya et al (Pub No. US 20220328486 A1) (hereinafter, Onuki), and further in view of Kato, Kiyoshi et al. (Pub No. US 20200144310 A1) (hereinafter, Kato).
Onuki, Fig 2: Semiconductor device, first embodiment
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Re Claim 1, (Currently Amended) Onuki teaches a method of forming a semiconductor device (Figures 2 and 4B-12B), comprising:
forming a gate electrode (Conductor; 248; Fig 2; ¶[0142]) within an insulating layer (Insulator; 224; Fig 2; ¶[0070]) that overlies a substrate (Lies below insulators 224; (Not Shown); ¶[0069]);
forming a gate dielectric layer (Oxide; 230a/230b; Fig 2; ¶[0071]) over the gate electrode;
forming a semiconductor channel layer (Conductor; 242; Fig 2; ¶[0160]; Note: Conductor 242 may be ruthenium oxide, an oxide containing strontium or ruthenium, or an oxide containing lanthanum and nickel) over the gate dielectric layer;
forming a dielectric layer (Insulator; 280; Fig 8B; ¶[0073]) over the semiconductor channel layer;
patterning (Forming openings, ¶[0308]) the dielectric layer and the semiconductor channel layer, so as to form first and second openings (Openings; Fig 9B; ¶[0308]) that expose portions (Openings expose portions of Oxide 230b; Fig 9B; ¶[0308]) of the gate dielectric layer;
forming an interfacial layer (Insulating film; 250A; Fig 10B; ¶[0322]) conformally on sidewalls and bottoms of the first and second openings (Insulating film deposited on bottom and side surfaces of openings; Fig 10B; ¶[0324]) ;
forming a semiconductor layer (Conductor; 260a; Fig 11B; ¶[0175]; Note: Conductor 260a is considered an oxide layer as it functions to inhibit the diffusion of oxygen. Per paragraph ¶[0037] of Applicant's disclosure buffer layer (second oxide semiconductor layer) is composed of conductive materials such as Ga, Zn, W, Sn, etc.) over the interfacial layer in the first and second openings; and
forming a metal layer (Conductor; 260b; Fig 12B; ¶[0176]) over the semiconductor layer in the first and second openings.
However, Onuki does not teach wherein bottom surfaces of the first and second openings are substantially flush with a top surface of the gate dielectric layer.
In the same field of endeavor, Kato teaches wherein bottom surfaces of the first and second openings (Openings in layer 280; Fig 15B) are substantially flush (Coplanar) with a top surface (Top surface of 230a/230b; Figs 8B/15B) of the gate dielectric layer (Oxides; 230a/230b; Figs 8B/15B; ¶[0093]).
Kato, Fig 15B: Semiconductor device with openings flush with gate dielectric layer
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It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device as disclosed by Onuki by making bottom surfaces of the first and second openings substantially flush with a top surface of the gate dielectric layer, as disclosed by Kato. One of ordinary skill in the art would have been motivated to make this modification because the capacitors formed above the gate dielectric layers may have a mismatch in capacitance if the openings for the capacitors protrude into the gate dielectric layers, whereas by etching the openings to be flush with the gate dielectric layers, the capacitance may be set to an optimal level if the projected areas of capacitor are equivalent, as suggested by Kato (¶¶[0173–0174]).
Re Claim 2, (Previously Presented) Onuki teaches the method of claim 1, wherein the interfacial layer (Insulating film; 250A; Fig 10B; ¶[0322]) is in physical contact (Insulating film 250A contacts upper surface of oxide 230b and conductor 260a; Figs 2/10B) with the gate dielectric layer (Oxide; 230a/230b; Fig 2; ¶[0071]) and the semiconductor layer (Conductor; 260a; Fig 11B; ¶[0175]).
Re Claim 3, (Original) Onuki teaches the method of claim 1, wherein the interfacial layer (Insulating film; 250A; Fig 10B; ¶[0327]) comprises TIN, WCN, W, TaN, Ru, Al, InO, IZO, ITO or a combination thereof (Insulating film 250A comprises one kind or two or more metal oxides W (Tungsten), Al (Aluminum), and additionally can be made of same materials as Oxide 230 per ¶[0097], comprising IZO (Indium Zinc Oxide) ITO (Indium Tin Oxide); ¶[0327]) .
Re Claim 6, (Previously Presented) Onuki teaches the method of claim 1, further comprising forming a blocking layer (Oxide; 243a/243b/243c; Fig 2; ¶[0071]) between the gate dielectric layer (Oxide; 230a/230b; Fig 2; ¶[0071]) and the semiconductor channel layer (Conductor; 242; Fig 2; ¶[0160]).
Re Claim 7, (Original) Onuki teaches the method of claim 6, wherein the blocking layer (Oxide; 243a/243b/243c; Fig 2; ¶[0071]) comprises hafnium oxide, zirconium oxide, gallium oxide, tungsten oxide, aluminum oxide, silicon oxide, or a combination thereof (Gallium oxide/Aluminum oxide; ¶[0158]).
Re Claim 8, (Previously Presented) Onuki teaches the method of claim 1, further comprising performing a plasma treatment (High-density plasma with use of a microwave, in a state where conductor 242 is provided over oxide 230b; ¶[0110]) after forming the gate dielectric layer (Oxide; 230a/230b; Fig 2; ¶[0071]) and before forming the semiconductor channel layer (Conductor; 242; Fig 2; ¶[0160]).
Re Claim 9, (Original) Onuki teaches the method of claim 8, wherein the plasma treatment (High-density plasma with use of a microwave, in a state where conductor 242 is provided over oxide 230b; ¶[0110]) comprises ozone, 02, N20, NH3, N2 or a combination thereof (Oxygen gas; O2; ¶[0111])
Re Claim 10, (Currently Amended) Onuki teaches a method of forming a semiconductor device, comprising:
forming a gate electrode (Conductor; 248; Fig 2; ¶[0142]) within an insulating layer (Insulator; 224; Fig 2; ¶[0070]) that overlies a substrate (Lies below insulators 224; (Not Shown); ¶[0069]);
forming a gate dielectric layer (Oxide; 230a/230b; Fig 2; ¶[0071]) over the gate electrode;
forming a blocking layer (Oxide; 243a/243b/243c; Fig 2; ¶[0071]) on the gate dielectric layer;
forming a semiconductor channel layer (Conductor; 242; Fig 2; ¶[0160]; Note: Conductor 242 may be ruthenium oxide, an oxide containing strontium or ruthenium, or an oxide containing lanthanum and nickel) over the blocking layer;
forming a dielectric layer (Insulator; 280; Fig 8B; ¶[0073]) over the semiconductor channel layer;
patterning (Forming openings, ¶[0308]) the dielectric layer, the first oxide semiconductor layer and the blocking layer, so as to form first and second openings (Openings; Fig 9B; ¶[0308]) that expose portions (Openings expose portions of Oxide 230b; Fig 9B; ¶[0308]) of the gate dielectric layer;
forming a semiconductor layer (Conductor; 260a; Fig 11B; ¶[0175]; Note: Conductor 260a is considered an oxide layer as it functions to inhibit the diffusion of oxygen. Per paragraph ¶[0037] of Applicant's disclosure the buffer layer (second oxide semiconductor layer) is composed of conductive materials such as Ga, Zn, W, Sn, etc.) in the first and second openings; and
forming a metal layer (Conductor; 260b; Fig 12B; ¶[0176]) over the semiconductor layer in the first and second openings.
However, Onuki does not teach wherein bottom surfaces of the first and second openings are substantially flush with a top surface of the gate dielectric layer.
In the same field of endeavor, Kato teaches wherein bottom surfaces of the first and second openings (Openings in layer 280; Fig 15B) are substantially flush (Coplanar) with a top surface (Top surface of 230a/230b; Figs 8B/15B) of the gate dielectric layer (Oxides; 230a/230b; Figs 8B/15B; ¶[0093]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device as disclosed by Onuki by making bottom surfaces of the first and second openings substantially flush with a top surface of the gate dielectric layer, as disclosed by Kato. One of ordinary skill in the art would have been motivated to make this modification because the capacitors formed above the gate dielectric layers may have a mismatch in capacitance if the openings for the capacitors protrude into the gate dielectric layers, whereas by etching the openings to be flush with the gate dielectric layers, the capacitance may be set to an optimal level if the projected areas of capacitor are equivalent, as suggested by Kato (¶¶[0173–0174]).
Re Claim 11, (Original) Onuki teaches the method of claim 10, wherein the blocking layer (Oxide; 243a/243b/243c; Fig 2; ¶[0071]) comprises hafnium oxide, zirconium oxide, gallium oxide, tungsten oxide, aluminum oxide, silicon oxide, or a combination thereof (Gallium oxide/Aluminum oxide; ¶[0158]).
Re Claim 13, (Previously Presented) Onuki teaches the method of claim 10, further comprising forming an interfacial layer (Insulating film; 250A; Fig 10B; ¶[0322]) in the first and second openings (Insulating film deposited on bottom and side surfaces of openings; Fig 10B; ¶[0324]) before forming the semiconductor layer (Conductor; 260a; Fig 11B; ¶[0175]).
Re Claim 14, (Original) Onuki teaches the method of claim 13, wherein the interfacial layer (Insulating film; 250A; Fig 10B; ¶[0322]) comprises TiN, WCN, W, TaN, Ru, Al, InO, IZO, ITO or a combination thereof (Insulating film 250A comprises one kind or two or more metal oxides W (Tungsten), Al (Aluminum), and additionally can be made of same materials as Oxide 230 per ¶[0097], comprising IZO (Indium Zinc Oxide) ITO (Indium Tin Oxide); ¶[0327]).
Re Claim 21, (Currently Amended) Onuki teaches a method of forming a semiconductor device, comprising:
forming a gate electrode (Conductor; 248; Fig 2; ¶[0142]) within an insulating layer (Insulator; 224; Fig 2; ¶[0070]) over a transistor (300; Fig 18; ¶[0432]; Specifically, transistor 200a and transistor 200b are provided above transistor 300, where the gate electrode of the memory 400 is located per ¶[0432]) ;
forming a gate dielectric layer (Oxide; 230a/230b; Fig 2; ¶[0071]) over the gate electrode;
forming a semiconductor channel layer (Conductor; 242; Fig 2; ¶[0160]; Note: Conductor 242 may be ruthenium oxide, an oxide containing strontium or ruthenium, or an oxide containing lanthanum and nickel) over the gate dielectric layer;
forming a dielectric layer (Insulator; 280; Fig 8B; ¶[0073]) over the semiconductor channel layer;
forming first and second openings (Openings; Fig 9B; ¶[0308]) in the dielectric layer and the semiconductor channel layer;
forming a semiconductor layer (Conductor; 260a; Fig 11B; ¶[0175]; Note: Conductor 260a is considered an oxide layer as it functions to inhibit the diffusion of oxygen. Per paragraph ¶[0037] of Applicant's disclosure the buffer layer (second oxide semiconductor layer) is composed of conductive materials such as Ga, Zn, W, Sn, etc.) in the first and second openings; and
forming a metal layer (Conductor; 260b; Fig 12B; ¶[0176]) over the semiconductor layer in the first and second openings.
However, Onuki does not teach wherein bottom surfaces of the first and second openings are substantially flush with a top surface of the gate dielectric layer.
In the same field of endeavor, Kato teaches wherein bottom surfaces of the first and second openings (Openings in layer 280; Fig 15B) are substantially flush (Coplanar) with a top surface (Top surface of 230a/230b; Figs 8B/15B) of the gate dielectric layer (Oxides; 230a/230b; Figs 8B/15B; ¶[0093]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device as disclosed by Onuki by making bottom surfaces of the first and second openings substantially flush with a top surface of the gate dielectric layer, as disclosed by Kato. One of ordinary skill in the art would have been motivated to make this modification because the capacitors formed above the gate dielectric layers may have a mismatch in capacitance if the openings for the capacitors protrude into the gate dielectric layers, whereas by etching the openings to be flush with the gate dielectric layers, the capacitance may be set to an optimal level if the projected areas of capacitor are equivalent, as suggested by Kato (¶¶[0173–0174]).
Re Claim 22, (Previously Presented) Onuki teaches the method of claim 21, further comprising, after forming the first and second openings (Openings; Fig 9B; ¶[0308]) and before forming the semiconductor layer (Conductor; 260a; Fig 11B; ¶[0175]), forming an interfacial layer (Insulating film; 250A; Fig 10B; ¶[0322]) conformally on sidewalls and bottoms of the first and second openings (Insulating film deposited on bottom and side surfaces of openings; Fig 10B; ¶[0324]).
Re Claim 24, (Previously Presented) Onuki teaches the method of claim 21, further comprising forming a blocking layer (Oxide; 243a/243b/243c; Fig 2; ¶[0071]) between the gate dielectric layer (Oxide; 230a/230b; Fig 2; ¶[0071]) and the semiconductor channel layer (Conductor; 242; Fig 2; ¶[0160]).
Re Claim 25, (Previously Presented) Onuki teaches the method of claim 21, further comprising performing a plasma treatment (High-density plasma with use of a microwave, in a state where conductor 242 is provided over oxide 230b; ¶[0110]) after forming the gate dielectric layer (Oxide; 230a/230b; Fig 2; ¶[0071]) and before forming the first oxide semiconductor layer (Conductor; 242; Fig 2; ¶[0160]).
Re Claim 26, (Previously Presented) Onuki teaches the method of claim 21, further comprising forming a memory cell (Memory cells; 100a/100b and 200a/200b; Fig 17A; per ¶[0413]) connected transistor 200a and capacitor 100a, and transistor 200b and capacitor 100b, can function as memory cells of the memory device) electrically connected to the metal layer (Conductor; 260b; Fig 17A; ¶[0176]).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Onuki, Tatsuya et al (Pub No. US20220328486A1) (hereinafter, Onuki).
Re Claim 4, (Currently Amended) Onuki teaches the method of claim 1, wherein the semiconductor layer (Conductor; 260a; Fig 11B; ¶[0175]; Note: Conductor 260a may be titanium) is more conductive than the semiconductor channel layer (Conductor; 242; Fig 2; ¶[0160]; Note: Conductor 242 may be ruthenium oxide, an oxide containing strontium or ruthenium, or an oxide containing lanthanum and nickel).
However, Onuki does not teach and the semiconductor layer and the semiconductor channel layer have a carrier density of about 1x 1014 /cm3 or more.
Onuki fails to disclose the exact carrier density as claimed.
Nevertheless, as depicted in Fig 2 such features (carrier density of semiconductor layers and semiconductor channel layer) must possess particular dimension. The choice of 1x 1014 /cm3 or more, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Onuki’s carrier density of the semiconductor layer and semiconductor channel layer to be 1x 1014 /cm3 or more, respectively, because this would be the best engineering design choice.
In addition, the selection of particular carrier density as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
11. Claims 5, 12, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Onuki, Tatsuya et al (Pub No. US20220328486A1) (hereinafter, Onuki) as applied to claims 4, 10 and 21, and further in view of Ishizu, Takahiko et al. (Pub No. US 20180075900 A1) (hereinafter, Ishizu).
Re Claim 5, (Previously Presented) Onuki does not teach the method of claim 4, wherein the semiconductor channel layer has a carrier density ranging from about 1x1014/cm3 to 1x1018/cm3, and the semiconductor layer has a carrier density of about 1x1019/cm3 or more.
However, the ordinary artisan would have recognized the semiconductor channel layer has a carrier density ranging from about 1x1014/cm3 to 1x1018/cm3, to be a result effective variable affecting oxygen plasma being blocked during microwave treatment to surrounding oxide regions, and furthermore the semiconductor layer has a carrier density of about 1x1019/cm3 or more such that oxygen diffusion to the source/drain electrode, adjacent to the semiconductor layer, can be suppressed given the higher carrier density. Thus, it would have been obvious to modify the carrier concentrations of the semiconductor channel layer and semiconductor layer, since optimum or workable ranges of such variables are discoverable through routine experimentation. (See MPEP 2144.05 II.B)
Re Claim 12, (Previously Presented) Onuki does not teach the method of claim 10, wherein the semiconductor layer is more conductive than the semiconductor channel layer.
Ishizu teaches the method of claim 10, wherein the semiconductor layer (Gate insulating layer; 5027; Fig 22B; ¶[0224]) is more conductive (Silicon Oxynitride is higher conductivity than at least one of the compounds of insulating layer 5032, i.e. Silicon Nitride; ¶[0219]) than the semiconductor channel layer (Insulating layer; 5032; Fig 22B; ¶[0219]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device as disclosed by Onuki by making the semiconductor layer more conductive than the semiconductor channel layer, as disclosed by Ishizu. One of ordinary skill in the art would have been motivated to make this modification in order reduce the parasitic capacitance between the gate and the source and the parasitic capacitance between the gate and the drais, so that the frequency characteristics can be improved, as suggested by Ishizu (¶[0227]).
Re Claim 23, (Previously Presented) Onuki does not teach the method of claim 21, wherein the semiconductor layer is more conductive than the semiconductor channel layer.
Ishizu teaches the method of claim 21, wherein the semiconductor layer (Gate insulating layer; 5027; Fig 22B; ¶[0224]) is more conductive (Silicon Oxynitride is higher conductivity than at least one of the compounds of insulating layer 5032, i.e. Silicon Nitride; ¶[0219]) than the semiconductor channel layer (Insulating layer; 5032; Fig 22B; ¶[0219]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device as disclosed by Onuki by making the semiconductor layer more conductive than the semiconductor channel layer, as disclosed by Ishizu. One of ordinary skill in the art would have been motivated to make this modification in order reduce the parasitic capacitance between the gate and the source and the parasitic capacitance between the gate and the drais, so that the frequency characteristics can be improved, as suggested by Ishizu (¶[0227]).
Conclusion
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817