DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 23, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-7, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0386012 A1 to Hsieh et al. (hereinafter “Hsieh” – previously cited reference).
Regarding claim 1, Hsieh discloses a static random access memory (SRAM) array pattern (SRAM 30 cell array formed by multiple SRAM cells 10; Fig. 1; paragraph [0019]), comprising:
a substrate, a first region, a second region, a third region and a fourth region are defined and arranged in an array (substrate 310 supporting SRAM 30 array having at least four regions respectively comprising SRAM cells 10_1 through 10_4; Fig. 3; paragraphs [0028], [0051]), wherein each region partially overlaps with the other three regions (each of the four regions having the SRAM cells 10_1 through 10_4 overlap with one another as shown in Fig. 3; paragraph [0028]);
each region comprises a static random access memory (SRAM) cell (each region comprises an SRAM memory cell 10; Fig 3; paragraph [0028]);
wherein a layout of the SRAM cell in the first region is the same as a layout of the SRAM cell in the third region (SRAM cell 10_1 arranged in same layout as SRAM cell 10_4 as shown in Fig. 3; paragraph [0028]), a layout of the SRAM cell in the second region is the same as a layout of the SRAM cell in the fourth region (SRAM cell 10_2 arranged in same layout as SRAM cell 10_3 as shown in Fig. 3; paragraph [0028]), and the layout of the SRAM cell in the first region and the layout of the SRAM cell in the fourth region are mirror patterns along a horizontal axis (SRAM cell 10_1 arranged in mirror pattern relative SRAM cell 10_3 across a horizontal axis X1-X as shown in Fig. 3; paragraph [0028]), wherein the SRAM cell located in the first region comprises at least one Vss contact electrically connected to a Vss voltage source (each SRAM cell 10 comprises a VSS contact electrically connected to a VSS voltage source; paragraph [0024]), the SRAM cell located in the first region comprises a first WL contact and a second WL contact electrically connected to a word line (SRAM cell 10_1 comprises first and second WL contacts connected via word line WL coupled to gate region of PG1 through gate contact 260_1 and gate electrode 130_3; Fig. 3; paragraphs [0032], [0040]), the SRAM cell located in the second region comprises the first WL contact and a third WL contact, wherein the SRAM cell in the first region and the SRAM cell in the second region share the first WL contact (SRAM cell 10_2 comprises first and third WL contacts with first WL contact being shared by cells 10_1, 10_2 as shown in Fig. 3; paragraphs [0032], [0040]), and the second WL contact and the third WL contact are aligned with each other along a horizontal direction (second and third WL contacts are aligned in a horizontal direction as shown in Fig. 3; paragraphs [0032], [0040]) and are electrically connected by a same word line metal layer (common word line WL for each of SRAM cells 10_1, 10_2 having first, second and third WL contacts; Fig. 3; paragraph [0040]), wherein the first WL contact, the second WL contact and the third WL contact are in direct contact with the same word line metal layer, and the word line metal layer extends along the horizontal direction (first, second and third WL contacts of SRAM cells 10_1, 10_2 contact the common word line WL of SRAM cells 10_1, 10_2 which extends at least in part in horizontal direction; Fig. 3; paragraph [0040]);
wherein each SRAM cell comprises a plurality of transistors, wherein the transistors at least comprise a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1) and a second access transistor (PG2) (each SRAM cell 10 comprises PU1, PD1, PU2, PD2, PG1 and PG2 as shown in Fig. 3; paragraph [0028]);
the SRAM array pattern further comprising a plurality of fin structures on the substrate, and a plurality of gate structures crossing each fin structure to form the transistors (semiconductor fins 110_1, 110_2 disposed upon substrate 310 with gate electrodes 130_3 overlapping as shown in Fig. 3; paragraphs [0031]-[0032], [0051]);
wherein in the first region, one of the gate structures spans two of the fin structures to form the first pull-down transistor (PD1) (fins 110_1, 110_2 overlapped by gate electrodes to form channel regions of PD1; Fig. 3, paragraph [0031]); and
wherein in the second region, one of the gate structures spans one of the fin structures to form the first pull-down transistor (PD1) (SRAM cell 10_2 identical to cell 10_1 in utilizing fins overlapped by gate electrodes to form channel regions of PD1 as shown in Fig. 3; paragraph [0031]).
Hsieh fails to explicitly disclose the first WL contact is aligned with the second and third WL contacts along the horizontal direction; and in the second region, one of the gate structures spans only a single one of the fin structures.
However, Hsieh already discloses the second WL contact and the third WL contact are aligned with each other along a horizontal direction (second and third WL contacts are aligned in a horizontal direction as shown in Fig. 3; paragraphs [0032], [0040]), and in a second region of a second group, one of the gate structures spans only a single one of the fin structures (group GP3 of SRAM 30 comprises gate electrode PG1 that spans only one fin structure 110_1 to form pull-down transistor PD1; Fig. 8; paragraphs [0022], [0070]).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Hsieh in this manner in order to potentially provide a simplified routing and interconnect patterns, reduced errors during mask generation, enhanced compatibility with advanced fabrication techniques, and consistent spacing between contacts to reduce parasitic effects. Further, alignment of the first word line contact along the horizontal direction requires only a simple rearrangement of an already-disclosed structure (first word line contact) in an already-disclosed manner (horizontal alignment of word line contacts) with respect to the second and third word line contacts. Moreover, as evidenced when comparing Figs. 3 and 8 of Hsieh, utilizing a gate structure that spans only one fin structure to form the pull-down transistor could provide higher cell density by reducing fin pitch which is critical for SRAM arrays where area dominates cost and capacity. Additionally, decreased device width could provide lower subthreshold leakage relative dual-fin structures and improved write margin given a single fin design provides weaker pull-down transistor making it easier to execute a write operation with a higher degree of sensitivity and control.
Regarding claim 2, Hsieh discloses the SRAM array pattern of claim 1. Hsieh further discloses the first region is aligned with the second region along the horizontal direction, and the first region is aligned with the fourth region in a vertical direction (SRAM cells 10_1 and 10_2 aligned along horizontal axis and SRAM cells 10_1 and 10_3 aligned along vertical direction as shown in Fig. 3; paragraph [0028]).
Regarding claim 3, Hsieh discloses the SRAM array pattern of claim 1. Hsieh further discloses the first region, the second region, the third region and the fourth region are arranged in a 2X2 array (SRAM cells 10_1 through 10_4 arranged in 2x2 array as shown in Fig. 3; paragraph [0028]), and the first region and the third region are located at both ends of a diagonal, while the second region and the fourth region are located at both ends of another diagonal (SRAM cells 10_1 and 10_4 and SRAM cells 10_2 and 10_3 are each disposed at diagonal ends of the 2x2 array as shown in Fig. 3; paragraph [0028]).
Regarding claim 5, Hsieh discloses the SRAM array pattern of claim 4. Hsieh further discloses the SRAM cell in the first region and the SRAM cell in the second region share the Vss contact and the first WL contact (WL shared by SRAM cells 10_1, 10_2 and VSS line 170_1 electrically coupled to first and second SRAM cells 10_1 and 10_2; abstract; paragraphs [0023], [0040], [0082]), and the Vss contact and the first WL contact are located in an overlapping range of the first region and the second region (VSS line 170_1 disposed in overlapping region as shown in Fig. 3 and WL shared by SRAM cells 10_1, 10_2 disposed in overlapping region at gate contact 260_4 as shown in Fig. 3; paragraphs [0023], [0038], [0040]).
Regarding claim 6, Hsieh discloses the SRAM array pattern of claim 4. Hsieh further discloses the SRAM cell in the first region and the SRAM cell in the third region share the Vss contact, but do not share the first WL contact, and the Vss contact is located in an overlapping range of the first region and the third region (VSS line 170_1 shared by SRAM cells 10_1, 10_4 and located in overlapping region as shown in Fig. 3, but WL only shared between SRAM cells 10_1, 10_2 as shown in Fig. 2A; abstract; paragraphs [0023], [0038], [0045], [0082]).
Regarding claim 7, Hsieh discloses the SRAM array pattern of claim 4. Hsieh further discloses the SRAM cell in the first region and the SRAM cell in the fourth region share the Vss contact, but do not share the first WL contact, and the Vss contact is located in an overlapping range of the first region and the fourth region (VSS line 170_1 shared by SRAM cells 10_1, 10_3 and located in overlapping region as shown in Fig. 3, but WL only shared between SRAM cells 10_1, 10_2 as shown in Fig. 2A; abstract; paragraphs [0023], [0038], [0045], [0082]).
Regarding claim 13, Hsieh discloses the SRAM array pattern of claim 1. Hsieh further discloses the first pull-up transistor (PU1), the first pull-down transistor (PD1), the second pull-up transistor (PU2), the second pull-down transistor (PD2), the first access transistor (PG1) and the second access transistor (PG2) are not located in an overlapping range of the first region and the second region (portions of each of PU1, PD1, PU2, PD2, PG1 and PG2 are not located in overlapping region of SRAM cells 10_1, 10_2 as shown in Fig. 3; paragraph [0028]).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in further view of US 2016/0064067 A1 to Mojumder et al. (hereinafter “Mojumder” – previously cited reference).
Regarding claim 11, Hsieh discloses the SRAM array pattern of claim 1. Hsieh further discloses wherein a width of the second region is defined as X1, and a pitch between the two fin structures is defined as X2 (SRAM cell 10_2 having width X-pitch-1 and a pitch between two fin structures as shown in Fig. 3; paragraphs [0031]-[0032]).
Hsieh fails to disclose wherein X1/X2 is equal to one of the following values: 10.75, 11, 11.25 and 11.5.
However, Mojumder discloses wherein X1/X2 is equal to one of the following values: 10.75, 11, 11.25 and 11.5 (bit cell width of 360 nm and a fin pitch within the range of 30-35 nm which provides ratio of about 10.25 to 12; paragraphs [0035]-[0036]).
Hsieh and Mojumder are both considered to be analogous to the claimed invention because they are in the same field of SRAM array layouts. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Hsieh to incorporate the teaching of Mojumder in order to optimize area efficiency, tune performance, manage process variability, and increase power efficiency.
Regarding claim 12, Hsieh in view of Mojumder discloses the SRAM array pattern of claim 11. Hsieh further discloses wherein an area of first region and an area of the second region are same with each other (area of SRAM cells 10 1,10 2 are the same as shown in Fig. 3; paragraph [0028)).
Response to Arguments
Applicant's arguments filed July 23, 2026 have been fully considered. Applicant presents substantive amendments to claim 1 and related arguments. Specifically, Applicant argues that amended claim 1 overcomes the 35 USC 103 rejection using Hsieh given that “in every SRAM cell of Hsieh, the first pull-down transistor (PD1) is formed by a gate structure spanning two fin structures, and Hsieh does not disclose any cell in which the first pull-down transistor is formed by only a single fin structure.” Applicant emphasized this quoted portion of their remarks using bolded font, but this statement is respectively traversed. Fig. 8 of Hsieh (or the identical Fig. 8 of US 10,411,022 B1 cited by Applicant in their recently submitted IDS) explicitly discloses PG1 130_3 spanning only a single fin 110_1 to form PD1. This group GP3 is a part of the same SRAM 30 as that cited to in Fig. 3 of the existing rejection (see Hsieh, Fig. 1 and paragraph [0022]). Therefore, amended claim 1 remains obvious over Hsieh.
Conclusion
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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